Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28703 1 T4 2 T5 8 T6 2
auto[1] 27728 1 T5 4 T7 16 T8 106


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28973 1 T4 2 T5 8 T6 2
auto[1] 27458 1 T5 4 T7 18 T8 89


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27515 1 T5 6 T7 22 T8 101
auto[1] 28916 1 T4 2 T5 6 T6 2


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32176 1 T4 1 T5 6 T6 1
auto[1] 24255 1 T4 1 T5 6 T6 1


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27829 1 T5 2 T7 30 T8 82
auto[1] 28602 1 T4 2 T5 10 T6 2


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28838 1 T4 2 T5 8 T6 2
auto[1] 27593 1 T5 4 T7 10 T8 103


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1028 1 T7 1 T8 1 T26 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 758 1 T7 1 T26 2 T13 5
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1006 1 T7 2 T8 4 T26 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 728 1 T7 2 T8 2 T26 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 980 1 T5 1 T7 2 T8 3
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 731 1 T5 1 T7 2 T8 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1592 1 T4 1 T5 1 T6 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1385 1 T4 1 T5 1 T6 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 970 1 T5 1 T8 2 T26 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 726 1 T5 1 T8 2 T26 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 983 1 T8 4 T26 1 T41 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 744 1 T8 3 T26 1 T41 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 984 1 T7 1 T8 4 T41 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 741 1 T7 1 T8 4 T41 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 976 1 T8 1 T26 2 T13 4
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 713 1 T8 1 T26 2 T13 4
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 975 1 T7 2 T8 3 T26 3
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 734 1 T7 2 T8 2 T26 3
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 960 1 T7 1 T26 1 T13 6
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 720 1 T7 1 T26 1 T13 6
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 959 1 T26 3 T13 4 T38 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 708 1 T26 3 T13 3 T38 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1009 1 T5 1 T8 2 T13 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 770 1 T5 1 T8 2 T13 3
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 981 1 T7 1 T8 5 T26 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 745 1 T7 1 T8 4 T26 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1018 1 T7 1 T8 5 T26 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 737 1 T7 1 T8 3 T26 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 976 1 T8 3 T26 2 T13 4
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 720 1 T8 2 T26 2 T13 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 932 1 T8 2 T26 1 T41 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 714 1 T8 2 T26 1 T41 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 952 1 T7 2 T8 6 T13 3
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 713 1 T7 2 T8 5 T13 3
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1014 1 T8 1 T41 2 T13 4
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 784 1 T8 1 T41 2 T13 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 943 1 T5 1 T8 7 T26 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 717 1 T5 1 T8 6 T26 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 984 1 T7 1 T8 2 T26 4
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 741 1 T7 1 T8 2 T26 4
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1030 1 T8 1 T13 1 T14 3
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 785 1 T14 1 T24 4 T61 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1044 1 T7 1 T8 3 T26 3
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 778 1 T7 1 T8 3 T26 3
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 957 1 T8 4 T26 3 T13 4
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 729 1 T8 3 T26 3 T13 4
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1009 1 T8 4 T26 4 T13 6
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 748 1 T8 4 T26 4 T13 5
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1023 1 T7 1 T8 1 T26 3
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 743 1 T7 1 T8 1 T26 3
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 982 1 T7 2 T8 1 T26 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 754 1 T7 2 T8 1 T26 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1000 1 T8 6 T26 2 T41 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 746 1 T8 6 T26 2 T41 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 996 1 T8 2 T26 1 T41 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 703 1 T8 2 T26 1 T41 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1007 1 T7 1 T8 5 T13 4
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 745 1 T7 1 T8 5 T13 4
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 949 1 T8 4 T41 2 T13 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 713 1 T8 4 T41 2 T13 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 972 1 T8 4 T26 2 T41 2
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 737 1 T8 4 T26 2 T41 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 985 1 T5 1 T8 5 T26 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 745 1 T5 1 T8 3 T26 1

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