Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30041

1

T1

25

T2

4

T5

1

auto[1]

29355

1

T1

24

T2

2

T6

4

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30085

1

T1

21

T2

2

T5

1

auto[1]

29311

1

T1

28

T2

4

T6

6

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29056

1

T1

23

T5

1

T6

8

auto[1]

30340

1

T1

26

T2

6

T6

10

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33592

1

T1

41

T2

4

T5

1

auto[1]

25804

1

T1

8

T2

2

T6

9

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28979

1

T1

29

T2

2

T6

12

auto[1]

30417

1

T1

20

T2

4

T5

1

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30184

1

T1

21

T2

6

T6

10

auto[1]

29212

1

T1

28

T5

1

T6

8

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1065

1

T1

1

T13

3

T14

13

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

807

1

T13

3

T14

9

T35

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1046

1

T1

2

T2

1

T6

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

804

1

T1

2

T2

1

T6

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

995

1

T6

2

T13

5

T49

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

764

1

T6

2

T13

5

T49

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1609

1

T7

1

T9

1

T39

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1373

1

T7

1

T9

1

T39

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

951

1

T13

2

T14

5

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

696

1

T13

2

T14

5

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1015

1

T1

1

T13

1

T14

12

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

777

1

T13

1

T14

9

T35

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

981

1

T1

1

T5

1

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

729

1

T6

1

T13

2

T14

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1036

1

T13

3

T14

15

T36

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

790

1

T13

2

T14

13

T36

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1028

1

T1

2

T13

4

T14

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

790

1

T13

4

T14

10

T35

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1019

1

T1

2

T13

1

T14

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

783

1

T13

1

T14

10

T35

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1045

1

T1

2

T13

3

T14

13

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

790

1

T1

1

T13

2

T14

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1035

1

T2

2

T13

2

T14

15

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

799

1

T13

2

T14

14

T35

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1047

1

T1

3

T6

1

T13

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

814

1

T1

2

T6

1

T13

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

979

1

T1

4

T6

1

T13

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

745

1

T1

1

T6

1

T13

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1063

1

T1

1

T14

8

T35

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

820

1

T14

7

T35

1

T36

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1048

1

T13

3

T14

14

T35

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

798

1

T13

3

T14

13

T35

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1015

1

T1

1

T13

1

T49

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

790

1

T13

1

T49

1

T14

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1054

1

T1

2

T6

1

T13

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

805

1

T6

1

T13

1

T14

14

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

987

1

T1

2

T13

1

T14

16

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

735

1

T14

14

T35

2

T36

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1035

1

T13

5

T49

1

T14

11

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

774

1

T13

5

T49

1

T14

11

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1031

1

T1

1

T13

6

T14

14

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

813

1

T13

6

T14

13

T35

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1028

1

T1

2

T13

2

T14

16

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

797

1

T13

2

T14

14

T36

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1084

1

T1

4

T13

2

T49

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

846

1

T13

2

T49

1

T14

16

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1048

1

T1

2

T13

1

T14

12

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

805

1

T13

1

T14

9

T35

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

995

1

T13

3

T49

1

T14

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

773

1

T13

3

T49

1

T14

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1031

1

T1

1

T13

3

T14

12

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

769

1

T13

3

T14

11

T35

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1094

1

T1

1

T13

1

T14

16

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

821

1

T13

1

T14

15

T36

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

991

1

T1

2

T2

1

T14

8

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

763

1

T2

1

T14

7

T35

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1037

1

T1

1

T13

4

T14

18

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

800

1

T13

4

T14

14

T36

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1059

1

T1

1

T6

1

T13

7

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

816

1

T6

1

T13

5

T14

17

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1055

1

T13

4

T14

8

T35

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

795

1

T13

4

T14

7

T35

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1086

1

T1

2

T13

1

T14

9

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

823

1

T1

2

T13

1

T14

7