Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32057

1

T2

40

T3

4

T4

14

auto[1]

30128

1

T2

60

T3

2

T4

6

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31857

1

T2

58

T3

2

T4

12

auto[1]

30328

1

T2

42

T3

4

T4

8

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30444

1

T2

50

T3

5

T4

14

auto[1]

31741

1

T2

50

T3

1

T4

6

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35327

1

T2

50

T3

4

T4

10

auto[1]

26858

1

T2

50

T3

2

T4

10

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30400

1

T2

48

T3

3

T4

8

auto[1]

31785

1

T2

52

T3

3

T4

12

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31624

1

T2

48

T3

3

T4

8

auto[1]

30561

1

T2

52

T3

3

T4

12

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1100

1

T3

1

T10

1

T16

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

812

1

T3

1

T10

1

T28

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1061

1

T2

3

T7

1

T8

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

799

1

T2

3

T8

1

T10

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1109

1

T2

2

T4

2

T10

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

855

1

T2

2

T4

2

T10

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1750

1

T2

1

T8

1

T10

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1471

1

T2

1

T10

2

T28

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1145

1

T2

1

T8

1

T15

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

882

1

T2

1

T28

2

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1104

1

T2

1

T16

1

T28

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

824

1

T2

1

T28

2

T40

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1128

1

T2

1

T4

2

T28

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

852

1

T2

1

T4

2

T28

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1124

1

T2

2

T8

1

T15

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

846

1

T2

2

T28

2

T40

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1048

1

T2

1

T10

3

T28

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

805

1

T2

1

T10

3

T28

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1017

1

T2

1

T8

1

T10

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

782

1

T2

1

T8

1

T10

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1103

1

T2

2

T7

1

T10

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

839

1

T2

2

T10

2

T28

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1109

1

T4

1

T10

2

T16

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

861

1

T4

1

T10

2

T28

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1069

1

T2

2

T4

1

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

825

1

T2

2

T4

1

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1162

1

T2

2

T4

1

T10

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

855

1

T2

2

T4

1

T10

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1099

1

T3

1

T15

1

T40

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

793

1

T3

1

T40

1

T25

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1035

1

T2

1

T10

3

T15

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

793

1

T2

1

T10

3

T28

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1058

1

T2

2

T4

1

T8

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

785

1

T2

2

T4

1

T10

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1056

1

T2

5

T8

1

T10

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

769

1

T2

5

T10

3

T40

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1055

1

T2

2

T8

1

T28

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

814

1

T2

2

T28

3

T40

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1092

1

T2

2

T10

1

T16

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

830

1

T2

2

T10

1

T28

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1104

1

T4

1

T8

2

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

837

1

T4

1

T8

1

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1069

1

T7

1

T8

2

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

818

1

T8

1

T10

1

T28

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1066

1

T2

5

T10

2

T15

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

803

1

T2

5

T10

2

T28

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1046

1

T2

2

T8

1

T10

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

793

1

T2

2

T10

1

T41

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1088

1

T2

1

T8

1

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

811

1

T2

1

T10

2

T40

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1121

1

T8

1

T10

2

T16

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

855

1

T10

2

T28

1

T40

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1071

1

T2

1

T3

1

T8

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

808

1

T2

1

T10

4

T28

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1068

1

T2

1

T15

1

T28

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

822

1

T2

1

T28

4

T40

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1045

1

T2

2

T10

1

T28

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

772

1

T2

2

T10

1

T28

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1093

1

T2

3

T3

1

T10

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

829

1

T2

3

T10

2

T21

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1067

1

T2

3

T8

2

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

796

1

T2

3

T10

1

T28

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1065

1

T2

1

T4

1

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

822

1

T2

1

T4

1

T8

1