Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31233 1 T3 50 T5 48 T7 273
auto[1] 29972 1 T3 29 T5 52 T7 269


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31307 1 T3 44 T5 42 T7 265
auto[1] 29898 1 T3 35 T5 58 T7 277


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30195 1 T3 32 T5 54 T7 264
auto[1] 31010 1 T3 47 T5 46 T7 278


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34827 1 T3 63 T5 50 T7 320
auto[1] 26378 1 T3 16 T5 50 T7 222


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30024 1 T3 32 T5 54 T7 306
auto[1] 31181 1 T3 47 T5 46 T7 236


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31279 1 T3 40 T5 40 T7 269
auto[1] 29926 1 T3 39 T5 60 T7 273


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1157 1 T3 1 T7 9 T9 32
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 876 1 T3 1 T7 8 T9 23
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1048 1 T3 4 T5 3 T7 10
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 810 1 T3 2 T5 3 T7 7
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1097 1 T3 1 T5 1 T7 5
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 825 1 T5 1 T7 5 T9 8
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1722 1 T3 5 T7 15 T9 47
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1449 1 T3 1 T7 11 T9 38
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1110 1 T3 2 T5 2 T7 15
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 828 1 T3 1 T5 2 T7 9
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 976 1 T3 3 T7 11 T9 16
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 741 1 T3 2 T7 9 T9 9
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1069 1 T3 5 T5 1 T7 7
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 801 1 T5 1 T7 5 T9 15
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1051 1 T7 6 T9 26 T64 5
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 778 1 T7 6 T9 19 T64 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1034 1 T3 1 T5 3 T7 16
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 766 1 T5 3 T7 10 T8 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1091 1 T3 2 T5 1 T7 13
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 804 1 T5 1 T7 8 T9 19
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1066 1 T3 3 T5 4 T7 9
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 791 1 T3 1 T5 4 T7 6
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1060 1 T3 4 T7 9 T9 32
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 796 1 T3 1 T7 6 T9 22
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1018 1 T5 3 T7 8 T8 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 750 1 T5 3 T7 6 T8 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1117 1 T3 1 T5 2 T7 8
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 860 1 T3 1 T5 2 T7 5
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1053 1 T3 2 T5 2 T7 7
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 812 1 T3 1 T5 2 T7 5
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1078 1 T3 4 T5 2 T7 11
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 799 1 T3 1 T5 2 T7 8
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1043 1 T3 2 T7 11 T9 24
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 794 1 T7 6 T9 18 T64 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1060 1 T3 1 T5 2 T7 9
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 792 1 T5 2 T7 4 T8 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1081 1 T7 4 T9 29 T39 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 810 1 T7 2 T9 17 T39 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1068 1 T3 2 T5 2 T7 10
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 822 1 T3 1 T5 2 T7 7
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1079 1 T3 1 T5 4 T7 12
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 830 1 T5 4 T7 6 T9 15
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1042 1 T3 2 T5 2 T7 13
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 807 1 T5 2 T7 9 T8 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1114 1 T3 3 T7 14 T8 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 854 1 T7 10 T8 2 T9 16
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1016 1 T3 3 T5 4 T7 6
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 757 1 T3 1 T5 4 T7 4
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1093 1 T3 1 T5 1 T7 9
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 812 1 T5 1 T7 7 T9 11
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1059 1 T3 1 T5 2 T7 12
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 822 1 T5 2 T7 10 T8 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 995 1 T3 3 T5 1 T7 11
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 746 1 T5 1 T7 7 T8 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1087 1 T3 1 T7 8 T9 24
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 803 1 T3 1 T7 5 T9 16
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1147 1 T3 1 T5 1 T7 12
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 845 1 T5 1 T7 10 T9 24
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1036 1 T3 2 T5 1 T7 15
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 777 1 T5 1 T7 9 T8 2
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1089 1 T3 1 T5 4 T7 7
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 810 1 T3 1 T5 4 T7 6
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1071 1 T3 1 T5 2 T7 8
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 811 1 T5 2 T7 6 T9 23

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