Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32561

1

T1

2

T2

2

T3

46

auto[1]

31162

1

T3

54

T4

27

T5

50

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32591

1

T1

2

T2

2

T3

54

auto[1]

31132

1

T3

46

T4

21

T5

52

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31162

1

T3

54

T4

24

T5

61

auto[1]

32561

1

T1

2

T2

2

T3

46

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36450

1

T1

1

T2

1

T3

50

auto[1]

27273

1

T1

1

T2

1

T3

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31345

1

T3

44

T4

18

T5

52

auto[1]

32378

1

T1

2

T2

2

T3

56

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32623

1

T1

2

T2

2

T3

40

auto[1]

31100

1

T3

60

T4

21

T5

48

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1073

1

T4

1

T5

3

T8

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

809

1

T5

2

T8

1

T14

15

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1107

1

T3

1

T4

1

T5

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

825

1

T3

1

T5

1

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1118

1

T3

2

T4

2

T5

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

847

1

T3

2

T5

1

T8

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1786

1

T1

1

T2

1

T3

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1484

1

T1

1

T2

1

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1146

1

T3

1

T4

1

T8

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

862

1

T3

1

T8

1

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1159

1

T3

1

T4

1

T5

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

844

1

T3

1

T4

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1106

1

T3

3

T4

1

T5

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

847

1

T3

3

T5

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1087

1

T3

2

T5

2

T8

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

819

1

T3

2

T5

2

T14

18

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1097

1

T3

2

T4

1

T5

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

811

1

T3

2

T5

4

T14

19

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1174

1

T3

1

T4

2

T14

26

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

862

1

T3

1

T14

18

T36

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1177

1

T4

2

T5

1

T8

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

853

1

T4

1

T5

1

T14

22

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1160

1

T3

3

T5

2

T8

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

836

1

T3

3

T5

2

T14

13

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1163

1

T3

1

T4

1

T5

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

869

1

T3

1

T5

3

T14

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1114

1

T3

2

T8

4

T14

18

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

821

1

T3

2

T14

14

T15

18

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1086

1

T3

3

T4

2

T5

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

789

1

T3

3

T4

1

T5

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1043

1

T8

1

T14

13

T36

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

787

1

T14

10

T36

2

T15

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1072

1

T3

1

T4

1

T5

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

781

1

T3

1

T5

1

T8

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1123

1

T3

1

T4

1

T5

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

842

1

T3

1

T5

3

T14

9

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1109

1

T3

2

T4

3

T5

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

814

1

T3

2

T5

2

T14

15

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1155

1

T4

3

T5

2

T14

22

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

857

1

T4

1

T5

1

T14

16

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1122

1

T3

5

T4

1

T5

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

825

1

T3

5

T5

1

T8

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1164

1

T3

2

T4

2

T5

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

878

1

T3

2

T4

1

T5

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1140

1

T3

1

T4

1

T5

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

844

1

T3

1

T5

1

T14

20

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1123

1

T3

4

T4

2

T5

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

823

1

T3

4

T5

2

T14

14

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1132

1

T3

1

T4

2

T5

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

853

1

T3

1

T5

1

T14

15

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1118

1

T3

1

T5

2

T8

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

827

1

T3

1

T5

1

T14

15

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1105

1

T3

2

T4

1

T5

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

844

1

T3

2

T4

1

T5

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1126

1

T3

2

T4

1

T8

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

846

1

T3

2

T8

1

T10

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1107

1

T3

1

T5

3

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

840

1

T3

1

T5

2

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1089

1

T3

1

T4

1

T5

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

836

1

T3

1

T5

2

T14

9

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1104

1

T3

2

T4

1

T5

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

817

1

T3

2

T5

4

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1065

1

T3

1

T4

3

T14

18

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

781

1

T3

1

T4

1

T14

11