Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36411

1

T4

732

T6

4

T10

8

auto[1]

34075

1

T4

670

T10

4

T21

4

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35874

1

T4

657

T6

3

T10

4

auto[1]

34612

1

T4

745

T6

1

T10

8

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34649

1

T4

665

T6

2

T10

10

auto[1]

35837

1

T4

737

T6

2

T10

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40188

1

T4

807

T6

4

T10

6

auto[1]

30298

1

T4

595

T10

6

T21

5

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34668

1

T4

707

T6

2

T10

8

auto[1]

35818

1

T4

695

T6

2

T10

4

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36130

1

T4

720

T6

2

T10

6

auto[1]

34356

1

T4

682

T6

2

T10

6

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1249

1

T4

29

T22

1

T35

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

932

1

T4

18

T22

1

T35

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1261

1

T4

25

T21

1

T13

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

938

1

T4

19

T21

1

T22

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1241

1

T4

27

T13

1

T22

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

915

1

T4

15

T22

2

T83

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

2018

1

T4

49

T6

1

T82

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1689

1

T4

40

T82

2

T43

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1217

1

T4

20

T10

1

T37

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

913

1

T4

16

T10

1

T37

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1233

1

T4

17

T6

1

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

917

1

T4

14

T10

1

T37

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1274

1

T4

24

T6

1

T13

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

948

1

T4

16

T22

1

T35

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1244

1

T4

21

T21

1

T37

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

920

1

T4

14

T21

1

T37

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1236

1

T4

28

T6

1

T82

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

943

1

T4

19

T82

1

T22

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1244

1

T4

29

T22

1

T83

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

936

1

T4

22

T22

1

T83

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1195

1

T4

20

T10

2

T22

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

911

1

T4

14

T10

2

T22

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1235

1

T4

19

T56

1

T36

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

929

1

T4

15

T56

1

T36

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1286

1

T4

26

T37

1

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

981

1

T4

19

T37

1

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1261

1

T4

33

T37

1

T13

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

949

1

T4

28

T37

1

T22

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1257

1

T4

28

T21

1

T82

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

936

1

T4

16

T21

1

T82

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1263

1

T4

30

T13

1

T22

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

940

1

T4

22

T22

2

T83

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1220

1

T4

15

T37

1

T82

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

924

1

T4

12

T37

1

T82

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1218

1

T4

20

T21

1

T83

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

932

1

T4

16

T21

1

T83

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1240

1

T4

20

T37

3

T82

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

927

1

T4

14

T37

3

T82

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1216

1

T4

20

T37

1

T22

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

910

1

T4

15

T37

1

T22

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1221

1

T4

26

T82

1

T22

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

903

1

T4

19

T82

1

T22

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1206

1

T4

29

T35

1

T36

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

883

1

T4

20

T35

1

T36

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1186

1

T4

19

T21

1

T13

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

881

1

T4

12

T21

1

T22

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1189

1

T4

22

T22

1

T83

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

909

1

T4

14

T22

1

T83

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1310

1

T4

27

T10

1

T37

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

976

1

T4

22

T10

1

T37

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1191

1

T4

26

T22

3

T35

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

925

1

T4

22

T22

3

T35

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1264

1

T4

29

T13

2

T35

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

949

1

T4

22

T35

1

T36

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1177

1

T4

32

T82

2

T22

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

879

1

T4

20

T82

2

T22

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1212

1

T4

26

T10

1

T56

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

899

1

T4

23

T10

1

T56

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1233

1

T4

22

T22

3

T83

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

919

1

T4

20

T22

3

T83

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1204

1

T4

25

T82

1

T22

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

899

1

T4

19

T82

1

T22

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1187

1

T4

24

T13

1

T22

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

886

1

T4

18

T22

1

T83

2