Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34754

1

T1

16

T4

10

T5

2

auto[1]

33605

1

T1

16

T4

26

T5

1

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34788

1

T1

16

T4

10

T6

92

auto[1]

33571

1

T1

16

T4

26

T5

3

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33592

1

T1

22

T4

24

T5

2

auto[1]

34767

1

T1

10

T4

12

T5

1

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39211

1

T1

16

T4

18

T5

3

auto[1]

29148

1

T1

16

T4

18

T6

69

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33665

1

T1

18

T4

16

T5

3

auto[1]

34694

1

T1

14

T4

20

T6

97

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35084

1

T1

18

T4

10

T6

91

auto[1]

33275

1

T1

14

T4

26

T5

3

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1219

1

T1

1

T6

2

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

869

1

T1

1

T8

1

T18

18

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1166

1

T6

5

T18

18

T19

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

848

1

T6

5

T18

13

T19

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1194

1

T6

4

T14

1

T18

20

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

887

1

T6

2

T18

17

T19

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1943

1

T1

1

T6

7

T7

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1600

1

T1

1

T6

7

T18

26

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1199

1

T4

1

T6

2

T7

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

899

1

T4

1

T6

1

T18

15

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1202

1

T6

2

T7

2

T18

25

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

905

1

T6

2

T7

1

T18

18

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1180

1

T4

1

T6

1

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

871

1

T4

1

T18

22

T19

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1219

1

T1

1

T6

5

T7

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

888

1

T1

1

T7

1

T18

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1214

1

T1

1

T4

1

T6

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

909

1

T1

1

T4

1

T6

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1184

1

T6

5

T18

23

T19

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

898

1

T6

1

T18

15

T19

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1195

1

T1

1

T6

3

T7

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

899

1

T1

1

T6

3

T18

20

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1165

1

T6

2

T7

2

T18

29

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

876

1

T6

2

T7

1

T18

22

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1183

1

T1

2

T5

1

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

869

1

T1

2

T6

1

T18

12

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1247

1

T5

1

T6

2

T7

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

933

1

T7

1

T9

1

T18

14

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1219

1

T6

4

T7

1

T18

21

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

910

1

T6

1

T18

17

T19

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1148

1

T1

1

T4

2

T6

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

816

1

T1

1

T4

2

T6

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1267

1

T1

3

T6

4

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

941

1

T1

3

T6

2

T18

16

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1218

1

T6

3

T7

2

T18

24

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

905

1

T6

1

T18

15

T19

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1195

1

T1

1

T6

4

T7

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

883

1

T1

1

T6

2

T18

17

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1204

1

T6

3

T18

24

T19

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

887

1

T6

2

T18

18

T19

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1209

1

T1

1

T6

5

T7

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

878

1

T1

1

T6

5

T18

11

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1206

1

T4

2

T6

4

T18

15

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

872

1

T4

2

T6

2

T18

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1167

1

T4

1

T6

4

T7

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

863

1

T4

1

T6

3

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1146

1

T6

2

T18

25

T19

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

858

1

T6

1

T18

21

T19

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1214

1

T1

1

T6

2

T7

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

904

1

T1

1

T6

1

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1199

1

T6

3

T14

1

T18

28

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

913

1

T6

1

T18

17

T19

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1205

1

T4

3

T6

1

T18

21

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

916

1

T4

3

T18

17

T19

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1255

1

T4

1

T6

4

T8

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

912

1

T4

1

T6

4

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1249

1

T4

3

T5

1

T6

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

901

1

T4

3

T6

4

T18

16

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1178

1

T4

1

T6

1

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

867

1

T4

1

T18

11

T19

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1198

1

T4

2

T6

6

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

886

1

T4

2

T6

6

T18

14

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1224

1

T1

2

T6

4

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

885

1

T1

2

T6

4

T18

10