Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31019

1

T2

10

T6

12

T9

125

auto[1]

30271

1

T2

30

T6

6

T9

127

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31333

1

T2

24

T6

10

T9

129

auto[1]

29957

1

T2

16

T6

8

T9

123

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30105

1

T2

20

T6

8

T9

131

auto[1]

31185

1

T2

20

T6

10

T9

121

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34713

1

T2

20

T6

9

T9

138

auto[1]

26577

1

T2

20

T6

9

T9

114

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29816

1

T2

20

T6

6

T9

123

auto[1]

31474

1

T2

20

T6

12

T9

129

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31168

1

T2

24

T6

12

T9

129

auto[1]

30122

1

T2

16

T6

6

T9

123

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1027

1

T9

3

T10

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

774

1

T9

3

T10

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1072

1

T6

2

T9

2

T10

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

817

1

T6

2

T9

1

T38

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1112

1

T2

1

T9

7

T38

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

847

1

T2

1

T9

4

T38

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1697

1

T2

1

T9

7

T38

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1439

1

T2

1

T9

6

T38

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1090

1

T9

5

T10

2

T38

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

826

1

T9

4

T38

1

T63

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1012

1

T2

1

T9

5

T10

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

780

1

T2

1

T9

5

T10

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1044

1

T9

3

T10

4

T38

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

807

1

T9

1

T10

2

T38

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1016

1

T6

1

T9

3

T10

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

796

1

T6

1

T9

3

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1029

1

T9

7

T10

3

T38

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

786

1

T9

6

T38

1

T63

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1067

1

T6

1

T9

3

T38

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

812

1

T6

1

T9

1

T38

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1024

1

T2

1

T6

2

T9

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

759

1

T2

1

T6

2

T9

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1071

1

T9

2

T10

2

T14

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

783

1

T9

2

T10

1

T39

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1068

1

T9

3

T10

1

T38

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

799

1

T9

3

T10

1

T38

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1029

1

T9

6

T38

1

T63

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

777

1

T9

5

T38

1

T63

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1112

1

T9

6

T10

1

T38

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

852

1

T9

5

T38

2

T39

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1066

1

T2

1

T9

4

T10

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

829

1

T2

1

T9

4

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1055

1

T2

2

T9

4

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

798

1

T2

2

T9

4

T38

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1086

1

T2

1

T9

3

T10

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

832

1

T2

1

T9

3

T10

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1046

1

T2

1

T6

1

T9

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

800

1

T2

1

T6

1

T9

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1100

1

T2

1

T9

6

T10

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

813

1

T2

1

T9

5

T38

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1067

1

T2

2

T9

5

T10

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

811

1

T2

2

T9

3

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1038

1

T9

4

T10

1

T38

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

814

1

T9

2

T10

1

T38

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1130

1

T2

1

T6

1

T9

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

870

1

T2

1

T6

1

T9

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1089

1

T2

1

T9

7

T10

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

828

1

T2

1

T9

7

T38

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1026

1

T2

1

T9

5

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

783

1

T2

1

T9

5

T10

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1079

1

T2

2

T9

6

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

825

1

T2

2

T9

5

T38

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1115

1

T9

7

T10

1

T38

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

868

1

T9

7

T38

2

T14

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1039

1

T2

1

T9

1

T10

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

787

1

T2

1

T38

1

T40

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1092

1

T9

3

T10

3

T38

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

819

1

T9

3

T38

2

T64

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1095

1

T2

1

T9

3

T10

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

831

1

T2

1

T9

3

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1062

1

T2

1

T9

3

T10

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

807

1

T2

1

T9

2

T38

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1058

1

T6

1

T9

4

T10

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

808

1

T6

1

T9

3

T10

2