Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29113

1

T3

20

T4

4

T6

6

auto[1]

27534

1

T3

20

T4

2

T8

6

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28989

1

T3

26

T4

4

T6

4

auto[1]

27658

1

T3

14

T4

2

T6

2

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27680

1

T3

16

T4

4

T6

4

auto[1]

28967

1

T3

24

T4

2

T6

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32430

1

T3

20

T4

3

T6

3

auto[1]

24217

1

T3

20

T4

3

T6

3

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27736

1

T3

28

T4

6

T8

12

auto[1]

28911

1

T3

12

T6

6

T8

14

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29106

1

T3

14

T4

4

T6

2

auto[1]

27541

1

T3

26

T4

2

T6

4

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

963

1

T3

2

T4

1

T26

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

722

1

T3

2

T4

1

T26

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

988

1

T3

1

T8

1

T26

6

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

776

1

T3

1

T8

1

T26

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1011

1

T6

1

T8

2

T26

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

777

1

T6

1

T8

2

T26

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1616

1

T9

1

T22

1

T26

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1374

1

T9

1

T22

1

T26

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

924

1

T3

2

T9

2

T29

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

705

1

T3

2

T9

2

T29

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1025

1

T4

1

T8

1

T26

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

765

1

T4

1

T8

1

T26

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1017

1

T8

1

T26

3

T29

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

759

1

T8

1

T26

3

T29

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1000

1

T3

1

T6

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

721

1

T3

1

T6

1

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1008

1

T3

1

T8

1

T9

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

720

1

T3

1

T8

1

T9

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

965

1

T9

1

T26

3

T29

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

730

1

T9

1

T26

3

T29

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1046

1

T26

1

T29

1

T27

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

774

1

T26

1

T29

1

T27

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1010

1

T8

2

T9

1

T26

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

755

1

T8

2

T9

1

T26

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1006

1

T3

1

T9

2

T26

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

742

1

T3

1

T9

2

T26

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1030

1

T3

1

T9

1

T26

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

763

1

T3

1

T9

1

T26

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1008

1

T3

1

T6

1

T26

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

740

1

T3

1

T6

1

T26

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

966

1

T8

1

T48

1

T27

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

707

1

T8

1

T48

1

T27

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1044

1

T9

1

T26

3

T29

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

759

1

T9

1

T26

3

T29

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1014

1

T3

2

T8

2

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

761

1

T3

2

T8

2

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

979

1

T13

5

T28

1

T14

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

728

1

T13

5

T28

1

T14

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1008

1

T3

1

T9

1

T26

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

733

1

T3

1

T9

1

T26

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1003

1

T9

1

T26

2

T27

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

747

1

T9

1

T26

2

T27

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

984

1

T3

3

T27

2

T13

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

730

1

T3

3

T27

2

T13

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

982

1

T26

1

T48

1

T27

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

688

1

T26

1

T48

1

T27

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

967

1

T3

1

T26

2

T29

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

719

1

T3

1

T26

2

T29

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

961

1

T4

1

T9

1

T26

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

706

1

T4

1

T9

1

T26

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1059

1

T8

1

T9

1

T27

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

777

1

T8

1

T9

1

T27

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

960

1

T26

1

T27

2

T13

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

707

1

T26

1

T27

2

T13

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

959

1

T27

2

T13

6

T28

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

716

1

T27

2

T13

6

T28

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

981

1

T3

1

T26

3

T29

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

708

1

T3

1

T26

3

T29

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

961

1

T9

1

T26

2

T27

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

709

1

T9

1

T26

2

T27

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1039

1

T26

1

T27

2

T13

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

766

1

T26

1

T27

2

T13

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

946

1

T3

2

T9

1

T26

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

733

1

T3

2

T9

1

T26

1