Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32702

1

T2

16

T8

2

T9

22

auto[1]

31838

1

T2

16

T9

16

T12

62

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32936

1

T2

12

T8

2

T9

16

auto[1]

31604

1

T2

20

T9

22

T12

52

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31801

1

T2

12

T9

20

T12

41

auto[1]

32739

1

T2

20

T8

2

T9

18

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36752

1

T2

16

T8

1

T9

19

auto[1]

27788

1

T2

16

T8

1

T9

19

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31682

1

T2

16

T9

16

T12

44

auto[1]

32858

1

T2

16

T8

2

T9

22

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33221

1

T2

10

T8

2

T9

20

auto[1]

31319

1

T2

22

T9

18

T12

49

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1111

1

T23

1

T13

5

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

823

1

T23

1

T13

2

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1126

1

T12

1

T23

1

T13

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

847

1

T12

1

T23

1

T13

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1108

1

T9

1

T12

1

T23

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

846

1

T9

1

T12

1

T23

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1788

1

T2

1

T8

1

T12

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1513

1

T2

1

T8

1

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1131

1

T12

2

T23

1

T13

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

858

1

T12

1

T23

1

T13

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1120

1

T2

1

T9

1

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

839

1

T2

1

T9

1

T12

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1154

1

T2

1

T9

1

T12

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

845

1

T2

1

T9

1

T23

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1066

1

T2

1

T12

2

T13

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

778

1

T2

1

T12

1

T36

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1175

1

T2

1

T9

1

T23

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

880

1

T2

1

T9

1

T23

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1143

1

T9

1

T12

1

T23

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

833

1

T9

1

T12

1

T23

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1080

1

T9

1

T12

3

T23

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

823

1

T9

1

T12

3

T23

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1128

1

T2

1

T12

3

T35

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

849

1

T2

1

T12

3

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1125

1

T2

1

T9

1

T23

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

853

1

T2

1

T9

1

T23

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1099

1

T2

1

T9

2

T12

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

828

1

T2

1

T9

2

T12

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1150

1

T9

1

T23

4

T13

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

843

1

T9

1

T23

4

T13

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1094

1

T9

1

T12

1

T40

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

846

1

T9

1

T40

1

T35

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1166

1

T9

1

T12

1

T40

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

887

1

T9

1

T12

1

T23

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1095

1

T9

1

T23

2

T13

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

830

1

T9

1

T23

2

T41

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1146

1

T9

1

T12

1

T23

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

843

1

T9

1

T12

1

T23

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1126

1

T12

2

T13

1

T35

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

884

1

T12

2

T13

1

T35

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1121

1

T12

5

T23

1

T13

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

824

1

T12

3

T23

1

T13

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1174

1

T2

1

T12

2

T23

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

874

1

T2

1

T12

2

T23

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1171

1

T12

4

T23

1

T13

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

891

1

T12

4

T23

1

T13

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1107

1

T2

1

T9

2

T12

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

844

1

T2

1

T9

2

T23

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1195

1

T12

1

T13

7

T41

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

901

1

T12

1

T13

4

T41

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1145

1

T2

1

T12

3

T23

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

853

1

T2

1

T12

2

T23

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1127

1

T2

1

T9

2

T12

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

836

1

T2

1

T9

2

T12

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1203

1

T9

1

T12

4

T23

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

911

1

T9

1

T12

3

T23

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1090

1

T2

1

T12

1

T23

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

804

1

T2

1

T12

1

T23

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1106

1

T2

1

T12

5

T23

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

826

1

T2

1

T12

3

T23

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1136

1

T2

1

T23

1

T13

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

858

1

T2

1

T23

1

T13

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1046

1

T2

1

T12

3

T23

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

818

1

T2

1

T12

1

T23

2