Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33772

1

T2

46

T3

9

T5

44

auto[1]

32660

1

T2

54

T3

5

T5

56

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33758

1

T2

46

T3

7

T5

52

auto[1]

32674

1

T2

54

T3

7

T5

48

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32439

1

T2

52

T3

11

T5

48

auto[1]

33993

1

T2

48

T3

3

T5

52

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37894

1

T2

50

T3

14

T5

50

auto[1]

28538

1

T2

50

T5

50

T6

16

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32231

1

T2

56

T3

4

T5

36

auto[1]

34201

1

T2

44

T3

10

T5

64

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34191

1

T2

56

T3

5

T5

42

auto[1]

32241

1

T2

44

T3

9

T5

58

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1162

1

T2

2

T3

2

T5

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

875

1

T2

2

T5

1

T14

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1153

1

T2

3

T5

1

T6

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

861

1

T2

3

T5

1

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1162

1

T3

1

T5

1

T6

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

884

1

T5

1

T6

2

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1860

1

T2

1

T5

1

T7

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1552

1

T2

1

T5

1

T14

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1110

1

T2

2

T5

1

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

801

1

T2

2

T5

1

T54

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1154

1

T2

3

T5

1

T51

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

847

1

T2

3

T5

1

T51

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1133

1

T2

1

T3

1

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

867

1

T2

1

T6

1

T14

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1147

1

T2

1

T3

1

T5

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

851

1

T2

1

T5

4

T14

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1195

1

T6

1

T51

1

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

889

1

T6

1

T51

1

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1161

1

T2

3

T6

1

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

899

1

T2

3

T6

1

T7

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1175

1

T2

1

T5

1

T14

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

899

1

T2

1

T5

1

T14

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1167

1

T2

1

T5

1

T51

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

890

1

T2

1

T5

1

T51

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1109

1

T2

2

T3

2

T5

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

830

1

T2

2

T5

5

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1183

1

T2

1

T5

1

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

897

1

T2

1

T5

1

T6

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1120

1

T3

1

T6

2

T14

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

833

1

T6

2

T14

1

T15

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1188

1

T2

2

T3

1

T5

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

918

1

T2

2

T5

4

T6

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1174

1

T2

4

T5

1

T14

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

856

1

T2

4

T5

1

T14

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1174

1

T2

3

T5

2

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

872

1

T2

3

T5

2

T14

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1205

1

T3

1

T5

3

T6

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

916

1

T5

3

T6

1

T51

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1140

1

T2

1

T5

2

T6

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

856

1

T2

1

T5

2

T6

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1114

1

T2

1

T5

2

T51

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

848

1

T2

1

T5

2

T51

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1153

1

T51

1

T54

4

T15

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

836

1

T51

1

T15

3

T16

11

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1212

1

T2

1

T3

1

T5

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

909

1

T2

1

T5

3

T14

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1179

1

T5

3

T54

3

T15

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

895

1

T5

3

T54

1

T15

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1110

1

T2

3

T5

1

T54

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

832

1

T2

3

T5

1

T15

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1232

1

T5

1

T14

1

T40

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

888

1

T5

1

T14

1

T54

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1180

1

T2

4

T3

1

T5

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

883

1

T2

4

T5

2

T14

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1193

1

T2

2

T5

3

T51

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

896

1

T2

2

T5

3

T51

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1201

1

T51

1

T54

1

T15

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

906

1

T51

1

T15

3

T16

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1107

1

T2

1

T5

1

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

802

1

T2

1

T5

1

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1168

1

T2

5

T3

1

T5

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

881

1

T2

5

T5

3

T6

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1173

1

T2

2

T3

1

T5

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

869

1

T2

2

T5

1

T14

1