Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32839 1 T1 8 T4 2 T5 56
auto[1] 31551 1 T1 6 T4 4 T5 34


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33108 1 T1 12 T4 4 T5 46
auto[1] 31282 1 T1 2 T4 2 T5 44


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31377 1 T1 10 T4 5 T5 38
auto[1] 33013 1 T1 4 T4 1 T5 52


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36299 1 T1 7 T4 4 T5 73
auto[1] 28091 1 T1 7 T4 2 T5 17


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31552 1 T1 12 T4 3 T5 39
auto[1] 32838 1 T1 2 T4 3 T5 51


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32612 1 T1 6 T4 1 T5 50
auto[1] 31778 1 T1 8 T4 5 T5 40


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1152 1 T1 2 T5 1 T6 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 876 1 T1 2 T6 2 T9 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1108 1 T5 6 T6 1 T24 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 869 1 T5 2 T6 1 T24 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1069 1 T1 1 T5 1 T9 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 809 1 T1 1 T5 1 T9 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1874 1 T5 4 T9 1 T42 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1590 1 T5 1 T9 1 T42 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1092 1 T5 2 T9 3 T14 6
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 839 1 T5 1 T9 3 T14 4
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1088 1 T1 1 T5 3 T7 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 864 1 T1 1 T5 1 T7 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1129 1 T5 5 T9 3 T14 12
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 868 1 T5 1 T9 3 T14 10
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1107 1 T5 1 T9 3 T24 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 834 1 T9 3 T24 1 T74 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1053 1 T5 3 T6 1 T9 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 849 1 T6 1 T9 1 T24 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1105 1 T5 3 T9 4 T24 3
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 857 1 T5 1 T9 4 T24 3
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1078 1 T4 1 T5 3 T9 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 844 1 T5 1 T9 2 T24 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1110 1 T5 3 T9 1 T24 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 861 1 T5 1 T9 1 T24 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1159 1 T5 1 T7 1 T24 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 878 1 T7 1 T24 1 T14 7
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1085 1 T4 1 T5 1 T7 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 831 1 T7 1 T24 2 T14 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1095 1 T5 1 T8 1 T9 3
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 830 1 T5 1 T8 1 T9 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1152 1 T5 5 T24 1 T14 8
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 884 1 T5 2 T24 1 T14 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1102 1 T5 2 T6 1 T24 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 878 1 T6 1 T24 2 T14 5
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1132 1 T5 2 T9 2 T24 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 846 1 T9 2 T24 1 T14 4
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1060 1 T5 1 T9 2 T24 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 837 1 T9 2 T24 2 T14 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1100 1 T5 2 T9 2 T24 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 839 1 T9 2 T24 1 T14 4
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1175 1 T1 1 T4 1 T5 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 904 1 T1 1 T4 1 T6 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1200 1 T1 1 T5 2 T6 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 912 1 T1 1 T6 1 T9 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1097 1 T4 1 T5 2 T6 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 886 1 T4 1 T6 1 T24 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1111 1 T5 3 T6 1 T9 4
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 861 1 T5 1 T6 1 T9 4
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1099 1 T5 2 T6 1 T9 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 834 1 T5 2 T6 1 T9 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1037 1 T5 1 T9 2 T24 3
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 763 1 T9 2 T24 3 T14 3
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1125 1 T5 3 T8 1 T24 4
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 876 1 T24 4 T14 3 T16 9
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1131 1 T5 4 T6 1 T9 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 849 1 T6 1 T9 2 T24 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1110 1 T1 1 T7 1 T9 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 865 1 T1 1 T7 1 T9 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1121 1 T5 2 T24 1 T14 8
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 869 1 T24 1 T14 5 T16 15
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1067 1 T5 2 T8 1 T9 4
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 842 1 T5 1 T9 4 T24 3
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1176 1 T5 1 T6 1 T9 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 847 1 T6 1 T9 1 T24 1

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