Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34272 1 T3 41 T4 6 T6 44
auto[1] 32907 1 T3 31 T4 1 T6 56


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34389 1 T3 45 T4 2 T6 38
auto[1] 32790 1 T3 27 T4 5 T6 62


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32541 1 T3 37 T4 5 T6 46
auto[1] 34638 1 T3 35 T4 2 T6 54


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 38363 1 T3 58 T4 7 T6 50
auto[1] 28816 1 T3 14 T6 50 T9 10


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32944 1 T3 36 T4 1 T6 42
auto[1] 34235 1 T3 36 T4 6 T6 58


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34457 1 T3 42 T4 2 T6 56
auto[1] 32722 1 T3 30 T4 5 T6 44


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1131 1 T3 4 T6 1 T8 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 871 1 T3 2 T6 1 T14 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1181 1 T3 1 T20 15 T43 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 890 1 T20 14 T37 1 T23 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1163 1 T3 4 T9 1 T14 4
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 882 1 T3 1 T9 1 T14 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1946 1 T3 1 T10 1 T14 6
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1650 1 T10 1 T14 6 T20 32
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1114 1 T3 2 T6 1 T14 4
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 858 1 T3 2 T6 1 T14 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1192 1 T3 4 T6 1 T14 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 871 1 T3 2 T6 1 T14 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1109 1 T3 4 T4 1 T6 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 824 1 T6 1 T14 1 T20 11
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1158 1 T3 2 T9 1 T14 5
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 845 1 T9 1 T14 1 T20 10
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1155 1 T6 1 T8 1 T14 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 858 1 T6 1 T20 11 T23 4
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1181 1 T3 1 T6 3 T9 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 894 1 T6 3 T9 1 T14 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1212 1 T3 1 T6 4 T14 3
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 893 1 T6 4 T14 1 T20 14
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1213 1 T3 2 T4 1 T6 5
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 918 1 T6 5 T20 19 T43 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1181 1 T3 1 T4 1 T6 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 874 1 T6 1 T14 2 T20 19
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1206 1 T3 2 T6 1 T8 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 891 1 T3 1 T6 1 T20 14
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1200 1 T3 2 T4 2 T6 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 867 1 T6 1 T20 14 T41 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1173 1 T3 2 T4 1 T6 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 871 1 T6 2 T14 2 T20 14
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1138 1 T3 4 T6 1 T9 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 843 1 T6 1 T9 1 T14 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1239 1 T3 2 T6 3 T9 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 940 1 T3 2 T6 3 T9 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1138 1 T4 1 T6 1 T9 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 861 1 T6 1 T9 1 T14 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1163 1 T3 4 T6 2 T14 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 869 1 T3 1 T6 2 T20 13
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1225 1 T6 2 T8 1 T14 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 916 1 T6 2 T20 18 T37 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1198 1 T3 1 T6 2 T14 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 881 1 T6 2 T20 18 T41 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1241 1 T3 1 T6 2 T9 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 943 1 T6 2 T9 1 T20 23
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1200 1 T3 1 T6 2 T9 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 909 1 T6 2 T9 2 T14 2
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1186 1 T3 1 T6 3 T10 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 891 1 T3 1 T6 3 T14 3
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1180 1 T3 2 T9 1 T10 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 895 1 T9 1 T14 2 T20 9
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1153 1 T3 4 T6 1 T10 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 839 1 T3 1 T6 1 T10 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1189 1 T3 2 T6 3 T8 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 895 1 T3 1 T6 3 T20 20
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1159 1 T14 1 T20 26 T41 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 856 1 T14 1 T20 23 T41 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1187 1 T3 1 T6 1 T14 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 862 1 T6 1 T20 13 T43 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1131 1 T3 2 T6 3 T8 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 829 1 T6 3 T20 15 T43 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1121 1 T6 2 T14 2 T20 12
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 830 1 T6 2 T14 2 T20 9

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