Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02


Total test records in report: 1119
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T111 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2994678336 May 23 03:32:47 PM PDT 24 May 23 03:32:56 PM PDT 24 118992547 ps
T1020 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.185359761 May 23 03:32:45 PM PDT 24 May 23 03:32:54 PM PDT 24 45641582 ps
T1021 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3010205385 May 23 03:32:53 PM PDT 24 May 23 03:33:01 PM PDT 24 93935844 ps
T1022 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.158119087 May 23 03:32:47 PM PDT 24 May 23 03:32:56 PM PDT 24 31329378 ps
T112 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.2687549755 May 23 03:32:46 PM PDT 24 May 23 03:32:54 PM PDT 24 31204865 ps
T1023 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1780827993 May 23 03:32:45 PM PDT 24 May 23 03:32:53 PM PDT 24 51773689 ps
T1024 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2247541254 May 23 03:33:19 PM PDT 24 May 23 03:33:22 PM PDT 24 49985768 ps
T1025 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3461927236 May 23 03:32:44 PM PDT 24 May 23 03:32:52 PM PDT 24 21531738 ps
T1026 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.438075292 May 23 03:32:56 PM PDT 24 May 23 03:33:04 PM PDT 24 49497535 ps
T1027 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.2282082608 May 23 03:32:44 PM PDT 24 May 23 03:32:51 PM PDT 24 23158044 ps
T1028 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3162642342 May 23 03:33:23 PM PDT 24 May 23 03:33:27 PM PDT 24 31536544 ps
T1029 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.1415820836 May 23 03:33:20 PM PDT 24 May 23 03:33:23 PM PDT 24 27218683 ps
T1030 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.189807198 May 23 03:32:55 PM PDT 24 May 23 03:33:03 PM PDT 24 50695328 ps
T1031 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.386979752 May 23 03:32:52 PM PDT 24 May 23 03:33:02 PM PDT 24 187719847 ps
T1032 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.594868640 May 23 03:32:59 PM PDT 24 May 23 03:33:08 PM PDT 24 47419880 ps
T113 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3771415558 May 23 03:32:45 PM PDT 24 May 23 03:32:53 PM PDT 24 32710407 ps
T1033 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3808170993 May 23 03:32:45 PM PDT 24 May 23 03:32:54 PM PDT 24 1525000806 ps
T72 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2902423217 May 23 03:32:47 PM PDT 24 May 23 03:32:57 PM PDT 24 289022477 ps
T1034 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.4174574402 May 23 03:33:17 PM PDT 24 May 23 03:33:19 PM PDT 24 20663372 ps
T1035 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2085488468 May 23 03:32:41 PM PDT 24 May 23 03:32:44 PM PDT 24 25340038 ps
T1036 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.3976913959 May 23 03:33:20 PM PDT 24 May 23 03:33:23 PM PDT 24 100766882 ps
T1037 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2293547236 May 23 03:32:43 PM PDT 24 May 23 03:32:52 PM PDT 24 1118847069 ps
T149 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1981956614 May 23 03:32:55 PM PDT 24 May 23 03:33:04 PM PDT 24 208052709 ps
T99 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3025986052 May 23 03:32:45 PM PDT 24 May 23 03:32:54 PM PDT 24 115082586 ps
T1038 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.359342363 May 23 03:32:53 PM PDT 24 May 23 03:33:02 PM PDT 24 318790561 ps
T1039 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3705307089 May 23 03:32:43 PM PDT 24 May 23 03:32:49 PM PDT 24 43112230 ps
T1040 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.543966815 May 23 03:32:46 PM PDT 24 May 23 03:32:54 PM PDT 24 21602371 ps
T1041 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2806951646 May 23 03:32:52 PM PDT 24 May 23 03:33:00 PM PDT 24 51903238 ps
T1042 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.3663048746 May 23 03:32:52 PM PDT 24 May 23 03:33:00 PM PDT 24 17337886 ps
T1043 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.4055677500 May 23 03:32:58 PM PDT 24 May 23 03:33:07 PM PDT 24 17457216 ps
T1044 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.3312102676 May 23 03:32:43 PM PDT 24 May 23 03:32:50 PM PDT 24 234145564 ps
T1045 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.1185105652 May 23 03:32:45 PM PDT 24 May 23 03:32:54 PM PDT 24 139798276 ps
T1046 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3552765052 May 23 03:32:43 PM PDT 24 May 23 03:32:49 PM PDT 24 62112735 ps
T1047 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.3350640104 May 23 03:33:20 PM PDT 24 May 23 03:33:23 PM PDT 24 21329236 ps
T1048 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3080261600 May 23 03:32:59 PM PDT 24 May 23 03:33:08 PM PDT 24 47351493 ps
T1049 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1669537909 May 23 03:32:43 PM PDT 24 May 23 03:32:49 PM PDT 24 65731365 ps
T1050 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.3452703674 May 23 03:32:53 PM PDT 24 May 23 03:33:01 PM PDT 24 41065441 ps
T1051 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.105844775 May 23 03:32:55 PM PDT 24 May 23 03:33:03 PM PDT 24 18242545 ps
T1052 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.4049084465 May 23 03:32:45 PM PDT 24 May 23 03:32:52 PM PDT 24 52778969 ps
T146 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3254987759 May 23 03:32:43 PM PDT 24 May 23 03:32:50 PM PDT 24 341428325 ps
T1053 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.634897861 May 23 03:32:47 PM PDT 24 May 23 03:32:56 PM PDT 24 30386582 ps
T1054 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.31947152 May 23 03:32:55 PM PDT 24 May 23 03:33:03 PM PDT 24 16189381 ps
T1055 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.1981195228 May 23 03:32:55 PM PDT 24 May 23 03:33:04 PM PDT 24 653517849 ps
T1056 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.4110616197 May 23 03:33:22 PM PDT 24 May 23 03:33:25 PM PDT 24 19203709 ps
T1057 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1459848200 May 23 03:32:45 PM PDT 24 May 23 03:32:54 PM PDT 24 35250728 ps
T1058 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.477574724 May 23 03:33:04 PM PDT 24 May 23 03:33:10 PM PDT 24 68284219 ps
T150 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3639840836 May 23 03:32:43 PM PDT 24 May 23 03:32:50 PM PDT 24 158918524 ps
T1059 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3689864689 May 23 03:32:42 PM PDT 24 May 23 03:32:48 PM PDT 24 47825604 ps
T1060 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1054175844 May 23 03:32:53 PM PDT 24 May 23 03:33:02 PM PDT 24 274091663 ps
T1061 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2947610312 May 23 03:33:01 PM PDT 24 May 23 03:33:09 PM PDT 24 18789482 ps
T1062 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1137522942 May 23 03:32:56 PM PDT 24 May 23 03:33:04 PM PDT 24 43249905 ps
T100 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1856206089 May 23 03:32:52 PM PDT 24 May 23 03:33:00 PM PDT 24 19802238 ps
T1063 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2448125921 May 23 03:32:44 PM PDT 24 May 23 03:32:51 PM PDT 24 29530562 ps
T1064 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2060891613 May 23 03:32:43 PM PDT 24 May 23 03:32:49 PM PDT 24 99694475 ps
T1065 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1117123030 May 23 03:32:54 PM PDT 24 May 23 03:33:01 PM PDT 24 41342607 ps
T1066 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1270347870 May 23 03:32:59 PM PDT 24 May 23 03:33:07 PM PDT 24 24892522 ps
T1067 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2546315973 May 23 03:32:53 PM PDT 24 May 23 03:33:01 PM PDT 24 17236365 ps
T1068 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.2099595568 May 23 03:33:04 PM PDT 24 May 23 03:33:10 PM PDT 24 114459227 ps
T1069 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3838303626 May 23 03:32:44 PM PDT 24 May 23 03:32:51 PM PDT 24 60405722 ps
T1070 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2604010617 May 23 03:32:46 PM PDT 24 May 23 03:32:56 PM PDT 24 50481619 ps
T1071 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.148232757 May 23 03:33:20 PM PDT 24 May 23 03:33:23 PM PDT 24 19691176 ps
T1072 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2562056056 May 23 03:32:44 PM PDT 24 May 23 03:32:54 PM PDT 24 5048468763 ps
T1073 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2267119497 May 23 03:32:44 PM PDT 24 May 23 03:32:51 PM PDT 24 40424123 ps
T1074 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2932990241 May 23 03:33:21 PM PDT 24 May 23 03:33:24 PM PDT 24 47638778 ps
T101 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.4225450174 May 23 03:32:47 PM PDT 24 May 23 03:32:57 PM PDT 24 21311930 ps
T1075 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.946281324 May 23 03:32:59 PM PDT 24 May 23 03:33:08 PM PDT 24 77400185 ps
T1076 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3372442256 May 23 03:32:45 PM PDT 24 May 23 03:32:53 PM PDT 24 45511165 ps
T1077 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3237664517 May 23 03:33:21 PM PDT 24 May 23 03:33:24 PM PDT 24 45543707 ps
T1078 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3035322258 May 23 03:33:24 PM PDT 24 May 23 03:33:28 PM PDT 24 41249132 ps
T151 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2720585613 May 23 03:32:54 PM PDT 24 May 23 03:33:02 PM PDT 24 127462277 ps
T1079 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.982283890 May 23 03:32:47 PM PDT 24 May 23 03:32:56 PM PDT 24 18748769 ps
T1080 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.114889840 May 23 03:32:46 PM PDT 24 May 23 03:32:54 PM PDT 24 86609017 ps
T1081 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.2216300831 May 23 03:32:45 PM PDT 24 May 23 03:32:53 PM PDT 24 197175718 ps
T1082 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2441556910 May 23 03:33:00 PM PDT 24 May 23 03:33:09 PM PDT 24 101615734 ps
T1083 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3021619676 May 23 03:32:42 PM PDT 24 May 23 03:32:46 PM PDT 24 105008211 ps
T1084 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.4022099124 May 23 03:32:57 PM PDT 24 May 23 03:33:05 PM PDT 24 115343753 ps
T102 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2180013677 May 23 03:32:47 PM PDT 24 May 23 03:32:56 PM PDT 24 58806516 ps
T1085 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3297868433 May 23 03:32:48 PM PDT 24 May 23 03:32:57 PM PDT 24 19701586 ps
T1086 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.1772719513 May 23 03:32:41 PM PDT 24 May 23 03:32:45 PM PDT 24 18289373 ps
T1087 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3060214703 May 23 03:32:47 PM PDT 24 May 23 03:32:57 PM PDT 24 31595450 ps
T1088 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2782318740 May 23 03:33:20 PM PDT 24 May 23 03:33:23 PM PDT 24 53581694 ps
T78 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1866368825 May 23 03:32:59 PM PDT 24 May 23 03:33:08 PM PDT 24 195662016 ps
T1089 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.776158749 May 23 03:32:52 PM PDT 24 May 23 03:33:00 PM PDT 24 62394185 ps
T73 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2974132331 May 23 03:32:51 PM PDT 24 May 23 03:33:00 PM PDT 24 93270382 ps
T1090 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.4069664622 May 23 03:32:46 PM PDT 24 May 23 03:32:54 PM PDT 24 56570757 ps
T1091 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2953436180 May 23 03:32:54 PM PDT 24 May 23 03:33:03 PM PDT 24 106495832 ps
T1092 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.975297705 May 23 03:32:57 PM PDT 24 May 23 03:33:06 PM PDT 24 58646241 ps
T1093 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.856381288 May 23 03:32:47 PM PDT 24 May 23 03:32:59 PM PDT 24 254054204 ps
T1094 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1760071859 May 23 03:33:23 PM PDT 24 May 23 03:33:26 PM PDT 24 37158813 ps
T1095 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.3473300433 May 23 03:33:19 PM PDT 24 May 23 03:33:21 PM PDT 24 25470361 ps
T1096 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3224829278 May 23 03:32:42 PM PDT 24 May 23 03:32:47 PM PDT 24 16682332 ps
T1097 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3992629702 May 23 03:32:53 PM PDT 24 May 23 03:33:01 PM PDT 24 66231488 ps
T1098 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2161882506 May 23 03:32:44 PM PDT 24 May 23 03:32:53 PM PDT 24 467671365 ps
T1099 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.498526196 May 23 03:32:54 PM PDT 24 May 23 03:33:02 PM PDT 24 1258796126 ps
T1100 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2730988608 May 23 03:32:56 PM PDT 24 May 23 03:33:04 PM PDT 24 32535992 ps
T1101 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1171843881 May 23 03:32:57 PM PDT 24 May 23 03:33:05 PM PDT 24 47338479 ps
T1102 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.154063797 May 23 03:33:00 PM PDT 24 May 23 03:33:08 PM PDT 24 20094233 ps
T1103 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1547340739 May 23 03:32:44 PM PDT 24 May 23 03:32:50 PM PDT 24 107901650 ps
T1104 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.2057637347 May 23 03:32:53 PM PDT 24 May 23 03:33:01 PM PDT 24 20230871 ps
T1105 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.2568638916 May 23 03:32:53 PM PDT 24 May 23 03:33:02 PM PDT 24 78760355 ps
T1106 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.659815415 May 23 03:32:59 PM PDT 24 May 23 03:33:08 PM PDT 24 193050322 ps
T1107 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.408526134 May 23 03:32:45 PM PDT 24 May 23 03:32:53 PM PDT 24 35974614 ps
T1108 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3319984293 May 23 03:32:55 PM PDT 24 May 23 03:33:03 PM PDT 24 28320563 ps
T1109 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2071475168 May 23 03:32:45 PM PDT 24 May 23 03:32:54 PM PDT 24 35929927 ps
T1110 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.3851045180 May 23 03:33:21 PM PDT 24 May 23 03:33:24 PM PDT 24 31306802 ps
T1111 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1235538563 May 23 03:32:46 PM PDT 24 May 23 03:32:55 PM PDT 24 42235172 ps
T103 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.4230181350 May 23 03:32:46 PM PDT 24 May 23 03:32:54 PM PDT 24 18588249 ps
T1112 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.3068087929 May 23 03:32:46 PM PDT 24 May 23 03:32:57 PM PDT 24 817048612 ps
T1113 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.3352432548 May 23 03:32:53 PM PDT 24 May 23 03:33:01 PM PDT 24 19235361 ps
T1114 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2399033532 May 23 03:32:55 PM PDT 24 May 23 03:33:05 PM PDT 24 149996673 ps
T104 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.1426152577 May 23 03:32:44 PM PDT 24 May 23 03:32:51 PM PDT 24 41577543 ps
T105 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.134966536 May 23 03:32:43 PM PDT 24 May 23 03:32:48 PM PDT 24 79616106 ps
T1115 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.4204961620 May 23 03:32:48 PM PDT 24 May 23 03:32:58 PM PDT 24 804870773 ps
T106 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2713984148 May 23 03:32:42 PM PDT 24 May 23 03:32:48 PM PDT 24 27798092 ps
T1116 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1537688078 May 23 03:32:54 PM PDT 24 May 23 03:33:02 PM PDT 24 139158919 ps
T1117 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2236535058 May 23 03:32:45 PM PDT 24 May 23 03:32:53 PM PDT 24 229507734 ps
T1118 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.1834636728 May 23 03:32:47 PM PDT 24 May 23 03:32:56 PM PDT 24 46243513 ps
T147 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.569915011 May 23 03:32:42 PM PDT 24 May 23 03:32:48 PM PDT 24 358435292 ps
T1119 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1559615035 May 23 03:32:44 PM PDT 24 May 23 03:32:51 PM PDT 24 31683875 ps

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1029397470
Short name T6
Test name
Test status
Simulation time 1159654754 ps
CPU time 2.16 seconds
Started May 23 03:37:59 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 200524 kb
Host smart-bc5ed21b-8db7-4acb-87a9-22cd9815b6cd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029397470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1029397470
Directory /workspace/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all_with_rand_reset.282349899
Short name T14
Test name
Test status
Simulation time 699671100 ps
CPU time 4.51 seconds
Started May 23 03:37:53 PM PDT 24
Finished May 23 03:38:02 PM PDT 24
Peak memory 200764 kb
Host smart-e48d1074-a771-4709-859b-0961071dcc23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282349899 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all_with_rand_reset.282349899
Directory /workspace/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.3093754097
Short name T47
Test name
Test status
Simulation time 503384610 ps
CPU time 0.81 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:17 PM PDT 24
Peak memory 209000 kb
Host smart-90e69e47-85cf-4704-937d-024a3b165532
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093754097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.3093754097
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.3473345329
Short name T19
Test name
Test status
Simulation time 504068383 ps
CPU time 1.11 seconds
Started May 23 03:36:11 PM PDT 24
Finished May 23 03:36:18 PM PDT 24
Peak memory 216368 kb
Host smart-97891114-034c-4acc-bdf9-542192b86a59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473345329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.3473345329
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.2121493010
Short name T46
Test name
Test status
Simulation time 43253667 ps
CPU time 0.69 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 200824 kb
Host smart-7babdab4-74e2-4dee-8b30-6b39dbad8174
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121493010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.2121493010
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.4152508523
Short name T57
Test name
Test status
Simulation time 105455732 ps
CPU time 1.21 seconds
Started May 23 03:32:54 PM PDT 24
Finished May 23 03:33:03 PM PDT 24
Peak memory 199976 kb
Host smart-a1e36997-c50b-44a4-9a91-c923231faa33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152508523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.4152508523
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all_with_rand_reset.4209295047
Short name T52
Test name
Test status
Simulation time 4918203133 ps
CPU time 13.8 seconds
Started May 23 03:36:37 PM PDT 24
Finished May 23 03:36:54 PM PDT 24
Peak memory 200792 kb
Host smart-cf6c1331-be24-4200-8ed5-c5ca5f9ce5c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209295047 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all_with_rand_reset.4209295047
Directory /workspace/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1868514097
Short name T142
Test name
Test status
Simulation time 1313980414 ps
CPU time 1.91 seconds
Started May 23 03:35:58 PM PDT 24
Finished May 23 03:36:06 PM PDT 24
Peak memory 200600 kb
Host smart-eef7ecdc-181b-4749-be09-58f6bd8afe60
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868514097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1868514097
Directory /workspace/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all_with_rand_reset.2357503118
Short name T20
Test name
Test status
Simulation time 9296820478 ps
CPU time 27.63 seconds
Started May 23 03:37:43 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 200916 kb
Host smart-5f6080e5-f0be-4eb5-8fdd-8c0e0d96da31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357503118 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all_with_rand_reset.2357503118
Directory /workspace/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3072178926
Short name T68
Test name
Test status
Simulation time 182372740 ps
CPU time 0.61 seconds
Started May 23 03:32:57 PM PDT 24
Finished May 23 03:33:05 PM PDT 24
Peak memory 194916 kb
Host smart-6acc8642-d0c4-4742-828f-6e1cffead50f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072178926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.3072178926
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.2190867636
Short name T97
Test name
Test status
Simulation time 31438553 ps
CPU time 0.61 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:48 PM PDT 24
Peak memory 197104 kb
Host smart-8b56ca20-1680-48c8-95cf-d120893fecfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190867636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.2190867636
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.185359761
Short name T1020
Test name
Test status
Simulation time 45641582 ps
CPU time 2 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 197084 kb
Host smart-d51150ff-78e0-4bc3-b73a-3070089413eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185359761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.185359761
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.318025645
Short name T136
Test name
Test status
Simulation time 29385350 ps
CPU time 0.64 seconds
Started May 23 03:35:56 PM PDT 24
Finished May 23 03:36:02 PM PDT 24
Peak memory 197560 kb
Host smart-3e4fd570-6215-4b8d-b53e-67745801497f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318025645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_m
alfunc.318025645
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.495830237
Short name T59
Test name
Test status
Simulation time 179296676 ps
CPU time 1.18 seconds
Started May 23 03:36:13 PM PDT 24
Finished May 23 03:36:21 PM PDT 24
Peak memory 199720 kb
Host smart-0485c63f-9a5e-4f8a-bb0e-5f320f97e622
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495830237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm
_ctrl_config_regwen.495830237
Directory /workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.3530275443
Short name T8
Test name
Test status
Simulation time 37033066 ps
CPU time 0.75 seconds
Started May 23 03:37:09 PM PDT 24
Finished May 23 03:37:17 PM PDT 24
Peak memory 198328 kb
Host smart-083f2910-cdae-4998-955d-d5c88ea74e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530275443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.3530275443
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.2902423217
Short name T72
Test name
Test status
Simulation time 289022477 ps
CPU time 1.63 seconds
Started May 23 03:32:47 PM PDT 24
Finished May 23 03:32:57 PM PDT 24
Peak memory 195084 kb
Host smart-1d0c4e0d-ee1f-4af8-99cd-060b05947d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902423217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.2902423217
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.114422100
Short name T140
Test name
Test status
Simulation time 59474755 ps
CPU time 0.76 seconds
Started May 23 03:37:09 PM PDT 24
Finished May 23 03:37:17 PM PDT 24
Peak memory 198684 kb
Host smart-80d03c1a-9cfe-4de4-88ad-02c073715f72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114422100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disa
ble_rom_integrity_check.114422100
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.3354321365
Short name T158
Test name
Test status
Simulation time 74046324 ps
CPU time 0.69 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 198704 kb
Host smart-9ac81631-8354-4287-b4c0-b9933ef0adf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354321365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.3354321365
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.2896807116
Short name T161
Test name
Test status
Simulation time 52155304 ps
CPU time 0.87 seconds
Started May 23 03:37:57 PM PDT 24
Finished May 23 03:38:03 PM PDT 24
Peak memory 198712 kb
Host smart-3ed30097-c8c2-4ee9-86d0-55b3f797ba0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896807116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.2896807116
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.775097434
Short name T71
Test name
Test status
Simulation time 20829508 ps
CPU time 0.61 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:52 PM PDT 24
Peak memory 194944 kb
Host smart-ed6407b8-6384-4bdc-951b-0be94fcfd80f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775097434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.775097434
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.569915011
Short name T147
Test name
Test status
Simulation time 358435292 ps
CPU time 1.46 seconds
Started May 23 03:32:42 PM PDT 24
Finished May 23 03:32:48 PM PDT 24
Peak memory 195088 kb
Host smart-5350e861-3e20-4937-9e32-4a7753d148b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569915011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.
569915011
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1254081300
Short name T144
Test name
Test status
Simulation time 954500956 ps
CPU time 2.03 seconds
Started May 23 03:36:38 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 200468 kb
Host smart-b729608b-94d0-4bf5-bf5e-afedd5edbe2b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254081300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1254081300
Directory /workspace/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2143061779
Short name T56
Test name
Test status
Simulation time 85373265 ps
CPU time 1.07 seconds
Started May 23 03:32:54 PM PDT 24
Finished May 23 03:33:02 PM PDT 24
Peak memory 195168 kb
Host smart-6c16bf75-2f19-43c7-80bd-1edf58df92eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143061779 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.2143061779
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1866368825
Short name T78
Test name
Test status
Simulation time 195662016 ps
CPU time 1.78 seconds
Started May 23 03:32:59 PM PDT 24
Finished May 23 03:33:08 PM PDT 24
Peak memory 200188 kb
Host smart-af178033-398a-4a95-b981-6b88708bf8cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866368825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.1866368825
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.170787780
Short name T226
Test name
Test status
Simulation time 57602048 ps
CPU time 0.67 seconds
Started May 23 03:36:09 PM PDT 24
Finished May 23 03:36:14 PM PDT 24
Peak memory 196816 kb
Host smart-4b8924e4-3fea-424c-87d8-b150f5c07d79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170787780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.170787780
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2085488468
Short name T1035
Test name
Test status
Simulation time 25340038 ps
CPU time 0.92 seconds
Started May 23 03:32:41 PM PDT 24
Finished May 23 03:32:44 PM PDT 24
Peak memory 194912 kb
Host smart-8ea00057-49bb-436d-afd8-4bcb26803046
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085488468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.2
085488468
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3808170993
Short name T1033
Test name
Test status
Simulation time 1525000806 ps
CPU time 2.11 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 198732 kb
Host smart-a5523dee-1dae-4e49-89e9-6f55a84b93e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808170993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.3
808170993
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1972073324
Short name T1016
Test name
Test status
Simulation time 77421026 ps
CPU time 0.66 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:50 PM PDT 24
Peak memory 197560 kb
Host smart-09760f52-028c-459a-a217-ff87041a6d34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972073324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.1
972073324
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3838303626
Short name T1069
Test name
Test status
Simulation time 60405722 ps
CPU time 0.97 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:51 PM PDT 24
Peak memory 194972 kb
Host smart-f8df6091-9d22-4f49-9c8f-9414f05de577
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838303626 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.3838303626
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.4230181350
Short name T103
Test name
Test status
Simulation time 18588249 ps
CPU time 0.64 seconds
Started May 23 03:32:46 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 197084 kb
Host smart-2c5952e8-d6d9-4d8f-bfa6-f508990806c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230181350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.4230181350
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3224829278
Short name T1096
Test name
Test status
Simulation time 16682332 ps
CPU time 0.67 seconds
Started May 23 03:32:42 PM PDT 24
Finished May 23 03:32:47 PM PDT 24
Peak memory 194932 kb
Host smart-0723c950-d99f-4dbe-b98c-d94c78485fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224829278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.3224829278
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3021619676
Short name T1083
Test name
Test status
Simulation time 105008211 ps
CPU time 0.67 seconds
Started May 23 03:32:42 PM PDT 24
Finished May 23 03:32:46 PM PDT 24
Peak memory 197100 kb
Host smart-51de480e-e35d-40c2-a135-dc216411c6fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021619676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.3021619676
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.2216300831
Short name T1081
Test name
Test status
Simulation time 197175718 ps
CPU time 1.11 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:53 PM PDT 24
Peak memory 195220 kb
Host smart-826e2d70-b583-4144-a82e-1df18acb73af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216300831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.2216300831
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3254987759
Short name T146
Test name
Test status
Simulation time 341428325 ps
CPU time 1.45 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:50 PM PDT 24
Peak memory 200324 kb
Host smart-c8d8fd3b-2875-42c8-8ff1-65515ec56263
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254987759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.3254987759
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3372442256
Short name T1076
Test name
Test status
Simulation time 45511165 ps
CPU time 1 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:53 PM PDT 24
Peak memory 198376 kb
Host smart-cfb504c9-bc0d-4464-a837-029b107aa12e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372442256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.3
372442256
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.4176120722
Short name T156
Test name
Test status
Simulation time 398913367 ps
CPU time 2 seconds
Started May 23 03:32:42 PM PDT 24
Finished May 23 03:32:48 PM PDT 24
Peak memory 194964 kb
Host smart-8623b034-1be3-4f40-8ad2-e0fdbcc203e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176120722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.4
176120722
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.134966536
Short name T105
Test name
Test status
Simulation time 79616106 ps
CPU time 0.65 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:48 PM PDT 24
Peak memory 194844 kb
Host smart-ab915969-8a4e-4325-9a31-28dd864ec548
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134966536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.134966536
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2060891613
Short name T1064
Test name
Test status
Simulation time 99694475 ps
CPU time 1.25 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:49 PM PDT 24
Peak memory 198032 kb
Host smart-54856ed4-c4e6-4fc8-83e9-6aa72f8a6265
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060891613 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.2060891613
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1235538563
Short name T1111
Test name
Test status
Simulation time 42235172 ps
CPU time 0.63 seconds
Started May 23 03:32:46 PM PDT 24
Finished May 23 03:32:55 PM PDT 24
Peak memory 194900 kb
Host smart-d610f8a2-8b31-458b-b80c-4dc4cf1475c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235538563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.1235538563
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3689864689
Short name T1059
Test name
Test status
Simulation time 47825604 ps
CPU time 0.76 seconds
Started May 23 03:32:42 PM PDT 24
Finished May 23 03:32:48 PM PDT 24
Peak memory 197168 kb
Host smart-692b742c-63cf-4c1e-b40b-f57dd5e0828d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689864689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.3689864689
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3552765052
Short name T1046
Test name
Test status
Simulation time 62112735 ps
CPU time 1.75 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:49 PM PDT 24
Peak memory 197216 kb
Host smart-9ec2348a-cc33-4bf4-8828-e5bfa4d10aad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552765052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.3552765052
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.800009850
Short name T61
Test name
Test status
Simulation time 84196324 ps
CPU time 1.05 seconds
Started May 23 03:32:55 PM PDT 24
Finished May 23 03:33:03 PM PDT 24
Peak memory 196004 kb
Host smart-8f12ef5c-b067-4150-b286-63397205eaa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800009850 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.800009850
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1117123030
Short name T1065
Test name
Test status
Simulation time 41342607 ps
CPU time 0.63 seconds
Started May 23 03:32:54 PM PDT 24
Finished May 23 03:33:01 PM PDT 24
Peak memory 194944 kb
Host smart-bbe86fac-0472-4d2e-aba2-7449a71c8ff0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117123030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.1117123030
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.3478368199
Short name T153
Test name
Test status
Simulation time 21582405 ps
CPU time 0.6 seconds
Started May 23 03:32:52 PM PDT 24
Finished May 23 03:33:00 PM PDT 24
Peak memory 194904 kb
Host smart-d08d508c-d956-46b0-aab9-300d0381ee8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478368199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.3478368199
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2441556910
Short name T1082
Test name
Test status
Simulation time 101615734 ps
CPU time 0.73 seconds
Started May 23 03:33:00 PM PDT 24
Finished May 23 03:33:09 PM PDT 24
Peak memory 197104 kb
Host smart-d60fa6cb-511e-4de5-bfda-ab2dd077b478
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441556910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.2441556910
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.386979752
Short name T1031
Test name
Test status
Simulation time 187719847 ps
CPU time 2.65 seconds
Started May 23 03:32:52 PM PDT 24
Finished May 23 03:33:02 PM PDT 24
Peak memory 196192 kb
Host smart-e3274d52-897e-4813-8175-968c196d0af6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386979752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.386979752
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2953436180
Short name T1091
Test name
Test status
Simulation time 106495832 ps
CPU time 1.15 seconds
Started May 23 03:32:54 PM PDT 24
Finished May 23 03:33:03 PM PDT 24
Peak memory 199860 kb
Host smart-57528f2e-5a37-4eaa-a325-192873db7dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953436180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.2953436180
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2806951646
Short name T1041
Test name
Test status
Simulation time 51903238 ps
CPU time 0.73 seconds
Started May 23 03:32:52 PM PDT 24
Finished May 23 03:33:00 PM PDT 24
Peak memory 194944 kb
Host smart-c700e56e-2c34-4aef-956f-d68d94d5c46d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806951646 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.2806951646
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.1182506103
Short name T110
Test name
Test status
Simulation time 47498558 ps
CPU time 0.59 seconds
Started May 23 03:32:57 PM PDT 24
Finished May 23 03:33:06 PM PDT 24
Peak memory 194952 kb
Host smart-7f021c8c-9382-47cd-a8ec-52743f16a531
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182506103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.1182506103
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.3352432548
Short name T1113
Test name
Test status
Simulation time 19235361 ps
CPU time 0.59 seconds
Started May 23 03:32:53 PM PDT 24
Finished May 23 03:33:01 PM PDT 24
Peak memory 194892 kb
Host smart-1cc4aa7c-b465-4219-b536-e5d95d3b86e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352432548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.3352432548
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1720448741
Short name T107
Test name
Test status
Simulation time 28645475 ps
CPU time 0.75 seconds
Started May 23 03:32:52 PM PDT 24
Finished May 23 03:33:00 PM PDT 24
Peak memory 197184 kb
Host smart-6db46042-9002-4495-964a-ac206b66758c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720448741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.1720448741
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.659815415
Short name T1106
Test name
Test status
Simulation time 193050322 ps
CPU time 1.4 seconds
Started May 23 03:32:59 PM PDT 24
Finished May 23 03:33:08 PM PDT 24
Peak memory 196060 kb
Host smart-a844612f-66e7-46b0-8da7-4c5d99c2fc84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659815415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.659815415
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2974132331
Short name T73
Test name
Test status
Simulation time 93270382 ps
CPU time 1.07 seconds
Started May 23 03:32:51 PM PDT 24
Finished May 23 03:33:00 PM PDT 24
Peak memory 199664 kb
Host smart-1335b872-960f-4e2e-aa14-0e32d186f5a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974132331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.2974132331
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2243149578
Short name T1013
Test name
Test status
Simulation time 80639997 ps
CPU time 1.17 seconds
Started May 23 03:32:54 PM PDT 24
Finished May 23 03:33:02 PM PDT 24
Peak memory 200308 kb
Host smart-5d83a773-9726-4af1-af8f-a5c98453ff20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243149578 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.2243149578
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.4055677500
Short name T1043
Test name
Test status
Simulation time 17457216 ps
CPU time 0.63 seconds
Started May 23 03:32:58 PM PDT 24
Finished May 23 03:33:07 PM PDT 24
Peak memory 194920 kb
Host smart-f668b82d-9f59-4729-9cfa-bd811c1d62ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055677500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.4055677500
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.631475497
Short name T1018
Test name
Test status
Simulation time 34484249 ps
CPU time 0.64 seconds
Started May 23 03:32:55 PM PDT 24
Finished May 23 03:33:03 PM PDT 24
Peak memory 194864 kb
Host smart-4d8ce6d2-ffd8-4b28-9bd5-d9d67a6ef24f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631475497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.631475497
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.946281324
Short name T1075
Test name
Test status
Simulation time 77400185 ps
CPU time 0.91 seconds
Started May 23 03:32:59 PM PDT 24
Finished May 23 03:33:08 PM PDT 24
Peak memory 194876 kb
Host smart-29cc2dbf-30c0-4d23-b11d-348863d24cde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946281324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sa
me_csr_outstanding.946281324
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2399033532
Short name T1114
Test name
Test status
Simulation time 149996673 ps
CPU time 1.96 seconds
Started May 23 03:32:55 PM PDT 24
Finished May 23 03:33:05 PM PDT 24
Peak memory 196100 kb
Host smart-e0e1057d-7c1c-42a9-a9c3-0750a90e8b89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399033532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.2399033532
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3010205385
Short name T1021
Test name
Test status
Simulation time 93935844 ps
CPU time 1.02 seconds
Started May 23 03:32:53 PM PDT 24
Finished May 23 03:33:01 PM PDT 24
Peak memory 195152 kb
Host smart-5c8ef59c-59be-4aee-844c-2741e82c8715
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010205385 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.3010205385
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.31947152
Short name T1054
Test name
Test status
Simulation time 16189381 ps
CPU time 0.63 seconds
Started May 23 03:32:55 PM PDT 24
Finished May 23 03:33:03 PM PDT 24
Peak memory 197136 kb
Host smart-54e7995f-c2a5-4927-a126-ab3f3fd53790
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31947152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.31947152
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2546315973
Short name T1067
Test name
Test status
Simulation time 17236365 ps
CPU time 0.63 seconds
Started May 23 03:32:53 PM PDT 24
Finished May 23 03:33:01 PM PDT 24
Peak memory 194924 kb
Host smart-16dab596-f830-4453-91b0-d15d3e90a4bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546315973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.2546315973
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1537688078
Short name T1116
Test name
Test status
Simulation time 139158919 ps
CPU time 0.85 seconds
Started May 23 03:32:54 PM PDT 24
Finished May 23 03:33:02 PM PDT 24
Peak memory 198152 kb
Host smart-c96405a8-f191-4a82-9861-8af123bdbba4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537688078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.1537688078
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.975297705
Short name T1092
Test name
Test status
Simulation time 58646241 ps
CPU time 1.53 seconds
Started May 23 03:32:57 PM PDT 24
Finished May 23 03:33:06 PM PDT 24
Peak memory 196128 kb
Host smart-f2ffaea3-4705-4343-9006-0b58042d9101
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975297705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.975297705
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1054175844
Short name T1060
Test name
Test status
Simulation time 274091663 ps
CPU time 1.64 seconds
Started May 23 03:32:53 PM PDT 24
Finished May 23 03:33:02 PM PDT 24
Peak memory 195120 kb
Host smart-175d4f87-43e4-478e-913b-563368fd1766
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054175844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.1054175844
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.867475850
Short name T130
Test name
Test status
Simulation time 90209968 ps
CPU time 0.85 seconds
Started May 23 03:32:55 PM PDT 24
Finished May 23 03:33:03 PM PDT 24
Peak memory 195132 kb
Host smart-9c86f0f6-6dbe-43c3-8d89-9fba8d378750
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867475850 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.867475850
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3797881419
Short name T1014
Test name
Test status
Simulation time 47637259 ps
CPU time 0.62 seconds
Started May 23 03:32:53 PM PDT 24
Finished May 23 03:33:00 PM PDT 24
Peak memory 194944 kb
Host smart-f53a0af0-50bd-403f-8996-349e33f125a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797881419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.3797881419
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.154063797
Short name T1102
Test name
Test status
Simulation time 20094233 ps
CPU time 0.61 seconds
Started May 23 03:33:00 PM PDT 24
Finished May 23 03:33:08 PM PDT 24
Peak memory 194864 kb
Host smart-8dbe742a-d94f-40a0-8d61-2f1c3116e36b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154063797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.154063797
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3730995365
Short name T108
Test name
Test status
Simulation time 204152236 ps
CPU time 0.84 seconds
Started May 23 03:32:55 PM PDT 24
Finished May 23 03:33:03 PM PDT 24
Peak memory 198180 kb
Host smart-3fa09d16-a0b4-47ff-9397-2981a0ee5774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730995365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.3730995365
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.359342363
Short name T1038
Test name
Test status
Simulation time 318790561 ps
CPU time 1.88 seconds
Started May 23 03:32:53 PM PDT 24
Finished May 23 03:33:02 PM PDT 24
Peak memory 196360 kb
Host smart-eb8a6f2c-0e53-453b-8695-01707904d0ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359342363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.359342363
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1981956614
Short name T149
Test name
Test status
Simulation time 208052709 ps
CPU time 1.7 seconds
Started May 23 03:32:55 PM PDT 24
Finished May 23 03:33:04 PM PDT 24
Peak memory 200436 kb
Host smart-96a97716-f34e-429b-af29-cbdab28ff42e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981956614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.1981956614
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.1533660119
Short name T64
Test name
Test status
Simulation time 39973780 ps
CPU time 0.77 seconds
Started May 23 03:32:53 PM PDT 24
Finished May 23 03:33:01 PM PDT 24
Peak memory 195000 kb
Host smart-e7d78802-3f32-48ac-a8cd-639261a221ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533660119 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.1533660119
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1158896356
Short name T60
Test name
Test status
Simulation time 22369467 ps
CPU time 0.62 seconds
Started May 23 03:32:56 PM PDT 24
Finished May 23 03:33:03 PM PDT 24
Peak memory 194964 kb
Host smart-98b5ac24-820b-4985-bfb1-dd4e81b5ba17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158896356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.1158896356
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.3663048746
Short name T1042
Test name
Test status
Simulation time 17337886 ps
CPU time 0.61 seconds
Started May 23 03:32:52 PM PDT 24
Finished May 23 03:33:00 PM PDT 24
Peak memory 194920 kb
Host smart-b9904888-ed20-439c-8f17-cff3028fa120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663048746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.3663048746
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.3452703674
Short name T1050
Test name
Test status
Simulation time 41065441 ps
CPU time 0.82 seconds
Started May 23 03:32:53 PM PDT 24
Finished May 23 03:33:01 PM PDT 24
Peak memory 199876 kb
Host smart-3610a003-14db-4536-984d-f88cef5dd15c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452703674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.3452703674
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.1981195228
Short name T1055
Test name
Test status
Simulation time 653517849 ps
CPU time 2.23 seconds
Started May 23 03:32:55 PM PDT 24
Finished May 23 03:33:04 PM PDT 24
Peak memory 196180 kb
Host smart-28e9e2ca-e294-4114-ba34-040afff13d95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981195228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.1981195228
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2720585613
Short name T151
Test name
Test status
Simulation time 127462277 ps
CPU time 1.12 seconds
Started May 23 03:32:54 PM PDT 24
Finished May 23 03:33:02 PM PDT 24
Peak memory 195080 kb
Host smart-c2ddcb3b-eaa8-4a9e-ab57-f78831e08cbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720585613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.2720585613
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1366159596
Short name T109
Test name
Test status
Simulation time 58218967 ps
CPU time 0.65 seconds
Started May 23 03:32:57 PM PDT 24
Finished May 23 03:33:05 PM PDT 24
Peak memory 195000 kb
Host smart-ff71600e-c5d4-4fcc-bb51-4cb7bf6ebacb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366159596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1366159596
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.2057637347
Short name T1104
Test name
Test status
Simulation time 20230871 ps
CPU time 0.63 seconds
Started May 23 03:32:53 PM PDT 24
Finished May 23 03:33:01 PM PDT 24
Peak memory 194880 kb
Host smart-064daa97-d031-4bf0-ad79-41b2b406f7c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057637347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.2057637347
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3992629702
Short name T1097
Test name
Test status
Simulation time 66231488 ps
CPU time 0.72 seconds
Started May 23 03:32:53 PM PDT 24
Finished May 23 03:33:01 PM PDT 24
Peak memory 197152 kb
Host smart-3eade1b5-a62c-47f5-95fe-8446200652c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992629702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.3992629702
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1664453682
Short name T65
Test name
Test status
Simulation time 42332974 ps
CPU time 1.92 seconds
Started May 23 03:32:52 PM PDT 24
Finished May 23 03:33:01 PM PDT 24
Peak memory 196108 kb
Host smart-ade93f52-5437-4fa7-8d28-5e23679eef2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664453682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1664453682
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.498526196
Short name T1099
Test name
Test status
Simulation time 1258796126 ps
CPU time 1.48 seconds
Started May 23 03:32:54 PM PDT 24
Finished May 23 03:33:02 PM PDT 24
Peak memory 195088 kb
Host smart-1f67c70d-406a-4aba-8823-fb569056c371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498526196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err
.498526196
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3577451116
Short name T77
Test name
Test status
Simulation time 36412720 ps
CPU time 0.84 seconds
Started May 23 03:32:56 PM PDT 24
Finished May 23 03:33:04 PM PDT 24
Peak memory 195080 kb
Host smart-0305b297-f96d-4174-b77d-6abc982003eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577451116 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.3577451116
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1856206089
Short name T100
Test name
Test status
Simulation time 19802238 ps
CPU time 0.66 seconds
Started May 23 03:32:52 PM PDT 24
Finished May 23 03:33:00 PM PDT 24
Peak memory 197400 kb
Host smart-a294d1ae-ee59-4abc-8476-92022b5f69b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856206089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1856206089
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1137522942
Short name T1062
Test name
Test status
Simulation time 43249905 ps
CPU time 0.62 seconds
Started May 23 03:32:56 PM PDT 24
Finished May 23 03:33:04 PM PDT 24
Peak memory 194940 kb
Host smart-dc6153e7-34f8-455a-9d18-f486aca64d78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137522942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.1137522942
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.776158749
Short name T1089
Test name
Test status
Simulation time 62394185 ps
CPU time 0.72 seconds
Started May 23 03:32:52 PM PDT 24
Finished May 23 03:33:00 PM PDT 24
Peak memory 194904 kb
Host smart-cd35aa6f-c2f3-48d9-8712-419742c1b8d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776158749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sa
me_csr_outstanding.776158749
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.4038838252
Short name T75
Test name
Test status
Simulation time 68910187 ps
CPU time 1.44 seconds
Started May 23 03:32:54 PM PDT 24
Finished May 23 03:33:03 PM PDT 24
Peak memory 195200 kb
Host smart-1714700c-210b-4806-b3a2-e1498bb886f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038838252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.4038838252
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.477574724
Short name T1058
Test name
Test status
Simulation time 68284219 ps
CPU time 1.31 seconds
Started May 23 03:33:04 PM PDT 24
Finished May 23 03:33:10 PM PDT 24
Peak memory 197656 kb
Host smart-ec9fe1f5-eefc-4ff1-a443-c6a7da327309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477574724 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.477574724
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2947610312
Short name T1061
Test name
Test status
Simulation time 18789482 ps
CPU time 0.62 seconds
Started May 23 03:33:01 PM PDT 24
Finished May 23 03:33:09 PM PDT 24
Peak memory 194948 kb
Host smart-f4d2e657-80ec-4942-967c-e37aeb6e5e86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947610312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.2947610312
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.594868640
Short name T1032
Test name
Test status
Simulation time 47419880 ps
CPU time 0.6 seconds
Started May 23 03:32:59 PM PDT 24
Finished May 23 03:33:08 PM PDT 24
Peak memory 194872 kb
Host smart-895fac06-c06a-4250-bc83-89d436f4221c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594868640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.594868640
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1270347870
Short name T1066
Test name
Test status
Simulation time 24892522 ps
CPU time 0.82 seconds
Started May 23 03:32:59 PM PDT 24
Finished May 23 03:33:07 PM PDT 24
Peak memory 198580 kb
Host smart-1e17905e-f720-4503-a4ef-cd4defb36130
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270347870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.1270347870
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.2568638916
Short name T1105
Test name
Test status
Simulation time 78760355 ps
CPU time 1.75 seconds
Started May 23 03:32:53 PM PDT 24
Finished May 23 03:33:02 PM PDT 24
Peak memory 196088 kb
Host smart-09b431c6-380e-4ca5-8037-77e884594ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568638916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.2568638916
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2836116899
Short name T50
Test name
Test status
Simulation time 109086679 ps
CPU time 1.19 seconds
Started May 23 03:33:00 PM PDT 24
Finished May 23 03:33:09 PM PDT 24
Peak memory 199836 kb
Host smart-e33e4b8c-5599-4ef9-8317-1cff1d5e1354
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836116899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.2836116899
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.189807198
Short name T1030
Test name
Test status
Simulation time 50695328 ps
CPU time 0.83 seconds
Started May 23 03:32:55 PM PDT 24
Finished May 23 03:33:03 PM PDT 24
Peak memory 195036 kb
Host smart-dcb5bf8b-380d-4eb5-8465-412ce8f0f0f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189807198 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.189807198
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.105844775
Short name T1051
Test name
Test status
Simulation time 18242545 ps
CPU time 0.64 seconds
Started May 23 03:32:55 PM PDT 24
Finished May 23 03:33:03 PM PDT 24
Peak memory 194952 kb
Host smart-8560ea5c-8dd3-4688-922e-4af4d8ed89dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105844775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.105844775
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3080261600
Short name T1048
Test name
Test status
Simulation time 47351493 ps
CPU time 0.58 seconds
Started May 23 03:32:59 PM PDT 24
Finished May 23 03:33:08 PM PDT 24
Peak memory 194880 kb
Host smart-fdb7ec37-138f-4b27-9585-857d7932138e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080261600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.3080261600
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2318251021
Short name T62
Test name
Test status
Simulation time 55305935 ps
CPU time 0.79 seconds
Started May 23 03:33:04 PM PDT 24
Finished May 23 03:33:10 PM PDT 24
Peak memory 199468 kb
Host smart-ca245816-dba2-4968-8469-e16698fe5dde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318251021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.2318251021
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.2824462821
Short name T66
Test name
Test status
Simulation time 128934160 ps
CPU time 2.33 seconds
Started May 23 03:32:55 PM PDT 24
Finished May 23 03:33:04 PM PDT 24
Peak memory 197136 kb
Host smart-17314de4-e16b-4453-a6a4-e3c46b3b4bea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824462821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.2824462821
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1932215668
Short name T1017
Test name
Test status
Simulation time 102327768 ps
CPU time 1.16 seconds
Started May 23 03:33:04 PM PDT 24
Finished May 23 03:33:10 PM PDT 24
Peak memory 195032 kb
Host smart-75d7fa27-9817-4c2d-a2e9-9f8bfd122557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932215668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.1932215668
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2713984148
Short name T106
Test name
Test status
Simulation time 27798092 ps
CPU time 0.92 seconds
Started May 23 03:32:42 PM PDT 24
Finished May 23 03:32:48 PM PDT 24
Peak memory 194872 kb
Host smart-955e1d25-2058-4fd1-997c-1024ce055eac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713984148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.2
713984148
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2562056056
Short name T1072
Test name
Test status
Simulation time 5048468763 ps
CPU time 3.6 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 195124 kb
Host smart-ca99a7d0-bb05-4826-9977-f2925c00c2a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562056056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.2
562056056
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3705307089
Short name T1039
Test name
Test status
Simulation time 43112230 ps
CPU time 0.68 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:49 PM PDT 24
Peak memory 197476 kb
Host smart-c79920e5-c2e4-4b1f-b651-df36971c60de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705307089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.3
705307089
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1669537909
Short name T1049
Test name
Test status
Simulation time 65731365 ps
CPU time 0.81 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:49 PM PDT 24
Peak memory 195024 kb
Host smart-ed0ed1ee-cbad-4f48-abe3-336a24760331
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669537909 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.1669537909
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.1426152577
Short name T104
Test name
Test status
Simulation time 41577543 ps
CPU time 0.6 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:51 PM PDT 24
Peak memory 197208 kb
Host smart-31aad2d5-2986-4fff-aeed-7f2b630fe901
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426152577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.1426152577
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.2282082608
Short name T1027
Test name
Test status
Simulation time 23158044 ps
CPU time 0.61 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:51 PM PDT 24
Peak memory 194876 kb
Host smart-c267a35d-422f-453f-a1d8-a2338a2ec1dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282082608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.2282082608
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2071475168
Short name T1109
Test name
Test status
Simulation time 35929927 ps
CPU time 0.83 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 194888 kb
Host smart-55c52581-2471-40f0-80d0-78fd46105465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071475168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.2071475168
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3639840836
Short name T150
Test name
Test status
Simulation time 158918524 ps
CPU time 1.11 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:50 PM PDT 24
Peak memory 199964 kb
Host smart-bc5cb8e0-a337-4934-bb35-8ab65782437f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639840836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.3639840836
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.438075292
Short name T1026
Test name
Test status
Simulation time 49497535 ps
CPU time 0.59 seconds
Started May 23 03:32:56 PM PDT 24
Finished May 23 03:33:04 PM PDT 24
Peak memory 194896 kb
Host smart-2eb52b99-8b2f-4233-b110-c2c6389c019f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438075292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.438075292
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.4174681120
Short name T1007
Test name
Test status
Simulation time 15989589 ps
CPU time 0.59 seconds
Started May 23 03:32:56 PM PDT 24
Finished May 23 03:33:04 PM PDT 24
Peak memory 194920 kb
Host smart-05c1c208-420c-4731-839a-856f86404740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174681120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.4174681120
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2730988608
Short name T1100
Test name
Test status
Simulation time 32535992 ps
CPU time 0.58 seconds
Started May 23 03:32:56 PM PDT 24
Finished May 23 03:33:04 PM PDT 24
Peak memory 194920 kb
Host smart-87f203b1-096a-4fa2-be51-b32a0f7db76a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730988608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.2730988608
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.2099595568
Short name T1068
Test name
Test status
Simulation time 114459227 ps
CPU time 0.59 seconds
Started May 23 03:33:04 PM PDT 24
Finished May 23 03:33:10 PM PDT 24
Peak memory 194928 kb
Host smart-700a0ff4-8580-404b-a60d-40412fe400b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099595568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.2099595568
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1909197098
Short name T1010
Test name
Test status
Simulation time 154731823 ps
CPU time 0.59 seconds
Started May 23 03:33:06 PM PDT 24
Finished May 23 03:33:11 PM PDT 24
Peak memory 194920 kb
Host smart-f861df1c-51d1-4d83-a44a-3b78af78a9b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909197098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.1909197098
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3319984293
Short name T1108
Test name
Test status
Simulation time 28320563 ps
CPU time 0.64 seconds
Started May 23 03:32:55 PM PDT 24
Finished May 23 03:33:03 PM PDT 24
Peak memory 194892 kb
Host smart-ff2c0553-278f-474e-8081-894440ebe1e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319984293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3319984293
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1171843881
Short name T1101
Test name
Test status
Simulation time 47338479 ps
CPU time 0.58 seconds
Started May 23 03:32:57 PM PDT 24
Finished May 23 03:33:05 PM PDT 24
Peak memory 194908 kb
Host smart-350d9381-5c45-4f96-b875-bed7614039d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171843881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1171843881
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.4022099124
Short name T1084
Test name
Test status
Simulation time 115343753 ps
CPU time 0.6 seconds
Started May 23 03:32:57 PM PDT 24
Finished May 23 03:33:05 PM PDT 24
Peak memory 194916 kb
Host smart-1b639df9-9d6b-492f-ac3d-db2fccc35b77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022099124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.4022099124
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1289148831
Short name T1008
Test name
Test status
Simulation time 133662120 ps
CPU time 0.64 seconds
Started May 23 03:33:06 PM PDT 24
Finished May 23 03:33:11 PM PDT 24
Peak memory 194928 kb
Host smart-f8720da2-5877-4f79-8173-52f922144793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289148831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.1289148831
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3461927236
Short name T1025
Test name
Test status
Simulation time 21531738 ps
CPU time 0.78 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:52 PM PDT 24
Peak memory 194880 kb
Host smart-af60492d-8b94-4f95-86c8-85cb6f786abc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461927236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.3
461927236
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2293547236
Short name T1037
Test name
Test status
Simulation time 1118847069 ps
CPU time 3.5 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:52 PM PDT 24
Peak memory 195036 kb
Host smart-fd2cdbc3-71b1-4771-b8f7-8ab34d23d25b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293547236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.2
293547236
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3776175668
Short name T98
Test name
Test status
Simulation time 72862960 ps
CPU time 0.64 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:52 PM PDT 24
Peak memory 194876 kb
Host smart-1a8102c9-aba1-4cd4-bf14-823954fefcce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776175668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.3
776175668
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2211725995
Short name T1009
Test name
Test status
Simulation time 38564396 ps
CPU time 0.74 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:49 PM PDT 24
Peak memory 195124 kb
Host smart-981b6d42-e98e-4634-85c5-6469dc747ed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211725995 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.2211725995
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1547340739
Short name T1103
Test name
Test status
Simulation time 107901650 ps
CPU time 0.6 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:50 PM PDT 24
Peak memory 194904 kb
Host smart-a1c54c9a-5533-4f58-8278-221c2e342d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547340739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.1547340739
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.634897861
Short name T1053
Test name
Test status
Simulation time 30386582 ps
CPU time 0.87 seconds
Started May 23 03:32:47 PM PDT 24
Finished May 23 03:32:56 PM PDT 24
Peak memory 198180 kb
Host smart-d351010c-b614-4d49-aa24-aac46a513f1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634897861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sam
e_csr_outstanding.634897861
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.1630710252
Short name T51
Test name
Test status
Simulation time 38994160 ps
CPU time 1.88 seconds
Started May 23 03:32:46 PM PDT 24
Finished May 23 03:32:56 PM PDT 24
Peak memory 196336 kb
Host smart-125b51e5-74e0-4a90-8809-55dae5d56111
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630710252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.1630710252
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2734426022
Short name T148
Test name
Test status
Simulation time 187218362 ps
CPU time 1.03 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 194972 kb
Host smart-14835764-d983-45de-afb4-c2e37ede67d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734426022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.2734426022
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3035322258
Short name T1078
Test name
Test status
Simulation time 41249132 ps
CPU time 0.65 seconds
Started May 23 03:33:24 PM PDT 24
Finished May 23 03:33:28 PM PDT 24
Peak memory 194884 kb
Host smart-900c8e36-a2e7-4e37-ba7f-07a40e778ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035322258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.3035322258
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.3350640104
Short name T1047
Test name
Test status
Simulation time 21329236 ps
CPU time 0.65 seconds
Started May 23 03:33:20 PM PDT 24
Finished May 23 03:33:23 PM PDT 24
Peak memory 194924 kb
Host smart-6b7a3d0c-8953-46bc-b0fc-f179010e25f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350640104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.3350640104
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3162642342
Short name T1028
Test name
Test status
Simulation time 31536544 ps
CPU time 0.61 seconds
Started May 23 03:33:23 PM PDT 24
Finished May 23 03:33:27 PM PDT 24
Peak memory 194908 kb
Host smart-9113a559-1cae-476c-977a-61876452313e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162642342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.3162642342
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.148232757
Short name T1071
Test name
Test status
Simulation time 19691176 ps
CPU time 0.62 seconds
Started May 23 03:33:20 PM PDT 24
Finished May 23 03:33:23 PM PDT 24
Peak memory 194904 kb
Host smart-1c71f65d-8e0d-40cd-8813-5ad639773c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148232757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.148232757
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2782318740
Short name T1088
Test name
Test status
Simulation time 53581694 ps
CPU time 0.65 seconds
Started May 23 03:33:20 PM PDT 24
Finished May 23 03:33:23 PM PDT 24
Peak memory 194896 kb
Host smart-428cf633-0218-4978-b537-64d13af6ace0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782318740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2782318740
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.2469199019
Short name T1011
Test name
Test status
Simulation time 37205763 ps
CPU time 0.57 seconds
Started May 23 03:33:18 PM PDT 24
Finished May 23 03:33:20 PM PDT 24
Peak memory 194920 kb
Host smart-1e4d5a8c-87e0-4180-a9ed-a0f93a2e3b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469199019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.2469199019
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.2627205305
Short name T154
Test name
Test status
Simulation time 29973795 ps
CPU time 0.57 seconds
Started May 23 03:33:20 PM PDT 24
Finished May 23 03:33:23 PM PDT 24
Peak memory 194888 kb
Host smart-9f4ed96e-75d7-4882-bbbd-3924f33fdfdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627205305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.2627205305
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.4110616197
Short name T1056
Test name
Test status
Simulation time 19203709 ps
CPU time 0.62 seconds
Started May 23 03:33:22 PM PDT 24
Finished May 23 03:33:25 PM PDT 24
Peak memory 194932 kb
Host smart-823b09c9-0b2b-4e88-b9dc-97d513bdfeb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110616197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.4110616197
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.1415820836
Short name T1029
Test name
Test status
Simulation time 27218683 ps
CPU time 0.63 seconds
Started May 23 03:33:20 PM PDT 24
Finished May 23 03:33:23 PM PDT 24
Peak memory 194920 kb
Host smart-d5e8f053-1de8-4640-839c-13bc02693f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415820836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.1415820836
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2247541254
Short name T1024
Test name
Test status
Simulation time 49985768 ps
CPU time 0.59 seconds
Started May 23 03:33:19 PM PDT 24
Finished May 23 03:33:22 PM PDT 24
Peak memory 194908 kb
Host smart-35ea01ba-9ba8-4cd0-9d33-4a435e19e8fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247541254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2247541254
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1938194782
Short name T155
Test name
Test status
Simulation time 252709558 ps
CPU time 0.81 seconds
Started May 23 03:32:47 PM PDT 24
Finished May 23 03:32:56 PM PDT 24
Peak memory 194912 kb
Host smart-1fc8ca9c-5390-48fe-af64-fca185dacb42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938194782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.1
938194782
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.3068087929
Short name T1112
Test name
Test status
Simulation time 817048612 ps
CPU time 3.27 seconds
Started May 23 03:32:46 PM PDT 24
Finished May 23 03:32:57 PM PDT 24
Peak memory 194996 kb
Host smart-81172e67-6de6-4c5b-bd87-9e38db305d1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068087929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.3
068087929
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.729364697
Short name T1006
Test name
Test status
Simulation time 30997221 ps
CPU time 0.67 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 196124 kb
Host smart-1f40a3fe-65ba-4587-9048-1f8359d64a24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729364697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.729364697
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2604010617
Short name T1070
Test name
Test status
Simulation time 50481619 ps
CPU time 1.23 seconds
Started May 23 03:32:46 PM PDT 24
Finished May 23 03:32:56 PM PDT 24
Peak memory 196092 kb
Host smart-ace1d5e2-68ab-4b2f-873e-984a3fd3645f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604010617 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.2604010617
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3025986052
Short name T99
Test name
Test status
Simulation time 115082586 ps
CPU time 0.62 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 194936 kb
Host smart-92fee185-f04d-430f-82ca-1931ea2c8d4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025986052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.3025986052
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1559615035
Short name T1119
Test name
Test status
Simulation time 31683875 ps
CPU time 0.68 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:51 PM PDT 24
Peak memory 194860 kb
Host smart-82543e8d-fe03-4b8b-b522-a33e093ab1db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559615035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1559615035
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3771415558
Short name T113
Test name
Test status
Simulation time 32710407 ps
CPU time 0.95 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:53 PM PDT 24
Peak memory 198388 kb
Host smart-7258da6e-fb0d-4522-bb19-0bad0c561b35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771415558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.3771415558
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.2933746616
Short name T76
Test name
Test status
Simulation time 64744528 ps
CPU time 1.04 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:51 PM PDT 24
Peak memory 195168 kb
Host smart-bb587b05-f498-4d6a-8c47-5d5f5559f574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933746616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.2933746616
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.3312102676
Short name T1044
Test name
Test status
Simulation time 234145564 ps
CPU time 1.53 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:50 PM PDT 24
Peak memory 195080 kb
Host smart-50782154-58c3-4e27-8bdd-214ef4b759c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312102676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.3312102676
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.3976913959
Short name T1036
Test name
Test status
Simulation time 100766882 ps
CPU time 0.6 seconds
Started May 23 03:33:20 PM PDT 24
Finished May 23 03:33:23 PM PDT 24
Peak memory 194924 kb
Host smart-49a54243-3c82-4899-900d-0be49bca41a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976913959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.3976913959
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.3851045180
Short name T1110
Test name
Test status
Simulation time 31306802 ps
CPU time 0.62 seconds
Started May 23 03:33:21 PM PDT 24
Finished May 23 03:33:24 PM PDT 24
Peak memory 194844 kb
Host smart-98379c66-da30-469b-9732-cbd7b9a8ef0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851045180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.3851045180
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.4174574402
Short name T1034
Test name
Test status
Simulation time 20663372 ps
CPU time 0.63 seconds
Started May 23 03:33:17 PM PDT 24
Finished May 23 03:33:19 PM PDT 24
Peak memory 194876 kb
Host smart-fd22a9a8-30c0-4b3a-9675-a04350262999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174574402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.4174574402
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2932990241
Short name T1074
Test name
Test status
Simulation time 47638778 ps
CPU time 0.59 seconds
Started May 23 03:33:21 PM PDT 24
Finished May 23 03:33:24 PM PDT 24
Peak memory 194916 kb
Host smart-cfe83683-8b3c-4fd1-85e7-2d6df1c25b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932990241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2932990241
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.4175544251
Short name T69
Test name
Test status
Simulation time 20043436 ps
CPU time 0.6 seconds
Started May 23 03:33:22 PM PDT 24
Finished May 23 03:33:25 PM PDT 24
Peak memory 194908 kb
Host smart-8c165749-44b8-4d7a-860d-00e7949473e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175544251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.4175544251
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.1860689754
Short name T70
Test name
Test status
Simulation time 21518704 ps
CPU time 0.63 seconds
Started May 23 03:33:13 PM PDT 24
Finished May 23 03:33:14 PM PDT 24
Peak memory 194960 kb
Host smart-ba1af234-2887-427c-8875-08ce72bc14a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860689754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.1860689754
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3601292417
Short name T152
Test name
Test status
Simulation time 19756701 ps
CPU time 0.62 seconds
Started May 23 03:33:23 PM PDT 24
Finished May 23 03:33:26 PM PDT 24
Peak memory 194884 kb
Host smart-10a2d0ee-6917-46ab-8aa4-c234b65b6c64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601292417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.3601292417
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.3473300433
Short name T1095
Test name
Test status
Simulation time 25470361 ps
CPU time 0.64 seconds
Started May 23 03:33:19 PM PDT 24
Finished May 23 03:33:21 PM PDT 24
Peak memory 194880 kb
Host smart-af793dc7-31cf-4508-8ff9-6c577f446bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473300433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.3473300433
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1760071859
Short name T1094
Test name
Test status
Simulation time 37158813 ps
CPU time 0.67 seconds
Started May 23 03:33:23 PM PDT 24
Finished May 23 03:33:26 PM PDT 24
Peak memory 194884 kb
Host smart-9406e7d4-d186-49bc-a707-e5521761a008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760071859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.1760071859
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3237664517
Short name T1077
Test name
Test status
Simulation time 45543707 ps
CPU time 0.59 seconds
Started May 23 03:33:21 PM PDT 24
Finished May 23 03:33:24 PM PDT 24
Peak memory 194844 kb
Host smart-9b2365de-9a24-4399-8264-cf8a47446e54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237664517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.3237664517
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3099502790
Short name T1015
Test name
Test status
Simulation time 324688056 ps
CPU time 1.34 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:50 PM PDT 24
Peak memory 197104 kb
Host smart-e568f9a5-be18-4f8b-9e57-ecfbd3316244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099502790 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.3099502790
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1367634618
Short name T157
Test name
Test status
Simulation time 22774750 ps
CPU time 0.66 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:48 PM PDT 24
Peak memory 197128 kb
Host smart-597c4942-f7be-43c6-95af-6e79d4c4ae0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367634618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.1367634618
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.1834636728
Short name T1118
Test name
Test status
Simulation time 46243513 ps
CPU time 0.59 seconds
Started May 23 03:32:47 PM PDT 24
Finished May 23 03:32:56 PM PDT 24
Peak memory 194864 kb
Host smart-72b27507-e0e1-4934-9294-b1a845766b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834636728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.1834636728
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2448125921
Short name T1063
Test name
Test status
Simulation time 29530562 ps
CPU time 0.71 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:51 PM PDT 24
Peak memory 197144 kb
Host smart-363e7fb7-f1f0-43c3-9e7e-2c481708c749
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448125921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2448125921
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2161882506
Short name T1098
Test name
Test status
Simulation time 467671365 ps
CPU time 2.16 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:53 PM PDT 24
Peak memory 200380 kb
Host smart-18be7b3c-ba32-4be3-8263-7c8ae1b10bb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161882506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.2161882506
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.1185105652
Short name T1045
Test name
Test status
Simulation time 139798276 ps
CPU time 1.09 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 200392 kb
Host smart-547868ef-3961-4a38-8a63-53e2f3cbc044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185105652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.1185105652
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2902549532
Short name T1012
Test name
Test status
Simulation time 94335610 ps
CPU time 0.81 seconds
Started May 23 03:32:48 PM PDT 24
Finished May 23 03:32:57 PM PDT 24
Peak memory 195036 kb
Host smart-205caaeb-44e1-4fe1-b06c-a1f8e2e1a26b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902549532 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.2902549532
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.2687549755
Short name T112
Test name
Test status
Simulation time 31204865 ps
CPU time 0.68 seconds
Started May 23 03:32:46 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 194984 kb
Host smart-1aded205-f8a4-48eb-8e02-546794ecf679
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687549755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.2687549755
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.158119087
Short name T1022
Test name
Test status
Simulation time 31329378 ps
CPU time 0.61 seconds
Started May 23 03:32:47 PM PDT 24
Finished May 23 03:32:56 PM PDT 24
Peak memory 194912 kb
Host smart-c2a504b0-27dc-401c-9624-ff68882227f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158119087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.158119087
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2994678336
Short name T111
Test name
Test status
Simulation time 118992547 ps
CPU time 0.69 seconds
Started May 23 03:32:47 PM PDT 24
Finished May 23 03:32:56 PM PDT 24
Peak memory 197140 kb
Host smart-49d05b0c-8989-4aac-95b3-0f01139cbcea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994678336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.2994678336
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.2505661935
Short name T1019
Test name
Test status
Simulation time 245294171 ps
CPU time 3 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:56 PM PDT 24
Peak memory 200436 kb
Host smart-02fafe87-45f5-4df4-af62-c2de04175640
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505661935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.2505661935
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2236535058
Short name T1117
Test name
Test status
Simulation time 229507734 ps
CPU time 1.12 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:53 PM PDT 24
Peak memory 200376 kb
Host smart-bb68f354-55e3-470c-a295-4c783461bdb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236535058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.2236535058
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2267119497
Short name T1073
Test name
Test status
Simulation time 40424123 ps
CPU time 0.96 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:51 PM PDT 24
Peak memory 195028 kb
Host smart-eb96e033-3fc2-4a4e-a204-22d8a4e0dad3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267119497 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.2267119497
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.982283890
Short name T1079
Test name
Test status
Simulation time 18748769 ps
CPU time 0.63 seconds
Started May 23 03:32:47 PM PDT 24
Finished May 23 03:32:56 PM PDT 24
Peak memory 197092 kb
Host smart-2b729399-b83c-47d0-a5a8-3acc611da611
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982283890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.982283890
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3297868433
Short name T1085
Test name
Test status
Simulation time 19701586 ps
CPU time 0.6 seconds
Started May 23 03:32:48 PM PDT 24
Finished May 23 03:32:57 PM PDT 24
Peak memory 194904 kb
Host smart-d31a74e7-d834-4bb5-8b8f-499f56b7522f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297868433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.3297868433
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3060214703
Short name T1087
Test name
Test status
Simulation time 31595450 ps
CPU time 0.77 seconds
Started May 23 03:32:47 PM PDT 24
Finished May 23 03:32:57 PM PDT 24
Peak memory 198180 kb
Host smart-ade852b4-5e79-4dbf-bd33-09ab018929ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060214703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.3060214703
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1780827993
Short name T1023
Test name
Test status
Simulation time 51773689 ps
CPU time 2.11 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:53 PM PDT 24
Peak memory 197200 kb
Host smart-f11d503f-dba3-44a1-b6df-03e550884038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780827993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.1780827993
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.4204961620
Short name T1115
Test name
Test status
Simulation time 804870773 ps
CPU time 1.08 seconds
Started May 23 03:32:48 PM PDT 24
Finished May 23 03:32:58 PM PDT 24
Peak memory 195060 kb
Host smart-e4760f7f-8f88-428f-9138-cec9f380bb2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204961620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.4204961620
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.114889840
Short name T1080
Test name
Test status
Simulation time 86609017 ps
CPU time 0.91 seconds
Started May 23 03:32:46 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 194896 kb
Host smart-ab21aa13-c0cc-443d-9eba-941084eb3dbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114889840 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.114889840
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.4225450174
Short name T101
Test name
Test status
Simulation time 21311930 ps
CPU time 0.66 seconds
Started May 23 03:32:47 PM PDT 24
Finished May 23 03:32:57 PM PDT 24
Peak memory 197360 kb
Host smart-595740dc-e796-4f07-ac9b-3ceef502630f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225450174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.4225450174
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.408526134
Short name T1107
Test name
Test status
Simulation time 35974614 ps
CPU time 0.6 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:53 PM PDT 24
Peak memory 194872 kb
Host smart-4d902f30-8461-46c2-9a6e-77c2b520917d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408526134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.408526134
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.4049084465
Short name T1052
Test name
Test status
Simulation time 52778969 ps
CPU time 0.71 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:52 PM PDT 24
Peak memory 197180 kb
Host smart-64f354b3-8a02-4c90-b015-4c066425dd6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049084465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.4049084465
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1459848200
Short name T1057
Test name
Test status
Simulation time 35250728 ps
CPU time 1.51 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 196108 kb
Host smart-130eb10b-695b-40e8-a8d4-03ea6e7d7b6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459848200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.1459848200
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.4069664622
Short name T1090
Test name
Test status
Simulation time 56570757 ps
CPU time 0.82 seconds
Started May 23 03:32:46 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 194916 kb
Host smart-b171d02e-f17e-479c-ab08-406139da3b70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069664622 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.4069664622
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2180013677
Short name T102
Test name
Test status
Simulation time 58806516 ps
CPU time 0.62 seconds
Started May 23 03:32:47 PM PDT 24
Finished May 23 03:32:56 PM PDT 24
Peak memory 194900 kb
Host smart-f49652e1-c0f6-49af-9275-9478b5b4739d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180013677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.2180013677
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.1772719513
Short name T1086
Test name
Test status
Simulation time 18289373 ps
CPU time 0.61 seconds
Started May 23 03:32:41 PM PDT 24
Finished May 23 03:32:45 PM PDT 24
Peak memory 194884 kb
Host smart-d40222e2-e436-4557-b9fc-d63681bd209c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772719513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.1772719513
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.543966815
Short name T1040
Test name
Test status
Simulation time 21602371 ps
CPU time 0.74 seconds
Started May 23 03:32:46 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 197236 kb
Host smart-193a50dc-1d3f-48ac-9c28-a0a27dc0717b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543966815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sam
e_csr_outstanding.543966815
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.856381288
Short name T1093
Test name
Test status
Simulation time 254054204 ps
CPU time 2.84 seconds
Started May 23 03:32:47 PM PDT 24
Finished May 23 03:32:59 PM PDT 24
Peak memory 197168 kb
Host smart-15dbf6c1-77fc-4fd5-b0be-fcce1cd9770e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856381288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.856381288
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2794573878
Short name T58
Test name
Test status
Simulation time 112695031 ps
CPU time 1.15 seconds
Started May 23 03:32:46 PM PDT 24
Finished May 23 03:32:55 PM PDT 24
Peak memory 199764 kb
Host smart-5d49c2c7-40ac-4236-b9f4-2e2e8f4027e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794573878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.2794573878
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.4223949006
Short name T4
Test name
Test status
Simulation time 24088821 ps
CPU time 0.77 seconds
Started May 23 03:35:54 PM PDT 24
Finished May 23 03:35:59 PM PDT 24
Peak memory 199348 kb
Host smart-905b7ac1-f2d9-4b1d-9c6b-dc97c7089940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223949006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.4223949006
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.1088986528
Short name T1003
Test name
Test status
Simulation time 51677838 ps
CPU time 0.8 seconds
Started May 23 03:35:56 PM PDT 24
Finished May 23 03:36:03 PM PDT 24
Peak memory 198708 kb
Host smart-f00e1972-b38e-4178-a706-2b4fdc2062f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088986528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.1088986528
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.3818078074
Short name T430
Test name
Test status
Simulation time 1259102308 ps
CPU time 0.98 seconds
Started May 23 03:35:55 PM PDT 24
Finished May 23 03:36:01 PM PDT 24
Peak memory 197632 kb
Host smart-cf678056-8c16-4c26-aea1-1dddedd13d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818078074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3818078074
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.208749206
Short name T1002
Test name
Test status
Simulation time 43720041 ps
CPU time 0.65 seconds
Started May 23 03:35:55 PM PDT 24
Finished May 23 03:36:01 PM PDT 24
Peak memory 196840 kb
Host smart-5dfebdd7-7f13-4fd6-8edd-f14ea16435c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208749206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.208749206
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.2497470120
Short name T793
Test name
Test status
Simulation time 52107974 ps
CPU time 0.62 seconds
Started May 23 03:35:58 PM PDT 24
Finished May 23 03:36:05 PM PDT 24
Peak memory 197608 kb
Host smart-939d8c14-cac9-43a0-9345-8edab221b8f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497470120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.2497470120
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.872301374
Short name T872
Test name
Test status
Simulation time 78418551 ps
CPU time 0.68 seconds
Started May 23 03:35:55 PM PDT 24
Finished May 23 03:36:02 PM PDT 24
Peak memory 200804 kb
Host smart-cef3919e-4a34-4f74-9c58-e54500e8af7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872301374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid
.872301374
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.388447611
Short name T727
Test name
Test status
Simulation time 38239212 ps
CPU time 0.66 seconds
Started May 23 03:35:57 PM PDT 24
Finished May 23 03:36:04 PM PDT 24
Peak memory 198672 kb
Host smart-100551df-7981-4f42-b69f-f63468fa686c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388447611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wak
eup_race.388447611
Directory /workspace/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.3848372886
Short name T397
Test name
Test status
Simulation time 72055717 ps
CPU time 0.82 seconds
Started May 23 03:35:57 PM PDT 24
Finished May 23 03:36:04 PM PDT 24
Peak memory 199420 kb
Host smart-5f01d54a-592d-486a-a519-77eea7ab592e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848372886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.3848372886
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.1746051667
Short name T327
Test name
Test status
Simulation time 118369822 ps
CPU time 0.89 seconds
Started May 23 03:35:57 PM PDT 24
Finished May 23 03:36:04 PM PDT 24
Peak memory 208872 kb
Host smart-2dea7c24-513c-4f94-8367-62f910699b47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746051667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.1746051667
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.817360991
Short name T18
Test name
Test status
Simulation time 802270225 ps
CPU time 1.1 seconds
Started May 23 03:35:54 PM PDT 24
Finished May 23 03:36:00 PM PDT 24
Peak memory 217200 kb
Host smart-2f0a2607-d442-4624-811d-c6d5caa5339d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817360991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.817360991
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.3594677644
Short name T358
Test name
Test status
Simulation time 298977700 ps
CPU time 1.42 seconds
Started May 23 03:35:57 PM PDT 24
Finished May 23 03:36:05 PM PDT 24
Peak memory 200468 kb
Host smart-6669fa39-f2f1-4625-9f37-2b75b7080cf7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594677644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_c
m_ctrl_config_regwen.3594677644
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2616195043
Short name T864
Test name
Test status
Simulation time 1463362008 ps
CPU time 2.16 seconds
Started May 23 03:35:58 PM PDT 24
Finished May 23 03:36:06 PM PDT 24
Peak memory 200528 kb
Host smart-47711c2f-6061-451f-aa16-2667c6930e48
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616195043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2616195043
Directory /workspace/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3416536684
Short name T758
Test name
Test status
Simulation time 170354705 ps
CPU time 0.9 seconds
Started May 23 03:35:58 PM PDT 24
Finished May 23 03:36:05 PM PDT 24
Peak memory 198752 kb
Host smart-c166cbf8-2926-488a-b722-2f67b1955f15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416536684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3416536684
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.4043172978
Short name T923
Test name
Test status
Simulation time 37997013 ps
CPU time 0.66 seconds
Started May 23 03:35:56 PM PDT 24
Finished May 23 03:36:03 PM PDT 24
Peak memory 198828 kb
Host smart-41676634-2e62-4df8-8c21-f2f84145b4a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043172978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.4043172978
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all.2720159230
Short name T993
Test name
Test status
Simulation time 467604158 ps
CPU time 2.38 seconds
Started May 23 03:35:54 PM PDT 24
Finished May 23 03:36:01 PM PDT 24
Peak memory 200652 kb
Host smart-b10dfc1d-9348-41b3-9f45-930a66dcb54c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720159230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.2720159230
Directory /workspace/0.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all_with_rand_reset.2649180318
Short name T994
Test name
Test status
Simulation time 7997091430 ps
CPU time 12.25 seconds
Started May 23 03:35:56 PM PDT 24
Finished May 23 03:36:14 PM PDT 24
Peak memory 200876 kb
Host smart-f6795cce-fff0-4a83-a339-cd0184cf99d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649180318 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all_with_rand_reset.2649180318
Directory /workspace/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup.2687082853
Short name T203
Test name
Test status
Simulation time 332728464 ps
CPU time 1.08 seconds
Started May 23 03:35:56 PM PDT 24
Finished May 23 03:36:03 PM PDT 24
Peak memory 198996 kb
Host smart-b344a4f4-83e9-4e17-b766-4f8ee1ecb8c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687082853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.2687082853
Directory /workspace/0.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.3188385515
Short name T981
Test name
Test status
Simulation time 319804812 ps
CPU time 1.51 seconds
Started May 23 03:35:57 PM PDT 24
Finished May 23 03:36:04 PM PDT 24
Peak memory 200572 kb
Host smart-53a725ee-916f-43b2-8b8f-1d6493d6d1b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188385515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.3188385515
Directory /workspace/0.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.2637699059
Short name T538
Test name
Test status
Simulation time 133536410 ps
CPU time 0.86 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 199516 kb
Host smart-1c1b45a2-d307-4ead-ab3d-6baa8fdea7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637699059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.2637699059
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.2832462626
Short name T678
Test name
Test status
Simulation time 70341378 ps
CPU time 0.75 seconds
Started May 23 03:36:11 PM PDT 24
Finished May 23 03:36:19 PM PDT 24
Peak memory 198616 kb
Host smart-0b6acea4-dce2-4c8e-892e-72f510cd7a3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832462626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.2832462626
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.566431081
Short name T652
Test name
Test status
Simulation time 83541330 ps
CPU time 0.63 seconds
Started May 23 03:36:08 PM PDT 24
Finished May 23 03:36:12 PM PDT 24
Peak memory 197568 kb
Host smart-78646d85-cd3a-48bc-ad64-ba25da497d5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566431081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_m
alfunc.566431081
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.2746627749
Short name T298
Test name
Test status
Simulation time 630843875 ps
CPU time 0.94 seconds
Started May 23 03:36:13 PM PDT 24
Finished May 23 03:36:21 PM PDT 24
Peak memory 197628 kb
Host smart-bf23ecd3-3a1f-486e-9271-e057d89f2709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746627749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.2746627749
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.1971134808
Short name T303
Test name
Test status
Simulation time 45371534 ps
CPU time 0.66 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 197640 kb
Host smart-a1de7a21-8f22-4ec0-807e-7bfe448f1e30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971134808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.1971134808
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.980570782
Short name T227
Test name
Test status
Simulation time 131558088 ps
CPU time 0.66 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:17 PM PDT 24
Peak memory 200820 kb
Host smart-ba7f0910-1d81-42dd-a8cb-ecf08803b7f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980570782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invalid
.980570782
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.352304793
Short name T524
Test name
Test status
Simulation time 336999884 ps
CPU time 0.79 seconds
Started May 23 03:35:58 PM PDT 24
Finished May 23 03:36:05 PM PDT 24
Peak memory 198060 kb
Host smart-7feaea15-4bae-4f6e-b5d1-6ea20fc0cc64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352304793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wak
eup_race.352304793
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.2036337270
Short name T698
Test name
Test status
Simulation time 32149395 ps
CPU time 0.71 seconds
Started May 23 03:36:01 PM PDT 24
Finished May 23 03:36:07 PM PDT 24
Peak memory 198656 kb
Host smart-0f43336b-11e8-41c0-8ab4-eee7dac1b036
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036337270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.2036337270
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.2988660964
Short name T934
Test name
Test status
Simulation time 169872587 ps
CPU time 0.81 seconds
Started May 23 03:36:11 PM PDT 24
Finished May 23 03:36:18 PM PDT 24
Peak memory 208988 kb
Host smart-cab79a14-356c-419a-b04b-7415928933e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988660964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.2988660964
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.2592409060
Short name T27
Test name
Test status
Simulation time 671926865 ps
CPU time 1.57 seconds
Started May 23 03:36:08 PM PDT 24
Finished May 23 03:36:13 PM PDT 24
Peak memory 217416 kb
Host smart-ad184240-8b78-4392-9c54-9d3f32d17019
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592409060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.2592409060
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2887948162
Short name T471
Test name
Test status
Simulation time 751829523 ps
CPU time 2.86 seconds
Started May 23 03:36:11 PM PDT 24
Finished May 23 03:36:21 PM PDT 24
Peak memory 200584 kb
Host smart-9816f750-9f0d-4db6-9dcb-d1fa1eb2e52a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887948162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2887948162
Directory /workspace/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3887740798
Short name T373
Test name
Test status
Simulation time 983652549 ps
CPU time 2.67 seconds
Started May 23 03:36:09 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 200536 kb
Host smart-ea1b6787-eef5-4927-b516-0690d68f1898
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887740798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3887740798
Directory /workspace/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.3118918567
Short name T275
Test name
Test status
Simulation time 94170971 ps
CPU time 0.8 seconds
Started May 23 03:36:09 PM PDT 24
Finished May 23 03:36:14 PM PDT 24
Peak memory 198800 kb
Host smart-4baec924-e365-4f61-beb2-149fe0ea058b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118918567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3118918567
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.1328230548
Short name T366
Test name
Test status
Simulation time 29115496 ps
CPU time 0.7 seconds
Started May 23 03:35:55 PM PDT 24
Finished May 23 03:36:00 PM PDT 24
Peak memory 198836 kb
Host smart-724bbe9e-170d-428b-925a-8c5904ceb996
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328230548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.1328230548
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all.2020443836
Short name T891
Test name
Test status
Simulation time 2558218791 ps
CPU time 3.61 seconds
Started May 23 03:36:08 PM PDT 24
Finished May 23 03:36:15 PM PDT 24
Peak memory 200748 kb
Host smart-5b3f6da0-9b31-4e50-94d0-cca811c3a87d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020443836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.2020443836
Directory /workspace/1.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all_with_rand_reset.1637808958
Short name T124
Test name
Test status
Simulation time 12732467241 ps
CPU time 25.69 seconds
Started May 23 03:36:18 PM PDT 24
Finished May 23 03:36:51 PM PDT 24
Peak memory 200868 kb
Host smart-af00b39a-96eb-47e3-9d4f-4288a680581c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637808958 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all_with_rand_reset.1637808958
Directory /workspace/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup.1629723974
Short name T463
Test name
Test status
Simulation time 108186785 ps
CPU time 0.92 seconds
Started May 23 03:35:57 PM PDT 24
Finished May 23 03:36:05 PM PDT 24
Peak memory 198108 kb
Host smart-af690803-e383-46bd-9e05-6d7ffa937734
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629723974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.1629723974
Directory /workspace/1.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup_reset.1320529666
Short name T440
Test name
Test status
Simulation time 79905762 ps
CPU time 0.83 seconds
Started May 23 03:36:09 PM PDT 24
Finished May 23 03:36:14 PM PDT 24
Peak memory 198540 kb
Host smart-7d570538-0d64-4644-b6fc-0510e100a056
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320529666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.1320529666
Directory /workspace/1.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.213065759
Short name T594
Test name
Test status
Simulation time 23477030 ps
CPU time 0.75 seconds
Started May 23 03:36:34 PM PDT 24
Finished May 23 03:36:37 PM PDT 24
Peak memory 199036 kb
Host smart-fd905a3e-6b05-4be6-a635-5ce4a74003df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213065759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.213065759
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.2668147455
Short name T742
Test name
Test status
Simulation time 52455002 ps
CPU time 0.79 seconds
Started May 23 03:36:38 PM PDT 24
Finished May 23 03:36:43 PM PDT 24
Peak memory 198672 kb
Host smart-8fdd2e4f-a814-4d97-999a-2e53e9a31e48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668147455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.2668147455
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.2609818858
Short name T450
Test name
Test status
Simulation time 28939500 ps
CPU time 0.64 seconds
Started May 23 03:36:36 PM PDT 24
Finished May 23 03:36:39 PM PDT 24
Peak memory 197504 kb
Host smart-57008a81-5bf8-4fc8-8a4b-9b1f53f070cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609818858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.2609818858
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.3376594979
Short name T831
Test name
Test status
Simulation time 678648836 ps
CPU time 0.96 seconds
Started May 23 03:36:34 PM PDT 24
Finished May 23 03:36:38 PM PDT 24
Peak memory 197652 kb
Host smart-7da87077-3271-499c-aaef-79e04af59e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376594979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.3376594979
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.771899108
Short name T918
Test name
Test status
Simulation time 33196553 ps
CPU time 0.64 seconds
Started May 23 03:36:38 PM PDT 24
Finished May 23 03:36:43 PM PDT 24
Peak memory 196816 kb
Host smart-3e32e748-4aea-45e6-a2d1-a912b43907a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771899108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.771899108
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.1409548583
Short name T810
Test name
Test status
Simulation time 60430467 ps
CPU time 0.6 seconds
Started May 23 03:36:34 PM PDT 24
Finished May 23 03:36:37 PM PDT 24
Peak memory 197612 kb
Host smart-743b53df-0407-40ba-be96-7fea5ad6d9aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409548583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.1409548583
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.1423791315
Short name T651
Test name
Test status
Simulation time 39122742 ps
CPU time 0.73 seconds
Started May 23 03:36:38 PM PDT 24
Finished May 23 03:36:42 PM PDT 24
Peak memory 200816 kb
Host smart-ada549a6-6b4c-4afd-8db1-40a5aa5a1081
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423791315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.1423791315
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.478402796
Short name T497
Test name
Test status
Simulation time 178261349 ps
CPU time 0.78 seconds
Started May 23 03:36:42 PM PDT 24
Finished May 23 03:36:47 PM PDT 24
Peak memory 198048 kb
Host smart-202439fd-44cf-4e2f-8007-7afdeb6df1d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478402796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wa
keup_race.478402796
Directory /workspace/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.972412606
Short name T260
Test name
Test status
Simulation time 475281084 ps
CPU time 0.86 seconds
Started May 23 03:36:36 PM PDT 24
Finished May 23 03:36:40 PM PDT 24
Peak memory 199464 kb
Host smart-a8e49809-d4ce-4fd1-a369-f83aa4563275
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972412606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.972412606
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.3190213278
Short name T658
Test name
Test status
Simulation time 114656661 ps
CPU time 0.98 seconds
Started May 23 03:36:34 PM PDT 24
Finished May 23 03:36:37 PM PDT 24
Peak memory 208932 kb
Host smart-5fd42667-42f7-47fa-98cd-9e81f9756b51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190213278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.3190213278
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.4196716201
Short name T749
Test name
Test status
Simulation time 281402797 ps
CPU time 1.38 seconds
Started May 23 03:36:35 PM PDT 24
Finished May 23 03:36:39 PM PDT 24
Peak memory 200472 kb
Host smart-6c0f0e71-f491-4c77-aff7-59a4ad8f823b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196716201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_
cm_ctrl_config_regwen.4196716201
Directory /workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.885130759
Short name T914
Test name
Test status
Simulation time 1003774584 ps
CPU time 2.44 seconds
Started May 23 03:36:38 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 200656 kb
Host smart-a67e99a2-15b5-415b-a726-30940dbaba03
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885130759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.885130759
Directory /workspace/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3078490511
Short name T746
Test name
Test status
Simulation time 1008416241 ps
CPU time 2.44 seconds
Started May 23 03:36:38 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 200592 kb
Host smart-950a840b-e03e-41fd-9e9f-417345c790ca
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078490511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3078490511
Directory /workspace/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2500990476
Short name T827
Test name
Test status
Simulation time 97383978 ps
CPU time 0.86 seconds
Started May 23 03:36:35 PM PDT 24
Finished May 23 03:36:39 PM PDT 24
Peak memory 198988 kb
Host smart-31ac0ff0-7928-4c5b-a106-69b6666c5515
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500990476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2500990476
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.2781331475
Short name T634
Test name
Test status
Simulation time 53146335 ps
CPU time 0.65 seconds
Started May 23 03:36:34 PM PDT 24
Finished May 23 03:36:37 PM PDT 24
Peak memory 198948 kb
Host smart-f19de135-5fce-48be-93b6-aa51383c19ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781331475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2781331475
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all.1967563317
Short name T582
Test name
Test status
Simulation time 2858253185 ps
CPU time 4.05 seconds
Started May 23 03:36:34 PM PDT 24
Finished May 23 03:36:40 PM PDT 24
Peak memory 200792 kb
Host smart-14f87ba4-f8b4-4754-98d2-05cd5d13a459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967563317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.1967563317
Directory /workspace/10.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup.103775277
Short name T519
Test name
Test status
Simulation time 290526232 ps
CPU time 0.93 seconds
Started May 23 03:36:42 PM PDT 24
Finished May 23 03:36:48 PM PDT 24
Peak memory 199296 kb
Host smart-4e073355-02b5-4bc5-a15f-a5335fedcaf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103775277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.103775277
Directory /workspace/10.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup_reset.1814790632
Short name T621
Test name
Test status
Simulation time 337119582 ps
CPU time 0.91 seconds
Started May 23 03:36:33 PM PDT 24
Finished May 23 03:36:36 PM PDT 24
Peak memory 199652 kb
Host smart-8c2c4ed9-b314-4bd2-94ce-b817ef0aa7cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814790632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.1814790632
Directory /workspace/10.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.1825084389
Short name T235
Test name
Test status
Simulation time 112965490 ps
CPU time 0.89 seconds
Started May 23 03:36:36 PM PDT 24
Finished May 23 03:36:40 PM PDT 24
Peak memory 199704 kb
Host smart-b410cdf8-6e71-4a7a-9079-93b275732653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825084389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.1825084389
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.882253076
Short name T162
Test name
Test status
Simulation time 63560557 ps
CPU time 0.85 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 198536 kb
Host smart-e6eb0dd6-17c5-4b84-812c-ceb31ef3b10f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882253076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disa
ble_rom_integrity_check.882253076
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.468443458
Short name T483
Test name
Test status
Simulation time 38148599 ps
CPU time 0.6 seconds
Started May 23 03:36:38 PM PDT 24
Finished May 23 03:36:42 PM PDT 24
Peak memory 197564 kb
Host smart-0bd783d8-1f96-43c1-a11b-1261444b594d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468443458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_
malfunc.468443458
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.1585635375
Short name T559
Test name
Test status
Simulation time 635433566 ps
CPU time 0.99 seconds
Started May 23 03:36:38 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 197696 kb
Host smart-13fb90cc-c413-4b83-acc3-2e287f77a238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585635375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.1585635375
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.497273619
Short name T603
Test name
Test status
Simulation time 25532482 ps
CPU time 0.63 seconds
Started May 23 03:36:37 PM PDT 24
Finished May 23 03:36:42 PM PDT 24
Peak memory 197656 kb
Host smart-b1ce4d25-03fe-41e3-ae30-34daee0db05f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497273619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.497273619
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.2079230878
Short name T175
Test name
Test status
Simulation time 35466391 ps
CPU time 0.64 seconds
Started May 23 03:36:37 PM PDT 24
Finished May 23 03:36:42 PM PDT 24
Peak memory 197628 kb
Host smart-f158ff9c-7756-45ec-960c-f6ed4173149b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079230878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.2079230878
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.730788868
Short name T609
Test name
Test status
Simulation time 42391176 ps
CPU time 0.75 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 200740 kb
Host smart-f5069aee-358a-4d3a-840a-2bc0a6762a3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730788868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invali
d.730788868
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_wakeup_race.1320047207
Short name T502
Test name
Test status
Simulation time 79715231 ps
CPU time 0.66 seconds
Started May 23 03:36:40 PM PDT 24
Finished May 23 03:36:46 PM PDT 24
Peak memory 197792 kb
Host smart-c608d260-e6ce-4dbd-8a55-dfd8dec3f91b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320047207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_w
akeup_race.1320047207
Directory /workspace/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.3315443787
Short name T272
Test name
Test status
Simulation time 109590373 ps
CPU time 0.76 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 198616 kb
Host smart-d0fde2ce-f5a7-4ae2-8ada-c24c1f2529f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315443787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.3315443787
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.1599746319
Short name T527
Test name
Test status
Simulation time 147091856 ps
CPU time 0.89 seconds
Started May 23 03:36:35 PM PDT 24
Finished May 23 03:36:38 PM PDT 24
Peak memory 208880 kb
Host smart-d70ad6ea-1340-4689-80e5-5a71d007dbf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599746319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.1599746319
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.87019024
Short name T467
Test name
Test status
Simulation time 316862470 ps
CPU time 1.11 seconds
Started May 23 03:36:36 PM PDT 24
Finished May 23 03:36:40 PM PDT 24
Peak memory 200320 kb
Host smart-bf5d82a9-fb2b-492a-a04d-7b2d82a6965f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87019024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm
_ctrl_config_regwen.87019024
Directory /workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2623550611
Short name T855
Test name
Test status
Simulation time 1045003200 ps
CPU time 2.45 seconds
Started May 23 03:36:37 PM PDT 24
Finished May 23 03:36:43 PM PDT 24
Peak memory 200280 kb
Host smart-af38951b-c6e9-4f78-b7d3-90436d348ec6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623550611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2623550611
Directory /workspace/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2265137063
Short name T535
Test name
Test status
Simulation time 87286012 ps
CPU time 0.87 seconds
Started May 23 03:36:38 PM PDT 24
Finished May 23 03:36:43 PM PDT 24
Peak memory 198696 kb
Host smart-4359e05a-3ed6-4f81-ac8c-a9e58b15aefb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265137063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2265137063
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.2967114307
Short name T491
Test name
Test status
Simulation time 70543372 ps
CPU time 0.66 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 198060 kb
Host smart-026f8a12-9915-4dd0-95ba-0ca8292b5c2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967114307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.2967114307
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all.3218061091
Short name T336
Test name
Test status
Simulation time 2249015735 ps
CPU time 4.7 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:48 PM PDT 24
Peak memory 200756 kb
Host smart-c90a37d3-6e41-4e90-963e-4837771fa27b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218061091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.3218061091
Directory /workspace/11.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all_with_rand_reset.3423318652
Short name T116
Test name
Test status
Simulation time 4692333894 ps
CPU time 8.04 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:51 PM PDT 24
Peak memory 200848 kb
Host smart-b01ad1a4-6b98-484a-b6a4-6e20da510ed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423318652 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all_with_rand_reset.3423318652
Directory /workspace/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup.1704385629
Short name T30
Test name
Test status
Simulation time 310652509 ps
CPU time 1.17 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 199296 kb
Host smart-80850c4e-7b6d-456d-a4ff-1a0a77e9030d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704385629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.1704385629
Directory /workspace/11.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup_reset.1615447749
Short name T172
Test name
Test status
Simulation time 227354335 ps
CPU time 1.08 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 199476 kb
Host smart-20fbad67-2bb5-45da-a192-5f6e9dda5cb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615447749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.1615447749
Directory /workspace/11.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.4075987507
Short name T301
Test name
Test status
Simulation time 20933089 ps
CPU time 0.7 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 198676 kb
Host smart-5b955424-3521-4dba-a98e-faa1e99c0b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075987507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.4075987507
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.2859798561
Short name T160
Test name
Test status
Simulation time 50327334 ps
CPU time 0.74 seconds
Started May 23 03:36:41 PM PDT 24
Finished May 23 03:36:46 PM PDT 24
Peak memory 198108 kb
Host smart-4d00e497-43ca-4c18-9f09-90c26d8f01e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859798561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.2859798561
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.2898778487
Short name T978
Test name
Test status
Simulation time 34033830 ps
CPU time 0.67 seconds
Started May 23 03:36:35 PM PDT 24
Finished May 23 03:36:38 PM PDT 24
Peak memory 197540 kb
Host smart-b33b5339-ca29-47ab-a0cc-dc50942beb17
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898778487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.2898778487
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.1123955449
Short name T13
Test name
Test status
Simulation time 947540533 ps
CPU time 1.03 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 197648 kb
Host smart-171be21d-ff6e-40d4-86f4-6d903970e0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123955449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.1123955449
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.1897469386
Short name T927
Test name
Test status
Simulation time 50227987 ps
CPU time 0.61 seconds
Started May 23 03:36:41 PM PDT 24
Finished May 23 03:36:46 PM PDT 24
Peak memory 197680 kb
Host smart-743826eb-0777-41d2-9b21-c097328f6cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897469386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1897469386
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.4072547059
Short name T705
Test name
Test status
Simulation time 199620384 ps
CPU time 0.61 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:43 PM PDT 24
Peak memory 197912 kb
Host smart-8fcce091-fa4d-4fd7-a514-e35edf833889
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072547059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.4072547059
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.1628714364
Short name T972
Test name
Test status
Simulation time 44671957 ps
CPU time 0.7 seconds
Started May 23 03:36:38 PM PDT 24
Finished May 23 03:36:42 PM PDT 24
Peak memory 200836 kb
Host smart-d12ae726-77d0-4633-acb8-2a208d3d35f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628714364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.1628714364
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.758970098
Short name T36
Test name
Test status
Simulation time 443593658 ps
CPU time 0.72 seconds
Started May 23 03:36:40 PM PDT 24
Finished May 23 03:36:46 PM PDT 24
Peak memory 197884 kb
Host smart-09d74147-cc0f-416b-853f-8411755b9318
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758970098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wa
keup_race.758970098
Directory /workspace/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.864093310
Short name T416
Test name
Test status
Simulation time 93556688 ps
CPU time 0.81 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 198636 kb
Host smart-45c985e5-fa84-4b84-a5d7-689478d15bb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864093310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.864093310
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.3036633982
Short name T507
Test name
Test status
Simulation time 233146345 ps
CPU time 0.77 seconds
Started May 23 03:36:40 PM PDT 24
Finished May 23 03:36:46 PM PDT 24
Peak memory 209028 kb
Host smart-53d5010a-bd82-4a9f-841d-e48882373f16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036633982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.3036633982
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.3416856274
Short name T661
Test name
Test status
Simulation time 84505496 ps
CPU time 0.79 seconds
Started May 23 03:36:37 PM PDT 24
Finished May 23 03:36:41 PM PDT 24
Peak memory 198368 kb
Host smart-450b5348-270e-4f3e-8b96-c6e8676d3080
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416856274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_
cm_ctrl_config_regwen.3416856274
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2185584628
Short name T672
Test name
Test status
Simulation time 772920285 ps
CPU time 3 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:46 PM PDT 24
Peak memory 200568 kb
Host smart-1e738d5c-3a41-4c32-af54-5c19070fa306
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185584628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2185584628
Directory /workspace/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.721596761
Short name T271
Test name
Test status
Simulation time 798248801 ps
CPU time 2.92 seconds
Started May 23 03:36:40 PM PDT 24
Finished May 23 03:36:48 PM PDT 24
Peak memory 200528 kb
Host smart-88207fe1-3281-42de-83a2-8ba310f16fe6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721596761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.721596761
Directory /workspace/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1523590487
Short name T853
Test name
Test status
Simulation time 203894202 ps
CPU time 0.89 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 198604 kb
Host smart-991e6fa6-4026-4751-9dbd-5a3979c59bd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523590487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1523590487
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.1845143960
Short name T974
Test name
Test status
Simulation time 64385544 ps
CPU time 0.69 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 198084 kb
Host smart-f76ca193-75ca-4ed6-a999-5eaa958fd073
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845143960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.1845143960
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all.2237653763
Short name T702
Test name
Test status
Simulation time 1722222264 ps
CPU time 4.33 seconds
Started May 23 03:36:57 PM PDT 24
Finished May 23 03:37:09 PM PDT 24
Peak memory 200684 kb
Host smart-dacf4951-7203-414f-9185-4b83437ef296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237653763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.2237653763
Directory /workspace/12.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all_with_rand_reset.3568296968
Short name T21
Test name
Test status
Simulation time 5313903149 ps
CPU time 16.93 seconds
Started May 23 03:36:49 PM PDT 24
Finished May 23 03:37:07 PM PDT 24
Peak memory 200904 kb
Host smart-0e4bbdcc-e892-4265-834b-5d198a310c9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568296968 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all_with_rand_reset.3568296968
Directory /workspace/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup.2170089361
Short name T728
Test name
Test status
Simulation time 33310194 ps
CPU time 0.66 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 197736 kb
Host smart-7e457ad8-9199-4e03-a280-cf1b80666708
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170089361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.2170089361
Directory /workspace/12.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup_reset.3291030514
Short name T258
Test name
Test status
Simulation time 241350847 ps
CPU time 0.88 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 199520 kb
Host smart-a5e12812-d804-432b-8193-1360b38b6c10
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291030514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.3291030514
Directory /workspace/12.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.101927677
Short name T590
Test name
Test status
Simulation time 57053693 ps
CPU time 0.68 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:58 PM PDT 24
Peak memory 198644 kb
Host smart-ab543c0f-66ce-428e-ae50-9ff3d48fec5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101927677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.101927677
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.2947444339
Short name T861
Test name
Test status
Simulation time 69055597 ps
CPU time 0.74 seconds
Started May 23 03:36:52 PM PDT 24
Finished May 23 03:36:56 PM PDT 24
Peak memory 198252 kb
Host smart-ebbb48fa-da44-457f-be93-eb35665610de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947444339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.2947444339
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.2842835007
Short name T323
Test name
Test status
Simulation time 30617261 ps
CPU time 0.69 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:02 PM PDT 24
Peak memory 197552 kb
Host smart-078e6741-fa3b-443a-8304-70737247e5f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842835007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.2842835007
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.4060998907
Short name T529
Test name
Test status
Simulation time 316469548 ps
CPU time 1.02 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:36:59 PM PDT 24
Peak memory 197644 kb
Host smart-bdb19b4e-3ae8-4567-a31f-6d924e9c349a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060998907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.4060998907
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.3761394792
Short name T16
Test name
Test status
Simulation time 76373011 ps
CPU time 0.62 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:36:59 PM PDT 24
Peak memory 197612 kb
Host smart-853b4956-b699-46eb-a341-f9ae4ae55d9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761394792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.3761394792
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.1496202765
Short name T862
Test name
Test status
Simulation time 117220605 ps
CPU time 0.61 seconds
Started May 23 03:36:50 PM PDT 24
Finished May 23 03:36:51 PM PDT 24
Peak memory 197624 kb
Host smart-0ff6a013-815d-4cd5-af1a-580bba9836f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496202765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.1496202765
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.1131284303
Short name T537
Test name
Test status
Simulation time 76724136 ps
CPU time 0.67 seconds
Started May 23 03:36:52 PM PDT 24
Finished May 23 03:36:54 PM PDT 24
Peak memory 200884 kb
Host smart-46a2ad0e-13c0-449b-b1d1-5d3a38d605df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131284303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.1131284303
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_wakeup_race.2582394233
Short name T917
Test name
Test status
Simulation time 288281290 ps
CPU time 1 seconds
Started May 23 03:36:50 PM PDT 24
Finished May 23 03:36:52 PM PDT 24
Peak memory 199252 kb
Host smart-db7e9ce7-ac29-42e4-9989-f7d24115cf03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582394233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_w
akeup_race.2582394233
Directory /workspace/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.2458615636
Short name T739
Test name
Test status
Simulation time 62115344 ps
CPU time 0.7 seconds
Started May 23 03:36:52 PM PDT 24
Finished May 23 03:36:56 PM PDT 24
Peak memory 197944 kb
Host smart-ba299ba1-fbab-45d7-9a42-84ccb5e27ad4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458615636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.2458615636
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.3430366848
Short name T291
Test name
Test status
Simulation time 113166066 ps
CPU time 0.98 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:57 PM PDT 24
Peak memory 208980 kb
Host smart-5cdfbac3-3222-4bc1-8ebd-89624ca33e36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430366848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.3430366848
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.2579317831
Short name T333
Test name
Test status
Simulation time 178242412 ps
CPU time 0.81 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:01 PM PDT 24
Peak memory 199512 kb
Host smart-82833450-8ffb-4721-a0af-0e49becc8ac2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579317831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_
cm_ctrl_config_regwen.2579317831
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1759425440
Short name T352
Test name
Test status
Simulation time 1253859908 ps
CPU time 2.18 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:58 PM PDT 24
Peak memory 200556 kb
Host smart-d5a587a2-deec-4525-99c4-6a323cc11230
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759425440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1759425440
Directory /workspace/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.423253422
Short name T625
Test name
Test status
Simulation time 1035768669 ps
CPU time 1.95 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:37:00 PM PDT 24
Peak memory 200564 kb
Host smart-8bfe71a1-adcb-4812-bbb3-4b3be9d5fec9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423253422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.423253422
Directory /workspace/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.4148022649
Short name T956
Test name
Test status
Simulation time 147406789 ps
CPU time 0.86 seconds
Started May 23 03:36:52 PM PDT 24
Finished May 23 03:36:55 PM PDT 24
Peak memory 198896 kb
Host smart-b9782929-faf6-4b43-9123-5d2c5b6b595c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148022649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4148022649
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.186040964
Short name T306
Test name
Test status
Simulation time 32623120 ps
CPU time 0.68 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:02 PM PDT 24
Peak memory 198012 kb
Host smart-2d70d32a-c2a1-46e1-bac3-506bf887d323
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186040964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.186040964
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all.3768109437
Short name T170
Test name
Test status
Simulation time 314064697 ps
CPU time 1.56 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:59 PM PDT 24
Peak memory 200520 kb
Host smart-3826a31b-c86d-4879-b92e-950854c3c9a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768109437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.3768109437
Directory /workspace/13.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all_with_rand_reset.1090549434
Short name T920
Test name
Test status
Simulation time 27766105671 ps
CPU time 22.46 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:26 PM PDT 24
Peak memory 200956 kb
Host smart-8b157740-9ca8-4880-86a1-9c441814489a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090549434 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all_with_rand_reset.1090549434
Directory /workspace/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup.1753874571
Short name T552
Test name
Test status
Simulation time 127231028 ps
CPU time 0.88 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:57 PM PDT 24
Peak memory 198636 kb
Host smart-b2e656e4-78b1-4552-9766-8166eae9cf3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753874571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.1753874571
Directory /workspace/13.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup_reset.2851701810
Short name T883
Test name
Test status
Simulation time 116049192 ps
CPU time 0.75 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:14 PM PDT 24
Peak memory 198680 kb
Host smart-b165f29a-a2dd-4b79-b900-937924f43b47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851701810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.2851701810
Directory /workspace/13.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.1249993335
Short name T877
Test name
Test status
Simulation time 29049477 ps
CPU time 0.89 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:57 PM PDT 24
Peak memory 199776 kb
Host smart-f1216964-f355-4912-abf3-694750225a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249993335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1249993335
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.2603098789
Short name T646
Test name
Test status
Simulation time 142916332 ps
CPU time 0.71 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:57 PM PDT 24
Peak memory 198672 kb
Host smart-d9189bce-c937-4335-ae2d-fbab333e8591
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603098789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.2603098789
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1258129118
Short name T139
Test name
Test status
Simulation time 29799854 ps
CPU time 0.65 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:58 PM PDT 24
Peak memory 197552 kb
Host smart-055feeee-b4de-47ea-9d44-cee7d5335bd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258129118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.1258129118
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.1522295443
Short name T406
Test name
Test status
Simulation time 611864165 ps
CPU time 1.01 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:00 PM PDT 24
Peak memory 197624 kb
Host smart-353a9ff0-c7e0-4d9b-937f-b132f11ac067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522295443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.1522295443
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.603160935
Short name T763
Test name
Test status
Simulation time 41203586 ps
CPU time 0.64 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:02 PM PDT 24
Peak memory 197564 kb
Host smart-59f0007a-31d2-4482-a739-6da7469e1a55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603160935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.603160935
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.3799754012
Short name T325
Test name
Test status
Simulation time 38807583 ps
CPU time 0.68 seconds
Started May 23 03:36:52 PM PDT 24
Finished May 23 03:36:56 PM PDT 24
Peak memory 197940 kb
Host smart-960156b0-6dc4-4938-9104-47620cf335ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799754012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.3799754012
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.4236677898
Short name T622
Test name
Test status
Simulation time 84029994 ps
CPU time 0.68 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:57 PM PDT 24
Peak memory 200856 kb
Host smart-11e6f84d-56b9-4bc2-b803-77418f6230f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236677898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.4236677898
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.1665610886
Short name T197
Test name
Test status
Simulation time 221919351 ps
CPU time 1.13 seconds
Started May 23 03:36:52 PM PDT 24
Finished May 23 03:36:56 PM PDT 24
Peak memory 199232 kb
Host smart-0c2636c0-d3d8-4fe2-a5c7-a4cfbd6e4a17
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665610886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_w
akeup_race.1665610886
Directory /workspace/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.1618748039
Short name T25
Test name
Test status
Simulation time 78901893 ps
CPU time 0.76 seconds
Started May 23 03:36:52 PM PDT 24
Finished May 23 03:36:56 PM PDT 24
Peak memory 198552 kb
Host smart-bb9007c8-0102-4cdc-ab79-1a01694d659e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618748039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.1618748039
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.2801595849
Short name T329
Test name
Test status
Simulation time 127650617 ps
CPU time 0.81 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:01 PM PDT 24
Peak memory 208900 kb
Host smart-78314348-f4c0-48ab-90a9-e9afd30a6079
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801595849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.2801595849
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.302550749
Short name T587
Test name
Test status
Simulation time 246150047 ps
CPU time 1.5 seconds
Started May 23 03:36:52 PM PDT 24
Finished May 23 03:36:56 PM PDT 24
Peak memory 200500 kb
Host smart-7592a74f-8119-4563-9bbc-46fe6bfdc5ba
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302550749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_c
m_ctrl_config_regwen.302550749
Directory /workspace/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.116698118
Short name T401
Test name
Test status
Simulation time 728555202 ps
CPU time 3.15 seconds
Started May 23 03:36:51 PM PDT 24
Finished May 23 03:36:56 PM PDT 24
Peak memory 200612 kb
Host smart-629f29d5-3c29-4be7-bcfc-d581366ed362
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116698118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.116698118
Directory /workspace/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1990480568
Short name T949
Test name
Test status
Simulation time 853398705 ps
CPU time 3.38 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:02 PM PDT 24
Peak memory 200644 kb
Host smart-b6f73e44-e740-41df-9081-3f134988f717
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990480568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1990480568
Directory /workspace/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.2465211491
Short name T563
Test name
Test status
Simulation time 99717967 ps
CPU time 0.87 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:57 PM PDT 24
Peak memory 198784 kb
Host smart-14fa9183-1819-46e8-a4c5-2a10468a3ec3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465211491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2465211491
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.1251138312
Short name T865
Test name
Test status
Simulation time 39512723 ps
CPU time 0.69 seconds
Started May 23 03:36:51 PM PDT 24
Finished May 23 03:36:53 PM PDT 24
Peak memory 198784 kb
Host smart-faa0b96e-83f4-4d39-9059-aaac5373bec1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251138312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.1251138312
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all.2844445668
Short name T369
Test name
Test status
Simulation time 3361149537 ps
CPU time 1.98 seconds
Started May 23 03:36:52 PM PDT 24
Finished May 23 03:36:57 PM PDT 24
Peak memory 200736 kb
Host smart-8c1a6d2a-90ad-4e57-a372-095abbe42b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844445668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.2844445668
Directory /workspace/14.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all_with_rand_reset.620819263
Short name T84
Test name
Test status
Simulation time 7161224411 ps
CPU time 9.66 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:13 PM PDT 24
Peak memory 200872 kb
Host smart-0d6f46d0-3481-4994-9630-4e865c002a8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620819263 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all_with_rand_reset.620819263
Directory /workspace/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup.3111905834
Short name T860
Test name
Test status
Simulation time 209426738 ps
CPU time 0.82 seconds
Started May 23 03:36:52 PM PDT 24
Finished May 23 03:36:55 PM PDT 24
Peak memory 198068 kb
Host smart-7365f955-940d-4e28-8fe4-650157bfc31b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111905834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.3111905834
Directory /workspace/14.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup_reset.3474268617
Short name T716
Test name
Test status
Simulation time 158143756 ps
CPU time 1.06 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:36:59 PM PDT 24
Peak memory 199600 kb
Host smart-044da018-f880-4fa5-8569-160781012fc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474268617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.3474268617
Directory /workspace/14.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.789176563
Short name T615
Test name
Test status
Simulation time 28140227 ps
CPU time 0.84 seconds
Started May 23 03:36:52 PM PDT 24
Finished May 23 03:36:56 PM PDT 24
Peak memory 199516 kb
Host smart-c29fa1fc-a806-4b92-a1ca-1020940829e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789176563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.789176563
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.1647895053
Short name T958
Test name
Test status
Simulation time 61563743 ps
CPU time 0.87 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:58 PM PDT 24
Peak memory 198608 kb
Host smart-d4be57be-7578-4037-b911-0dcb56ca7507
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647895053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.1647895053
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.2085197424
Short name T680
Test name
Test status
Simulation time 40137920 ps
CPU time 0.59 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:36:58 PM PDT 24
Peak memory 197552 kb
Host smart-07080c55-716b-4845-9270-e79cfce31e41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085197424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.2085197424
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.4270371321
Short name T823
Test name
Test status
Simulation time 2478729287 ps
CPU time 1 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:00 PM PDT 24
Peak memory 197956 kb
Host smart-65c5bc59-19f2-4c70-a6ae-9dac60da4e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270371321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.4270371321
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.2540386959
Short name T410
Test name
Test status
Simulation time 24316383 ps
CPU time 0.64 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:05 PM PDT 24
Peak memory 197644 kb
Host smart-e76012b5-5d5d-4ca9-b6ec-f43e92b90696
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540386959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2540386959
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.1431028815
Short name T589
Test name
Test status
Simulation time 72675041 ps
CPU time 0.65 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:03 PM PDT 24
Peak memory 197888 kb
Host smart-61a8f430-75af-477f-bff1-b775469d2fb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431028815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.1431028815
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.3876482245
Short name T770
Test name
Test status
Simulation time 46554355 ps
CPU time 0.69 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:57 PM PDT 24
Peak memory 200620 kb
Host smart-3a9df7ff-454b-4fc7-9fc3-4f41871f20f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876482245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.3876482245
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.2863063647
Short name T41
Test name
Test status
Simulation time 266868240 ps
CPU time 1.04 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:36:59 PM PDT 24
Peak memory 199328 kb
Host smart-ed9e191c-46a5-4663-8885-5e3ae0dce420
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863063647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_w
akeup_race.2863063647
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.3055577111
Short name T388
Test name
Test status
Simulation time 33509175 ps
CPU time 0.74 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:04 PM PDT 24
Peak memory 198620 kb
Host smart-b3ad14b9-60cc-479e-aae2-0c13233df7ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055577111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3055577111
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.1032086440
Short name T503
Test name
Test status
Simulation time 319279364 ps
CPU time 0.8 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:01 PM PDT 24
Peak memory 208984 kb
Host smart-5b9850aa-c50e-43da-bc5b-19a6e0ae0e6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032086440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.1032086440
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.1370788919
Short name T586
Test name
Test status
Simulation time 103498134 ps
CPU time 0.93 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:04 PM PDT 24
Peak memory 199524 kb
Host smart-23cd96b6-c087-4880-9e01-57ef8ea21a16
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370788919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_
cm_ctrl_config_regwen.1370788919
Directory /workspace/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2239746792
Short name T296
Test name
Test status
Simulation time 1139163481 ps
CPU time 2.24 seconds
Started May 23 03:36:51 PM PDT 24
Finished May 23 03:36:55 PM PDT 24
Peak memory 200628 kb
Host smart-bab193a9-d591-4481-b112-e04dfa6a8408
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239746792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2239746792
Directory /workspace/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2383625443
Short name T186
Test name
Test status
Simulation time 810020349 ps
CPU time 3.09 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:06 PM PDT 24
Peak memory 200624 kb
Host smart-0d2976ee-bc82-4597-afce-de2788185dc2
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383625443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2383625443
Directory /workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2751234418
Short name T63
Test name
Test status
Simulation time 68573696 ps
CPU time 0.96 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:04 PM PDT 24
Peak memory 198932 kb
Host smart-ded2a5c4-dd79-450b-9669-57a72c222ae8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751234418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2751234418
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.4183054348
Short name T459
Test name
Test status
Simulation time 31125521 ps
CPU time 0.69 seconds
Started May 23 03:36:59 PM PDT 24
Finished May 23 03:37:07 PM PDT 24
Peak memory 198012 kb
Host smart-ad6fd17b-4fd8-498b-9936-b6aa647687de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183054348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.4183054348
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all.2437897275
Short name T620
Test name
Test status
Simulation time 1808381857 ps
CPU time 5.42 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:10 PM PDT 24
Peak memory 200696 kb
Host smart-4d19f1b2-9c42-4db9-af72-ad19f5c8814e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437897275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.2437897275
Directory /workspace/15.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all_with_rand_reset.2115509364
Short name T125
Test name
Test status
Simulation time 27150460125 ps
CPU time 24.4 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:26 PM PDT 24
Peak memory 200788 kb
Host smart-bc0c412e-34a4-4911-996f-b1dd9d3f643f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115509364 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all_with_rand_reset.2115509364
Directory /workspace/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup.749153797
Short name T338
Test name
Test status
Simulation time 397702892 ps
CPU time 0.91 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:58 PM PDT 24
Peak memory 199056 kb
Host smart-c4b99330-ee9e-406b-bdf1-6d4022e473ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749153797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.749153797
Directory /workspace/15.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup_reset.318181236
Short name T546
Test name
Test status
Simulation time 335993263 ps
CPU time 1.57 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:59 PM PDT 24
Peak memory 200660 kb
Host smart-715f5541-3112-4664-a335-a623046154e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318181236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.318181236
Directory /workspace/15.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.295236721
Short name T803
Test name
Test status
Simulation time 58512346 ps
CPU time 0.66 seconds
Started May 23 03:36:51 PM PDT 24
Finished May 23 03:36:53 PM PDT 24
Peak memory 198204 kb
Host smart-a8135987-9b80-4d95-bc84-18bd736c87ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295236721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.295236721
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.2426349683
Short name T732
Test name
Test status
Simulation time 54733184 ps
CPU time 0.81 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:01 PM PDT 24
Peak memory 198660 kb
Host smart-ddb3ad95-66b3-4197-9c39-a921f2b62acf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426349683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.2426349683
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.1643956710
Short name T737
Test name
Test status
Simulation time 29905907 ps
CPU time 0.65 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:01 PM PDT 24
Peak memory 197536 kb
Host smart-b3e2ddf6-33c5-4dd7-9471-8cca3e3c1c43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643956710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.1643956710
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.2825068234
Short name T482
Test name
Test status
Simulation time 609682246 ps
CPU time 0.98 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:00 PM PDT 24
Peak memory 197924 kb
Host smart-8e63b067-b117-4201-8c08-524434c34a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825068234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.2825068234
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.1341118619
Short name T902
Test name
Test status
Simulation time 64940746 ps
CPU time 0.61 seconds
Started May 23 03:36:57 PM PDT 24
Finished May 23 03:37:05 PM PDT 24
Peak memory 197636 kb
Host smart-3d5c0b5d-13fb-47ea-87c0-9f43b3ae3152
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341118619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.1341118619
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.2579744067
Short name T466
Test name
Test status
Simulation time 27508153 ps
CPU time 0.61 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:00 PM PDT 24
Peak memory 197592 kb
Host smart-ea58f410-f19a-42c2-a426-e100110a3513
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579744067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.2579744067
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.1710691047
Short name T750
Test name
Test status
Simulation time 154965610 ps
CPU time 0.73 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:03 PM PDT 24
Peak memory 200808 kb
Host smart-aa9bb1bd-fde6-4531-9cae-15d2399a6d1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710691047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.1710691047
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_wakeup_race.1210983028
Short name T693
Test name
Test status
Simulation time 291204844 ps
CPU time 1.31 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:05 PM PDT 24
Peak memory 199380 kb
Host smart-3f25301b-c425-4b7c-abff-60639b79a663
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210983028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_w
akeup_race.1210983028
Directory /workspace/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.1841243498
Short name T42
Test name
Test status
Simulation time 81440630 ps
CPU time 1.07 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:05 PM PDT 24
Peak memory 199392 kb
Host smart-dc6fd957-0844-43f9-96b1-417352e04030
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841243498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.1841243498
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.2495676474
Short name T437
Test name
Test status
Simulation time 111054669 ps
CPU time 1.1 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:00 PM PDT 24
Peak memory 208916 kb
Host smart-bde5e121-d3f9-469b-bb47-492bc51b683d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495676474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.2495676474
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.2854550237
Short name T713
Test name
Test status
Simulation time 189112013 ps
CPU time 0.79 seconds
Started May 23 03:36:57 PM PDT 24
Finished May 23 03:37:05 PM PDT 24
Peak memory 198284 kb
Host smart-3492fee2-51f4-445f-93d3-0c19ca638fcc
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854550237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_
cm_ctrl_config_regwen.2854550237
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2540032808
Short name T936
Test name
Test status
Simulation time 880038533 ps
CPU time 3.18 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:08 PM PDT 24
Peak memory 200588 kb
Host smart-dbd51c6b-3eef-453b-b22d-18d6843b9975
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540032808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2540032808
Directory /workspace/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2681115022
Short name T879
Test name
Test status
Simulation time 809278534 ps
CPU time 3.58 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:05 PM PDT 24
Peak memory 200592 kb
Host smart-dc569985-12a8-41c2-8b48-1669381707df
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681115022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2681115022
Directory /workspace/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2760396816
Short name T757
Test name
Test status
Simulation time 64097229 ps
CPU time 0.92 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:04 PM PDT 24
Peak memory 198952 kb
Host smart-4c63e2bc-c87e-45a5-ba11-397dd27b5417
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760396816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2760396816
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.2631304647
Short name T187
Test name
Test status
Simulation time 26397130 ps
CPU time 0.72 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:02 PM PDT 24
Peak memory 198848 kb
Host smart-ff62a9f7-d020-41b2-b3b8-125951ba941d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631304647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.2631304647
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all.2073600793
Short name T769
Test name
Test status
Simulation time 2511991041 ps
CPU time 4.36 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:37:01 PM PDT 24
Peak memory 200696 kb
Host smart-280c4824-1585-4110-88ed-f01ffd8f560e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073600793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.2073600793
Directory /workspace/16.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all_with_rand_reset.2466327290
Short name T574
Test name
Test status
Simulation time 9422468249 ps
CPU time 22.94 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 200884 kb
Host smart-a7958e4e-267b-47b6-b09c-fa2ada06f5fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466327290 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all_with_rand_reset.2466327290
Directory /workspace/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup.1050854822
Short name T436
Test name
Test status
Simulation time 490021944 ps
CPU time 0.98 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:04 PM PDT 24
Peak memory 199172 kb
Host smart-6629ff68-90c4-4e4d-bb15-b885ee15eb03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050854822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.1050854822
Directory /workspace/16.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup_reset.4209066610
Short name T836
Test name
Test status
Simulation time 609210584 ps
CPU time 0.92 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:04 PM PDT 24
Peak memory 199680 kb
Host smart-ee6dd239-e699-4dd7-b520-5812cc879fc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209066610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.4209066610
Directory /workspace/16.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.1707985540
Short name T232
Test name
Test status
Simulation time 75418723 ps
CPU time 0.72 seconds
Started May 23 03:36:51 PM PDT 24
Finished May 23 03:36:54 PM PDT 24
Peak memory 198212 kb
Host smart-dcad7f89-83e1-45ee-b261-a8fe0b69e910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707985540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.1707985540
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.3095997482
Short name T164
Test name
Test status
Simulation time 49856360 ps
CPU time 0.87 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:59 PM PDT 24
Peak memory 198696 kb
Host smart-4b8239a7-ff1e-4989-a0da-b925f975628f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095997482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.3095997482
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.1103224030
Short name T648
Test name
Test status
Simulation time 31633067 ps
CPU time 0.61 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:01 PM PDT 24
Peak memory 197512 kb
Host smart-20cac847-ce4f-4ba2-8bf1-d11e1b9a9033
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103224030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.1103224030
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.3684911121
Short name T645
Test name
Test status
Simulation time 346034478 ps
CPU time 0.93 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:03 PM PDT 24
Peak memory 197484 kb
Host smart-bd589d71-2f93-441b-9f77-7fccea8cb1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684911121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.3684911121
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.3194854443
Short name T512
Test name
Test status
Simulation time 83073445 ps
CPU time 0.61 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:03 PM PDT 24
Peak memory 197292 kb
Host smart-41612105-b421-4ac3-906a-a2eff52c8b99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194854443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.3194854443
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.2370251439
Short name T206
Test name
Test status
Simulation time 36464875 ps
CPU time 0.62 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:05 PM PDT 24
Peak memory 197964 kb
Host smart-31e9f858-50ac-491b-9e93-3e0d9f39e6cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370251439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.2370251439
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.1636738455
Short name T276
Test name
Test status
Simulation time 57262199 ps
CPU time 0.68 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:36:59 PM PDT 24
Peak memory 200804 kb
Host smart-6ee7db2b-48b4-40d3-8bf3-117cabbe3f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636738455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.1636738455
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.2120429394
Short name T510
Test name
Test status
Simulation time 137800623 ps
CPU time 0.75 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:00 PM PDT 24
Peak memory 197860 kb
Host smart-7f83c106-aa18-48cc-9ee5-ecfb438a34ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120429394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_w
akeup_race.2120429394
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.3599131400
Short name T966
Test name
Test status
Simulation time 32378182 ps
CPU time 0.65 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:05 PM PDT 24
Peak memory 198564 kb
Host smart-e21b33c0-e178-496b-9fd3-8159339140a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599131400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.3599131400
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.1664390179
Short name T40
Test name
Test status
Simulation time 119271202 ps
CPU time 0.85 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:03 PM PDT 24
Peak memory 208848 kb
Host smart-1de25738-09de-4206-a0cd-fc19c3a7839b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664390179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.1664390179
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.723282325
Short name T216
Test name
Test status
Simulation time 264096715 ps
CPU time 0.92 seconds
Started May 23 03:36:53 PM PDT 24
Finished May 23 03:36:57 PM PDT 24
Peak memory 199632 kb
Host smart-8cdea886-fb3e-4a9f-a31f-f0465c7489a6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723282325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_c
m_ctrl_config_regwen.723282325
Directory /workspace/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3373829052
Short name T679
Test name
Test status
Simulation time 1499365702 ps
CPU time 2.17 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:05 PM PDT 24
Peak memory 200724 kb
Host smart-ce65c375-7545-4277-a818-d253a387e13c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373829052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3373829052
Directory /workspace/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3492136357
Short name T247
Test name
Test status
Simulation time 874366138 ps
CPU time 3.33 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:04 PM PDT 24
Peak memory 200572 kb
Host smart-2a62d82c-987f-4ba0-8153-ec181b1b2ab0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492136357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3492136357
Directory /workspace/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.3020974270
Short name T691
Test name
Test status
Simulation time 111831378 ps
CPU time 0.95 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:02 PM PDT 24
Peak memory 198644 kb
Host smart-7cd47184-a97d-4ab7-8e23-f14e43780069
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020974270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3020974270
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.2398100954
Short name T178
Test name
Test status
Simulation time 36865229 ps
CPU time 0.64 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:04 PM PDT 24
Peak memory 198876 kb
Host smart-d58bcd80-522c-4f68-8c72-e6cc676e94fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398100954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.2398100954
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all.866734811
Short name T784
Test name
Test status
Simulation time 43381696 ps
CPU time 0.72 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:00 PM PDT 24
Peak memory 198836 kb
Host smart-c1cf44e4-e8e8-4a47-a410-819ba28dc9dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866734811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.866734811
Directory /workspace/17.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all_with_rand_reset.3899696976
Short name T597
Test name
Test status
Simulation time 5451169489 ps
CPU time 9.48 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:08 PM PDT 24
Peak memory 200928 kb
Host smart-2671b67e-0f9d-492c-be42-ef4ff8d775bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899696976 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all_with_rand_reset.3899696976
Directory /workspace/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup.202812274
Short name T411
Test name
Test status
Simulation time 256880229 ps
CPU time 1.2 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:03 PM PDT 24
Peak memory 199208 kb
Host smart-4d7c92d2-59ba-4320-976f-18b2f784bb05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202812274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.202812274
Directory /workspace/17.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup_reset.3277688868
Short name T255
Test name
Test status
Simulation time 475529720 ps
CPU time 1.15 seconds
Started May 23 03:36:54 PM PDT 24
Finished May 23 03:37:00 PM PDT 24
Peak memory 200488 kb
Host smart-4ff8c8de-44ca-46ea-bb31-610bb6cbf08d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277688868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.3277688868
Directory /workspace/17.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.4222802914
Short name T699
Test name
Test status
Simulation time 259348826 ps
CPU time 0.71 seconds
Started May 23 03:37:06 PM PDT 24
Finished May 23 03:37:12 PM PDT 24
Peak memory 198236 kb
Host smart-bc82ec39-2427-45f1-9fe6-45a8c41e9799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222802914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.4222802914
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.3496727899
Short name T815
Test name
Test status
Simulation time 64140037 ps
CPU time 0.83 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:14 PM PDT 24
Peak memory 198628 kb
Host smart-5759f3e5-35f6-4b41-bb19-8469b618f5eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496727899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.3496727899
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.685689218
Short name T782
Test name
Test status
Simulation time 37464594 ps
CPU time 0.64 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:14 PM PDT 24
Peak memory 197572 kb
Host smart-e75e0f65-5091-4f41-ac03-874b4a4ef952
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685689218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_
malfunc.685689218
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.674523522
Short name T854
Test name
Test status
Simulation time 158357705 ps
CPU time 0.99 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:14 PM PDT 24
Peak memory 197672 kb
Host smart-5aca95ec-7f31-4289-8035-75557fbf2597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674523522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.674523522
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.2937725215
Short name T300
Test name
Test status
Simulation time 68798544 ps
CPU time 0.63 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:13 PM PDT 24
Peak memory 196936 kb
Host smart-a0961168-c701-4d12-b712-8d94b8dbd55a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937725215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.2937725215
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.455061697
Short name T2
Test name
Test status
Simulation time 25635335 ps
CPU time 0.61 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:14 PM PDT 24
Peak memory 197576 kb
Host smart-c40752ce-b9da-4838-bf9b-2f25a83f4a3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455061697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.455061697
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.1754226634
Short name T368
Test name
Test status
Simulation time 76799085 ps
CPU time 0.67 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:13 PM PDT 24
Peak memory 200880 kb
Host smart-197f5f60-9544-4d01-b661-f43470c18347
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754226634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.1754226634
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.4024508954
Short name T894
Test name
Test status
Simulation time 251303322 ps
CPU time 0.88 seconds
Started May 23 03:36:55 PM PDT 24
Finished May 23 03:37:03 PM PDT 24
Peak memory 198672 kb
Host smart-ef7fe230-3edc-458e-bb06-249411412eca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024508954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_w
akeup_race.4024508954
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.4207846135
Short name T813
Test name
Test status
Simulation time 40398468 ps
CPU time 0.66 seconds
Started May 23 03:36:56 PM PDT 24
Finished May 23 03:37:03 PM PDT 24
Peak memory 197972 kb
Host smart-e671d7ef-93c3-4ff9-be1f-e3dd804cc139
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207846135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.4207846135
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.424562762
Short name T779
Test name
Test status
Simulation time 169169335 ps
CPU time 0.77 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:14 PM PDT 24
Peak memory 208908 kb
Host smart-ec437d5c-b9c4-472a-98cb-9939c20aeb0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424562762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.424562762
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.4191850923
Short name T655
Test name
Test status
Simulation time 206231841 ps
CPU time 1.11 seconds
Started May 23 03:37:04 PM PDT 24
Finished May 23 03:37:11 PM PDT 24
Peak memory 199496 kb
Host smart-5116be0f-813f-44f1-a358-2728ef000d12
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191850923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_
cm_ctrl_config_regwen.4191850923
Directory /workspace/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2458916356
Short name T591
Test name
Test status
Simulation time 987845829 ps
CPU time 2.09 seconds
Started May 23 03:37:05 PM PDT 24
Finished May 23 03:37:12 PM PDT 24
Peak memory 200612 kb
Host smart-f7021bb5-1eb8-4f8d-ad13-f5cfee081abd
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458916356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2458916356
Directory /workspace/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4129653606
Short name T201
Test name
Test status
Simulation time 861592458 ps
CPU time 3.33 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:15 PM PDT 24
Peak memory 200652 kb
Host smart-a5e26179-c3ab-469a-8f16-52e781878789
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129653606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4129653606
Directory /workspace/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.2898962293
Short name T926
Test name
Test status
Simulation time 175367064 ps
CPU time 0.87 seconds
Started May 23 03:37:05 PM PDT 24
Finished May 23 03:37:11 PM PDT 24
Peak memory 198788 kb
Host smart-0e3eae53-e31a-4f6f-b569-4ccbd0366083
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898962293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2898962293
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.2923843119
Short name T207
Test name
Test status
Simulation time 30969426 ps
CPU time 0.66 seconds
Started May 23 03:36:51 PM PDT 24
Finished May 23 03:36:53 PM PDT 24
Peak memory 198848 kb
Host smart-5866c5e8-bc1b-4251-bffa-e7f16a0b58ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923843119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.2923843119
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all.3892603436
Short name T534
Test name
Test status
Simulation time 1746640105 ps
CPU time 2.74 seconds
Started May 23 03:37:05 PM PDT 24
Finished May 23 03:37:13 PM PDT 24
Peak memory 200624 kb
Host smart-26656f6d-2976-407a-b7a9-33552ab61cc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892603436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.3892603436
Directory /workspace/18.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all_with_rand_reset.3361880125
Short name T123
Test name
Test status
Simulation time 9340256703 ps
CPU time 28.36 seconds
Started May 23 03:37:04 PM PDT 24
Finished May 23 03:37:38 PM PDT 24
Peak memory 200832 kb
Host smart-384a3752-e5b9-4fc1-b036-a9e489c47be8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361880125 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all_with_rand_reset.3361880125
Directory /workspace/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.2209841606
Short name T224
Test name
Test status
Simulation time 92398787 ps
CPU time 0.91 seconds
Started May 23 03:37:05 PM PDT 24
Finished May 23 03:37:11 PM PDT 24
Peak memory 198160 kb
Host smart-2c70b0b3-5c0b-4541-8b4d-9add5906185e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209841606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.2209841606
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup_reset.1433851790
Short name T508
Test name
Test status
Simulation time 272935354 ps
CPU time 1.01 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:14 PM PDT 24
Peak memory 199760 kb
Host smart-4b9a9066-a47a-4ed2-b593-41e6967899bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433851790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.1433851790
Directory /workspace/18.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.3587857338
Short name T545
Test name
Test status
Simulation time 70050350 ps
CPU time 0.7 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:13 PM PDT 24
Peak memory 198692 kb
Host smart-02ed80df-1ad8-465d-a68c-f8cebdf05a5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587857338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.3587857338
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.2316941392
Short name T995
Test name
Test status
Simulation time 43714973 ps
CPU time 0.59 seconds
Started May 23 03:37:06 PM PDT 24
Finished May 23 03:37:12 PM PDT 24
Peak memory 197552 kb
Host smart-1ac0300b-d14c-4121-8f06-4083d815e3bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316941392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.2316941392
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.574279662
Short name T370
Test name
Test status
Simulation time 628217539 ps
CPU time 0.92 seconds
Started May 23 03:37:11 PM PDT 24
Finished May 23 03:37:20 PM PDT 24
Peak memory 197660 kb
Host smart-9a9b0642-e049-4f4d-950c-064f415e4862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574279662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.574279662
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.2000489908
Short name T963
Test name
Test status
Simulation time 34484076 ps
CPU time 0.66 seconds
Started May 23 03:37:05 PM PDT 24
Finished May 23 03:37:11 PM PDT 24
Peak memory 196872 kb
Host smart-162c5b26-8943-4733-962f-b6591d974729
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000489908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.2000489908
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.4255069297
Short name T581
Test name
Test status
Simulation time 55364598 ps
CPU time 0.63 seconds
Started May 23 03:37:06 PM PDT 24
Finished May 23 03:37:12 PM PDT 24
Peak memory 197604 kb
Host smart-120cf04d-f6cf-47e9-a2e8-a966e5619972
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255069297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.4255069297
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.2358648171
Short name T626
Test name
Test status
Simulation time 97447791 ps
CPU time 0.7 seconds
Started May 23 03:37:09 PM PDT 24
Finished May 23 03:37:17 PM PDT 24
Peak memory 200848 kb
Host smart-95d6f6c5-a8c6-4f41-accd-fb74e1c938e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358648171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.2358648171
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.865017327
Short name T637
Test name
Test status
Simulation time 162942764 ps
CPU time 0.71 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:14 PM PDT 24
Peak memory 198036 kb
Host smart-fbfc8ca1-6477-4848-8a0d-e96362dc7b74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865017327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wa
keup_race.865017327
Directory /workspace/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.1984710700
Short name T357
Test name
Test status
Simulation time 156323405 ps
CPU time 0.84 seconds
Started May 23 03:37:06 PM PDT 24
Finished May 23 03:37:12 PM PDT 24
Peak memory 199340 kb
Host smart-3f373976-e856-4eaa-86ea-9f086ab67494
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984710700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.1984710700
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.1495144135
Short name T360
Test name
Test status
Simulation time 121946925 ps
CPU time 0.85 seconds
Started May 23 03:37:09 PM PDT 24
Finished May 23 03:37:17 PM PDT 24
Peak memory 208992 kb
Host smart-ee073b09-d0fb-4967-8066-e71e7dff41ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495144135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.1495144135
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.724880669
Short name T946
Test name
Test status
Simulation time 279293727 ps
CPU time 0.94 seconds
Started May 23 03:37:10 PM PDT 24
Finished May 23 03:37:19 PM PDT 24
Peak memory 200376 kb
Host smart-95b4ebd8-438f-49b4-9782-a8ac8432ee7f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724880669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_c
m_ctrl_config_regwen.724880669
Directory /workspace/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3582699045
Short name T880
Test name
Test status
Simulation time 769512899 ps
CPU time 3.24 seconds
Started May 23 03:37:09 PM PDT 24
Finished May 23 03:37:19 PM PDT 24
Peak memory 200664 kb
Host smart-ade60b3e-095a-4eea-8bb4-d03aabfa53d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582699045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3582699045
Directory /workspace/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3388336435
Short name T660
Test name
Test status
Simulation time 1043327682 ps
CPU time 2.16 seconds
Started May 23 03:37:16 PM PDT 24
Finished May 23 03:37:25 PM PDT 24
Peak memory 200572 kb
Host smart-a4ec8a92-69e3-46e3-b8c2-4f490419c87a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388336435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3388336435
Directory /workspace/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2714358133
Short name T246
Test name
Test status
Simulation time 138647314 ps
CPU time 0.84 seconds
Started May 23 03:37:11 PM PDT 24
Finished May 23 03:37:20 PM PDT 24
Peak memory 198828 kb
Host smart-d20c0800-52f4-49bf-bda6-46431bd23d09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714358133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2714358133
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.3487854610
Short name T700
Test name
Test status
Simulation time 122378023 ps
CPU time 0.62 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:15 PM PDT 24
Peak memory 198008 kb
Host smart-abfce81e-07a2-4480-8af0-0dc157e43857
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487854610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.3487854610
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all.3578128373
Short name T180
Test name
Test status
Simulation time 269428204 ps
CPU time 0.94 seconds
Started May 23 03:37:09 PM PDT 24
Finished May 23 03:37:17 PM PDT 24
Peak memory 200064 kb
Host smart-639c1bef-f3b5-41a4-ae4f-5c312291a4e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578128373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.3578128373
Directory /workspace/19.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all_with_rand_reset.868717371
Short name T969
Test name
Test status
Simulation time 12323210766 ps
CPU time 22.09 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:34 PM PDT 24
Peak memory 200872 kb
Host smart-e7f28820-1738-4aa5-8cf6-47c62be45e7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868717371 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all_with_rand_reset.868717371
Directory /workspace/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup.1491612728
Short name T515
Test name
Test status
Simulation time 433796407 ps
CPU time 1.02 seconds
Started May 23 03:37:06 PM PDT 24
Finished May 23 03:37:12 PM PDT 24
Peak memory 199396 kb
Host smart-caeac884-22eb-4fa3-a929-db1655313584
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491612728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.1491612728
Directory /workspace/19.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup_reset.4048013890
Short name T979
Test name
Test status
Simulation time 252580943 ps
CPU time 1.25 seconds
Started May 23 03:37:11 PM PDT 24
Finished May 23 03:37:19 PM PDT 24
Peak memory 199680 kb
Host smart-56afc415-3023-4df4-90c0-4e101df2c5ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048013890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.4048013890
Directory /workspace/19.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.2729578581
Short name T349
Test name
Test status
Simulation time 23122467 ps
CPU time 0.79 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 199648 kb
Host smart-35539760-b0b6-4e39-a194-10261a1a3dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729578581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.2729578581
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.1918981274
Short name T165
Test name
Test status
Simulation time 58920026 ps
CPU time 0.76 seconds
Started May 23 03:36:13 PM PDT 24
Finished May 23 03:36:20 PM PDT 24
Peak memory 197996 kb
Host smart-2d50b4e0-cd13-4155-8804-eeaa4a0ab50d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918981274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.1918981274
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.194397051
Short name T701
Test name
Test status
Simulation time 32047603 ps
CPU time 0.59 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 197528 kb
Host smart-df106e22-be76-409e-9369-ba106490b0d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194397051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_m
alfunc.194397051
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.2237421117
Short name T566
Test name
Test status
Simulation time 160360651 ps
CPU time 0.96 seconds
Started May 23 03:36:12 PM PDT 24
Finished May 23 03:36:20 PM PDT 24
Peak memory 197616 kb
Host smart-41532a7e-50ef-4860-8ccb-509203b73d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237421117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2237421117
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.3053623916
Short name T438
Test name
Test status
Simulation time 67262363 ps
CPU time 0.63 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 196900 kb
Host smart-6dfc4e6d-a5eb-4ce9-be77-b3e08d67100e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053623916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.3053623916
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.1762830964
Short name T869
Test name
Test status
Simulation time 87238221 ps
CPU time 0.6 seconds
Started May 23 03:36:09 PM PDT 24
Finished May 23 03:36:15 PM PDT 24
Peak memory 197616 kb
Host smart-0080c0fe-48d1-408d-b3d2-0d91dabb4e89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762830964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1762830964
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.1337836120
Short name T846
Test name
Test status
Simulation time 43898521 ps
CPU time 0.7 seconds
Started May 23 03:36:11 PM PDT 24
Finished May 23 03:36:19 PM PDT 24
Peak memory 200812 kb
Host smart-cb8bd963-0f68-4a43-995b-5b7e45066cd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337836120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.1337836120
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.2648170259
Short name T363
Test name
Test status
Simulation time 266288740 ps
CPU time 0.99 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 199052 kb
Host smart-18797998-57ff-49ec-b220-6d2b39bd39d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648170259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wa
keup_race.2648170259
Directory /workspace/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.86560808
Short name T943
Test name
Test status
Simulation time 100194144 ps
CPU time 0.83 seconds
Started May 23 03:36:18 PM PDT 24
Finished May 23 03:36:25 PM PDT 24
Peak memory 199180 kb
Host smart-9c3c7f60-4719-408c-9475-f488847c1490
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86560808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.86560808
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.2534915382
Short name T901
Test name
Test status
Simulation time 95204942 ps
CPU time 0.88 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:17 PM PDT 24
Peak memory 208956 kb
Host smart-406f338d-886f-4337-8f35-f6f057c953d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534915382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.2534915382
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1976418073
Short name T17
Test name
Test status
Simulation time 697767163 ps
CPU time 1.07 seconds
Started May 23 03:36:12 PM PDT 24
Finished May 23 03:36:19 PM PDT 24
Peak memory 216352 kb
Host smart-7c4a44c6-e9a3-4f47-a4aa-72fd6ac83683
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976418073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1976418073
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.3148023135
Short name T616
Test name
Test status
Simulation time 240735032 ps
CPU time 1 seconds
Started May 23 03:36:09 PM PDT 24
Finished May 23 03:36:14 PM PDT 24
Peak memory 199552 kb
Host smart-ec8e91f2-4e77-4920-b69a-eb90a28036d8
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148023135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_c
m_ctrl_config_regwen.3148023135
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3721242740
Short name T908
Test name
Test status
Simulation time 860317750 ps
CPU time 2.26 seconds
Started May 23 03:36:11 PM PDT 24
Finished May 23 03:36:20 PM PDT 24
Peak memory 200564 kb
Host smart-16bfe1ae-1e1e-4eb1-a11e-0eb09dcad92b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721242740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3721242740
Directory /workspace/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.203854178
Short name T478
Test name
Test status
Simulation time 857669071 ps
CPU time 3.3 seconds
Started May 23 03:36:08 PM PDT 24
Finished May 23 03:36:14 PM PDT 24
Peak memory 200680 kb
Host smart-f8f3ceab-022f-4d5c-85f9-8bfa1bbf2e9b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203854178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.203854178
Directory /workspace/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2911513105
Short name T229
Test name
Test status
Simulation time 77193688 ps
CPU time 0.89 seconds
Started May 23 03:36:14 PM PDT 24
Finished May 23 03:36:22 PM PDT 24
Peak memory 199104 kb
Host smart-3ef3817e-ea2b-425d-8753-5b9d7d178e23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911513105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2911513105
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.1335119801
Short name T852
Test name
Test status
Simulation time 29613161 ps
CPU time 0.69 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:30 PM PDT 24
Peak memory 198876 kb
Host smart-87e6ccf9-1a3d-47e2-a8b4-0178f3317f4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335119801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.1335119801
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all.2297057326
Short name T666
Test name
Test status
Simulation time 886624545 ps
CPU time 1.61 seconds
Started May 23 03:36:11 PM PDT 24
Finished May 23 03:36:19 PM PDT 24
Peak memory 200716 kb
Host smart-873f97c7-dd66-48f3-8b72-cbadb4fe79f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297057326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.2297057326
Directory /workspace/2.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all_with_rand_reset.2181450050
Short name T266
Test name
Test status
Simulation time 12212472264 ps
CPU time 17.75 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:34 PM PDT 24
Peak memory 200964 kb
Host smart-340dc721-b7d3-4942-81e2-ba32290c190e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181450050 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all_with_rand_reset.2181450050
Directory /workspace/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup.2674399888
Short name T193
Test name
Test status
Simulation time 126910590 ps
CPU time 0.77 seconds
Started May 23 03:36:09 PM PDT 24
Finished May 23 03:36:14 PM PDT 24
Peak memory 197832 kb
Host smart-b91ed929-9f27-4db7-ab5c-13c6b1d065ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674399888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.2674399888
Directory /workspace/2.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup_reset.3872830717
Short name T283
Test name
Test status
Simulation time 105814092 ps
CPU time 0.87 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 198888 kb
Host smart-05015003-d3d7-40c3-9535-0e823afb6efb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872830717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.3872830717
Directory /workspace/2.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.3105920623
Short name T756
Test name
Test status
Simulation time 60735157 ps
CPU time 0.81 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:15 PM PDT 24
Peak memory 199492 kb
Host smart-bfd33965-2cf1-4190-9f0e-19245db4de04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105920623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.3105920623
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.1241116652
Short name T204
Test name
Test status
Simulation time 84361950 ps
CPU time 0.7 seconds
Started May 23 03:37:06 PM PDT 24
Finished May 23 03:37:12 PM PDT 24
Peak memory 198640 kb
Host smart-de765383-0976-45e0-b196-c5a3f4c098b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241116652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.1241116652
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.2591382829
Short name T245
Test name
Test status
Simulation time 39109382 ps
CPU time 0.6 seconds
Started May 23 03:37:09 PM PDT 24
Finished May 23 03:37:17 PM PDT 24
Peak memory 197560 kb
Host smart-75b2fec3-5040-49a7-a9d2-05315d240470
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591382829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.2591382829
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.1584621612
Short name T726
Test name
Test status
Simulation time 629646035 ps
CPU time 0.98 seconds
Started May 23 03:37:11 PM PDT 24
Finished May 23 03:37:20 PM PDT 24
Peak memory 197652 kb
Host smart-c5d7d911-cfde-4d90-84c6-659c3778b2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584621612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.1584621612
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.2046647998
Short name T733
Test name
Test status
Simulation time 31236336 ps
CPU time 0.61 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:14 PM PDT 24
Peak memory 196924 kb
Host smart-6278207b-d36b-4fb9-8750-e1f484b4166d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046647998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.2046647998
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.438163210
Short name T417
Test name
Test status
Simulation time 32091441 ps
CPU time 0.62 seconds
Started May 23 03:37:11 PM PDT 24
Finished May 23 03:37:19 PM PDT 24
Peak memory 197500 kb
Host smart-084b56ca-3e6a-4d62-ad45-75c15229d3ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438163210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.438163210
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.4075639755
Short name T48
Test name
Test status
Simulation time 76595675 ps
CPU time 0.67 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:13 PM PDT 24
Peak memory 200772 kb
Host smart-e136bbfe-ba73-496d-8434-91a6699d84c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075639755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.4075639755
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.4150474954
Short name T605
Test name
Test status
Simulation time 227897742 ps
CPU time 1.28 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:13 PM PDT 24
Peak memory 199160 kb
Host smart-8c0bede1-2d4f-45ce-8ffb-9d9ca6c72a02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150474954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_w
akeup_race.4150474954
Directory /workspace/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.3557593538
Short name T405
Test name
Test status
Simulation time 51702033 ps
CPU time 0.87 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:14 PM PDT 24
Peak memory 198588 kb
Host smart-b07cc4f5-4bc7-4ede-b13f-257930db6865
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557593538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.3557593538
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.952823100
Short name T915
Test name
Test status
Simulation time 106549087 ps
CPU time 0.95 seconds
Started May 23 03:37:05 PM PDT 24
Finished May 23 03:37:11 PM PDT 24
Peak memory 208972 kb
Host smart-7dad73e8-482d-49a6-b981-4f89c74f6cfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952823100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.952823100
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.1549402933
Short name T871
Test name
Test status
Simulation time 246018826 ps
CPU time 1.19 seconds
Started May 23 03:37:09 PM PDT 24
Finished May 23 03:37:17 PM PDT 24
Peak memory 199640 kb
Host smart-65f1eb72-1c76-41b9-8ee7-3f296ebaa9ac
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549402933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_
cm_ctrl_config_regwen.1549402933
Directory /workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.905826764
Short name T889
Test name
Test status
Simulation time 1190394244 ps
CPU time 2.1 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:16 PM PDT 24
Peak memory 200548 kb
Host smart-3ed0bf3f-7bee-4d5b-9a8b-e9357efb3a17
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905826764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.905826764
Directory /workspace/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3866687560
Short name T320
Test name
Test status
Simulation time 859490208 ps
CPU time 3.05 seconds
Started May 23 03:37:06 PM PDT 24
Finished May 23 03:37:14 PM PDT 24
Peak memory 200656 kb
Host smart-8fad6501-ce10-4967-83b3-d78aff063f64
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866687560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3866687560
Directory /workspace/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.3742191931
Short name T812
Test name
Test status
Simulation time 79240905 ps
CPU time 0.93 seconds
Started May 23 03:37:06 PM PDT 24
Finished May 23 03:37:12 PM PDT 24
Peak memory 198920 kb
Host smart-18d8cb30-1204-4c95-b46b-b16161f90842
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742191931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3742191931
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.1539524074
Short name T707
Test name
Test status
Simulation time 45662190 ps
CPU time 0.64 seconds
Started May 23 03:37:05 PM PDT 24
Finished May 23 03:37:11 PM PDT 24
Peak memory 198852 kb
Host smart-facc9d1a-dea7-496e-b985-bc647cc5df77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539524074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.1539524074
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all.2965884776
Short name T953
Test name
Test status
Simulation time 1244492649 ps
CPU time 2.18 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:15 PM PDT 24
Peak memory 200680 kb
Host smart-650815d4-d4ab-4cef-a469-e65c8276cf8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965884776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.2965884776
Directory /workspace/20.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all_with_rand_reset.2270721065
Short name T118
Test name
Test status
Simulation time 8603435206 ps
CPU time 12.61 seconds
Started May 23 03:37:10 PM PDT 24
Finished May 23 03:37:29 PM PDT 24
Peak memory 200916 kb
Host smart-0ac522dd-9c10-4b9a-9042-b94e8c260a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270721065 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all_with_rand_reset.2270721065
Directory /workspace/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup.2796923764
Short name T863
Test name
Test status
Simulation time 129066119 ps
CPU time 0.62 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:15 PM PDT 24
Peak memory 197788 kb
Host smart-8f7d8804-f494-462a-a946-2dc2231e18ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796923764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.2796923764
Directory /workspace/20.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup_reset.1369204560
Short name T311
Test name
Test status
Simulation time 453269574 ps
CPU time 1.23 seconds
Started May 23 03:37:09 PM PDT 24
Finished May 23 03:37:17 PM PDT 24
Peak memory 200460 kb
Host smart-958a8d22-3f89-4a61-a95f-c6765c0f898c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369204560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.1369204560
Directory /workspace/20.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.156901525
Short name T940
Test name
Test status
Simulation time 73307596 ps
CPU time 0.8 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:15 PM PDT 24
Peak memory 198472 kb
Host smart-5fc938d8-bdfe-498b-b270-7b21c22a8d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156901525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.156901525
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.4249536146
Short name T475
Test name
Test status
Simulation time 77898576 ps
CPU time 0.69 seconds
Started May 23 03:37:15 PM PDT 24
Finished May 23 03:37:22 PM PDT 24
Peak memory 198616 kb
Host smart-1cbacf63-f0d2-454a-9445-37224f75c917
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249536146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.4249536146
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2337309065
Short name T285
Test name
Test status
Simulation time 30436585 ps
CPU time 0.63 seconds
Started May 23 03:37:17 PM PDT 24
Finished May 23 03:37:23 PM PDT 24
Peak memory 196784 kb
Host smart-c6bf7bb2-02f2-4175-af9f-893f1a191b2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337309065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.2337309065
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.1710259476
Short name T364
Test name
Test status
Simulation time 606494660 ps
CPU time 0.93 seconds
Started May 23 03:37:16 PM PDT 24
Finished May 23 03:37:24 PM PDT 24
Peak memory 197900 kb
Host smart-3234450f-90a4-449a-89a4-c2ec7f74f2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710259476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1710259476
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.2909379167
Short name T999
Test name
Test status
Simulation time 131599084 ps
CPU time 0.65 seconds
Started May 23 03:37:09 PM PDT 24
Finished May 23 03:37:16 PM PDT 24
Peak memory 197580 kb
Host smart-a2b0ac49-4e1f-48c5-b144-c2733cc0ad0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909379167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.2909379167
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.2931478555
Short name T575
Test name
Test status
Simulation time 30668730 ps
CPU time 0.61 seconds
Started May 23 03:37:15 PM PDT 24
Finished May 23 03:37:22 PM PDT 24
Peak memory 197592 kb
Host smart-0f64e5a7-167a-4ef7-9522-dd922402d395
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931478555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.2931478555
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.585956712
Short name T820
Test name
Test status
Simulation time 82783775 ps
CPU time 0.66 seconds
Started May 23 03:37:16 PM PDT 24
Finished May 23 03:37:23 PM PDT 24
Peak memory 200820 kb
Host smart-e46ec29f-ddea-4d4a-a1f1-b829b34eaa92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585956712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invali
d.585956712
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.827384948
Short name T455
Test name
Test status
Simulation time 216170194 ps
CPU time 0.83 seconds
Started May 23 03:37:09 PM PDT 24
Finished May 23 03:37:17 PM PDT 24
Peak memory 198060 kb
Host smart-bff9afe0-c9e0-450d-b89e-bd45c530b450
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827384948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_wa
keup_race.827384948
Directory /workspace/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.3789781325
Short name T321
Test name
Test status
Simulation time 74125151 ps
CPU time 0.95 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:16 PM PDT 24
Peak memory 199216 kb
Host smart-9cbcfd09-9ec0-4043-a080-55f7d28ca5f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789781325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.3789781325
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.900715930
Short name T794
Test name
Test status
Simulation time 313065882 ps
CPU time 0.74 seconds
Started May 23 03:37:14 PM PDT 24
Finished May 23 03:37:21 PM PDT 24
Peak memory 208904 kb
Host smart-2d77d9fe-e6b4-4fe9-9a8c-588e7e9281d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900715930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.900715930
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.2289678447
Short name T470
Test name
Test status
Simulation time 178742595 ps
CPU time 0.92 seconds
Started May 23 03:37:15 PM PDT 24
Finished May 23 03:37:22 PM PDT 24
Peak memory 199440 kb
Host smart-49f966b9-742a-40a1-96ff-5654944fc52f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289678447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_
cm_ctrl_config_regwen.2289678447
Directory /workspace/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3105250207
Short name T578
Test name
Test status
Simulation time 1166023929 ps
CPU time 2.38 seconds
Started May 23 03:37:16 PM PDT 24
Finished May 23 03:37:25 PM PDT 24
Peak memory 200576 kb
Host smart-da714108-da00-44b0-8cc6-148e21c60a6d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105250207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3105250207
Directory /workspace/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1898872849
Short name T906
Test name
Test status
Simulation time 937176838 ps
CPU time 3.25 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:16 PM PDT 24
Peak memory 200616 kb
Host smart-7f421f5e-356d-4753-8d19-f32a1addb59d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898872849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1898872849
Directory /workspace/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.2084139750
Short name T825
Test name
Test status
Simulation time 85034442 ps
CPU time 0.92 seconds
Started May 23 03:37:16 PM PDT 24
Finished May 23 03:37:24 PM PDT 24
Peak memory 198856 kb
Host smart-063f9ced-6e57-438a-9ed2-921ce57efa06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084139750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2084139750
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.2162447877
Short name T200
Test name
Test status
Simulation time 29903370 ps
CPU time 0.66 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:13 PM PDT 24
Peak memory 198836 kb
Host smart-71aa9d16-bdf2-472f-a569-9c7e1fa5b289
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162447877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.2162447877
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all.3523272482
Short name T429
Test name
Test status
Simulation time 2094107178 ps
CPU time 5.83 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:20 PM PDT 24
Peak memory 200512 kb
Host smart-0a4ba02e-f988-4093-9b0c-8196170691ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523272482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.3523272482
Directory /workspace/21.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all_with_rand_reset.1305386210
Short name T88
Test name
Test status
Simulation time 6913108786 ps
CPU time 12.01 seconds
Started May 23 03:37:17 PM PDT 24
Finished May 23 03:37:35 PM PDT 24
Peak memory 200828 kb
Host smart-b9f36a09-0090-4972-a336-1d01daa09109
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305386210 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all_with_rand_reset.1305386210
Directory /workspace/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup.4068547856
Short name T773
Test name
Test status
Simulation time 256937871 ps
CPU time 1.28 seconds
Started May 23 03:37:10 PM PDT 24
Finished May 23 03:37:18 PM PDT 24
Peak memory 200360 kb
Host smart-04233d78-4667-47fb-ac05-140e29a6cfdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068547856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.4068547856
Directory /workspace/21.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup_reset.2804626824
Short name T448
Test name
Test status
Simulation time 505155755 ps
CPU time 1.19 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:16 PM PDT 24
Peak memory 200528 kb
Host smart-2b8b42a3-691c-498f-87bc-3cc019d92d1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804626824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.2804626824
Directory /workspace/21.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.3800060012
Short name T561
Test name
Test status
Simulation time 36186105 ps
CPU time 0.67 seconds
Started May 23 03:37:11 PM PDT 24
Finished May 23 03:37:19 PM PDT 24
Peak memory 198112 kb
Host smart-d859b222-b70b-4648-b62a-eaaa4caaf846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800060012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.3800060012
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.1656034469
Short name T980
Test name
Test status
Simulation time 31317298 ps
CPU time 0.61 seconds
Started May 23 03:37:11 PM PDT 24
Finished May 23 03:37:19 PM PDT 24
Peak memory 197552 kb
Host smart-bc8472ae-e227-4772-9be4-56af32284760
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656034469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.1656034469
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.3901683726
Short name T462
Test name
Test status
Simulation time 330931943 ps
CPU time 0.93 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:13 PM PDT 24
Peak memory 197844 kb
Host smart-f3b3ad01-ca4e-4d80-9d61-9074627adfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901683726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.3901683726
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.3754107138
Short name T577
Test name
Test status
Simulation time 63317832 ps
CPU time 0.65 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:15 PM PDT 24
Peak memory 196780 kb
Host smart-ac7d726e-cc59-4cce-acef-bcecd8391029
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754107138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.3754107138
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.4034308179
Short name T822
Test name
Test status
Simulation time 31552315 ps
CPU time 0.63 seconds
Started May 23 03:37:07 PM PDT 24
Finished May 23 03:37:13 PM PDT 24
Peak memory 197516 kb
Host smart-d9727956-4e5e-4534-9cd2-ddbd265dbef5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034308179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.4034308179
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.2059016726
Short name T199
Test name
Test status
Simulation time 78767159 ps
CPU time 0.68 seconds
Started May 23 03:37:11 PM PDT 24
Finished May 23 03:37:19 PM PDT 24
Peak memory 200868 kb
Host smart-311367c6-f9df-4d9d-b5cb-025aead198b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059016726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.2059016726
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_wakeup_race.2623872117
Short name T343
Test name
Test status
Simulation time 280685957 ps
CPU time 0.9 seconds
Started May 23 03:37:14 PM PDT 24
Finished May 23 03:37:22 PM PDT 24
Peak memory 199244 kb
Host smart-ecaefdb8-0925-46a3-ac4b-7691c39a954d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623872117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_w
akeup_race.2623872117
Directory /workspace/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.863569251
Short name T553
Test name
Test status
Simulation time 150035820 ps
CPU time 0.82 seconds
Started May 23 03:37:13 PM PDT 24
Finished May 23 03:37:21 PM PDT 24
Peak memory 199484 kb
Host smart-2358ad21-9f47-44b2-b8e8-b86444fc6709
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863569251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.863569251
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.4168131644
Short name T984
Test name
Test status
Simulation time 160690868 ps
CPU time 0.85 seconds
Started May 23 03:37:14 PM PDT 24
Finished May 23 03:37:22 PM PDT 24
Peak memory 208972 kb
Host smart-11e2949e-81e0-4ab6-b727-3878866423b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168131644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.4168131644
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.1135830682
Short name T225
Test name
Test status
Simulation time 437657192 ps
CPU time 1.04 seconds
Started May 23 03:37:15 PM PDT 24
Finished May 23 03:37:23 PM PDT 24
Peak memory 200352 kb
Host smart-a3927b3d-38d4-42e5-9fa9-75b50b2b4f16
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135830682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_
cm_ctrl_config_regwen.1135830682
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3512829033
Short name T592
Test name
Test status
Simulation time 725605812 ps
CPU time 3 seconds
Started May 23 03:37:10 PM PDT 24
Finished May 23 03:37:20 PM PDT 24
Peak memory 200580 kb
Host smart-b38b403b-5011-4660-8a16-3ab2d613c1e0
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512829033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3512829033
Directory /workspace/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1798223784
Short name T441
Test name
Test status
Simulation time 1274072265 ps
CPU time 2.22 seconds
Started May 23 03:37:11 PM PDT 24
Finished May 23 03:37:20 PM PDT 24
Peak memory 200616 kb
Host smart-d6134c38-aba2-4abe-a55b-808ce0790bf6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798223784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1798223784
Directory /workspace/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.87572650
Short name T845
Test name
Test status
Simulation time 87147241 ps
CPU time 0.83 seconds
Started May 23 03:37:14 PM PDT 24
Finished May 23 03:37:21 PM PDT 24
Peak memory 198736 kb
Host smart-fc156605-21c2-4952-8fa3-74e3f421d917
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87572650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.87572650
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.3752766989
Short name T379
Test name
Test status
Simulation time 53025548 ps
CPU time 0.68 seconds
Started May 23 03:37:09 PM PDT 24
Finished May 23 03:37:16 PM PDT 24
Peak memory 198876 kb
Host smart-6ff507ee-d7d7-431f-9299-7ba395e382d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752766989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.3752766989
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all.1056897239
Short name T747
Test name
Test status
Simulation time 1130980558 ps
CPU time 4.51 seconds
Started May 23 03:37:14 PM PDT 24
Finished May 23 03:37:25 PM PDT 24
Peak memory 200660 kb
Host smart-1bbf4fbd-c4d8-4f49-a10c-7e645d873ae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056897239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.1056897239
Directory /workspace/22.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all_with_rand_reset.620835622
Short name T87
Test name
Test status
Simulation time 4022943930 ps
CPU time 5.87 seconds
Started May 23 03:37:10 PM PDT 24
Finished May 23 03:37:22 PM PDT 24
Peak memory 200864 kb
Host smart-d087b9d2-e643-4680-8ae1-bbcb82779f0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620835622 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all_with_rand_reset.620835622
Directory /workspace/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup.1902902280
Short name T931
Test name
Test status
Simulation time 436507320 ps
CPU time 0.98 seconds
Started May 23 03:37:08 PM PDT 24
Finished May 23 03:37:15 PM PDT 24
Peak memory 199248 kb
Host smart-f7c81c13-5cef-4a3f-a954-7458782e6bff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902902280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.1902902280
Directory /workspace/22.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup_reset.1489870210
Short name T447
Test name
Test status
Simulation time 503015829 ps
CPU time 1.13 seconds
Started May 23 03:37:11 PM PDT 24
Finished May 23 03:37:19 PM PDT 24
Peak memory 200568 kb
Host smart-d76a3c66-e1bf-47d1-82c8-4319802884ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489870210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.1489870210
Directory /workspace/22.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.3499068242
Short name T273
Test name
Test status
Simulation time 171465801 ps
CPU time 0.83 seconds
Started May 23 03:37:30 PM PDT 24
Finished May 23 03:37:36 PM PDT 24
Peak memory 199528 kb
Host smart-a3e21e08-8797-48fb-bb1d-2c92a9e26a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499068242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.3499068242
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.2718584313
Short name T166
Test name
Test status
Simulation time 68510258 ps
CPU time 0.7 seconds
Started May 23 03:37:20 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 198636 kb
Host smart-3f6d2433-d60c-4ce6-8185-1e92713286da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718584313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.2718584313
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.3968366676
Short name T752
Test name
Test status
Simulation time 38777926 ps
CPU time 0.58 seconds
Started May 23 03:37:16 PM PDT 24
Finished May 23 03:37:22 PM PDT 24
Peak memory 197628 kb
Host smart-e1e3a083-68a7-471c-8a04-2685e0ad35bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968366676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.3968366676
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.2540842810
Short name T551
Test name
Test status
Simulation time 165825053 ps
CPU time 1.01 seconds
Started May 23 03:37:22 PM PDT 24
Finished May 23 03:37:29 PM PDT 24
Peak memory 197920 kb
Host smart-4d569a29-61b2-4322-818f-776f5b330967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540842810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.2540842810
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.1630201182
Short name T242
Test name
Test status
Simulation time 47890856 ps
CPU time 0.65 seconds
Started May 23 03:37:19 PM PDT 24
Finished May 23 03:37:26 PM PDT 24
Peak memory 197664 kb
Host smart-6b35c5df-62cf-412d-83ef-654b39b4bf21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630201182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.1630201182
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.895651246
Short name T977
Test name
Test status
Simulation time 24329973 ps
CPU time 0.62 seconds
Started May 23 03:37:25 PM PDT 24
Finished May 23 03:37:33 PM PDT 24
Peak memory 197612 kb
Host smart-e925fedd-8cdb-484a-9340-163d7b423893
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895651246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.895651246
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.3747565243
Short name T656
Test name
Test status
Simulation time 45140324 ps
CPU time 0.7 seconds
Started May 23 03:37:20 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 200852 kb
Host smart-4b72566e-bc5f-4968-b334-0bc7f9015391
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747565243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.3747565243
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.3118918380
Short name T80
Test name
Test status
Simulation time 159102125 ps
CPU time 0.96 seconds
Started May 23 03:37:11 PM PDT 24
Finished May 23 03:37:19 PM PDT 24
Peak memory 198000 kb
Host smart-cf63ca75-ce6f-4c45-b8e2-66d7db9b533d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118918380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_w
akeup_race.3118918380
Directory /workspace/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.974048122
Short name T791
Test name
Test status
Simulation time 33513189 ps
CPU time 0.78 seconds
Started May 23 03:37:10 PM PDT 24
Finished May 23 03:37:18 PM PDT 24
Peak memory 198620 kb
Host smart-49b7ef57-3e77-4074-9e09-2862459d3c19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974048122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.974048122
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.2840728391
Short name T228
Test name
Test status
Simulation time 158459371 ps
CPU time 0.8 seconds
Started May 23 03:37:21 PM PDT 24
Finished May 23 03:37:28 PM PDT 24
Peak memory 208924 kb
Host smart-8ce32423-f029-4074-999e-296ce114126f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840728391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.2840728391
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.4259094925
Short name T844
Test name
Test status
Simulation time 439779325 ps
CPU time 1.21 seconds
Started May 23 03:37:19 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 200456 kb
Host smart-2a785ae1-e97f-4cc0-a481-e4b6514d63a2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259094925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_
cm_ctrl_config_regwen.4259094925
Directory /workspace/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.353011822
Short name T849
Test name
Test status
Simulation time 781616932 ps
CPU time 2.31 seconds
Started May 23 03:37:16 PM PDT 24
Finished May 23 03:37:24 PM PDT 24
Peak memory 200600 kb
Host smart-b71aa763-05b3-4e5e-aab2-964137f93134
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353011822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.353011822
Directory /workspace/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4273558215
Short name T785
Test name
Test status
Simulation time 1053101632 ps
CPU time 2.24 seconds
Started May 23 03:37:26 PM PDT 24
Finished May 23 03:37:36 PM PDT 24
Peak memory 200648 kb
Host smart-a1e8f8a5-9b0c-4faf-a241-2304511ed5c4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273558215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4273558215
Directory /workspace/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.621094406
Short name T604
Test name
Test status
Simulation time 149969434 ps
CPU time 0.93 seconds
Started May 23 03:37:20 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 198800 kb
Host smart-145f6eae-6079-44c9-afd3-cb8e953876ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621094406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_
mubi.621094406
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.4259470826
Short name T45
Test name
Test status
Simulation time 40139553 ps
CPU time 0.66 seconds
Started May 23 03:37:15 PM PDT 24
Finished May 23 03:37:22 PM PDT 24
Peak memory 198844 kb
Host smart-70836c12-3064-40ca-bf47-eca64db3dde6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259470826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.4259470826
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all.519697766
Short name T91
Test name
Test status
Simulation time 2636574784 ps
CPU time 3.63 seconds
Started May 23 03:37:19 PM PDT 24
Finished May 23 03:37:28 PM PDT 24
Peak memory 200788 kb
Host smart-7bd0e09e-dae4-4271-80bc-e634b8897add
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519697766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.519697766
Directory /workspace/23.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all_with_rand_reset.40778742
Short name T129
Test name
Test status
Simulation time 9031750933 ps
CPU time 17.53 seconds
Started May 23 03:37:18 PM PDT 24
Finished May 23 03:37:41 PM PDT 24
Peak memory 200920 kb
Host smart-9a2ceecd-7a8e-41bd-af19-7d01ba55d0ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40778742 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all_with_rand_reset.40778742
Directory /workspace/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.4014824086
Short name T821
Test name
Test status
Simulation time 211181017 ps
CPU time 0.75 seconds
Started May 23 03:37:14 PM PDT 24
Finished May 23 03:37:21 PM PDT 24
Peak memory 197828 kb
Host smart-8391e874-a960-4096-9d81-5d199326612d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014824086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.4014824086
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup_reset.2057813312
Short name T367
Test name
Test status
Simulation time 72393002 ps
CPU time 0.75 seconds
Started May 23 03:37:11 PM PDT 24
Finished May 23 03:37:19 PM PDT 24
Peak memory 198632 kb
Host smart-7cbfdbbf-bef5-4f38-9def-33b273c301b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057813312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.2057813312
Directory /workspace/23.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.4012367074
Short name T431
Test name
Test status
Simulation time 81890910 ps
CPU time 0.76 seconds
Started May 23 03:37:18 PM PDT 24
Finished May 23 03:37:25 PM PDT 24
Peak memory 198348 kb
Host smart-1a75bc1b-67da-428f-81d3-cb82d28206f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012367074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.4012367074
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.242033115
Short name T774
Test name
Test status
Simulation time 89432892 ps
CPU time 0.73 seconds
Started May 23 03:37:17 PM PDT 24
Finished May 23 03:37:24 PM PDT 24
Peak memory 198696 kb
Host smart-f65f41d7-95f6-4abe-a111-b2165e502ff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242033115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disa
ble_rom_integrity_check.242033115
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.1344995828
Short name T319
Test name
Test status
Simulation time 30932299 ps
CPU time 0.62 seconds
Started May 23 03:37:24 PM PDT 24
Finished May 23 03:37:32 PM PDT 24
Peak memory 196800 kb
Host smart-9cd091c5-48ec-44f5-88ff-4db5fd705f5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344995828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.1344995828
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.2412678807
Short name T135
Test name
Test status
Simulation time 157897533 ps
CPU time 0.96 seconds
Started May 23 03:37:20 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 197644 kb
Host smart-cbb13096-cdbf-4b0a-b876-da668d14e425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412678807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.2412678807
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.2521811519
Short name T842
Test name
Test status
Simulation time 42598280 ps
CPU time 0.69 seconds
Started May 23 03:37:18 PM PDT 24
Finished May 23 03:37:25 PM PDT 24
Peak memory 196936 kb
Host smart-90855f05-4a2e-43cc-8c2c-9f99146e1b69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521811519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.2521811519
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.453539010
Short name T973
Test name
Test status
Simulation time 35263619 ps
CPU time 0.61 seconds
Started May 23 03:37:20 PM PDT 24
Finished May 23 03:37:26 PM PDT 24
Peak memory 197620 kb
Host smart-d21473f0-6a2e-4b7f-bc59-867e5ea37c9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453539010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.453539010
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.2881459175
Short name T670
Test name
Test status
Simulation time 38116912 ps
CPU time 0.78 seconds
Started May 23 03:37:29 PM PDT 24
Finished May 23 03:37:35 PM PDT 24
Peak memory 200708 kb
Host smart-680cefea-af2e-4e22-89d1-84736674d072
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881459175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.2881459175
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_wakeup_race.1031036057
Short name T176
Test name
Test status
Simulation time 303901843 ps
CPU time 0.96 seconds
Started May 23 03:37:23 PM PDT 24
Finished May 23 03:37:31 PM PDT 24
Peak memory 199112 kb
Host smart-fd008c1a-bcf3-4a60-9d95-4ba374a72216
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031036057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_w
akeup_race.1031036057
Directory /workspace/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.4205478693
Short name T215
Test name
Test status
Simulation time 33796660 ps
CPU time 0.62 seconds
Started May 23 03:37:16 PM PDT 24
Finished May 23 03:37:22 PM PDT 24
Peak memory 197796 kb
Host smart-b3ff358c-3251-41ea-acc8-ec14911d4287
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205478693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.4205478693
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.1236832559
Short name T721
Test name
Test status
Simulation time 165891077 ps
CPU time 0.85 seconds
Started May 23 03:37:22 PM PDT 24
Finished May 23 03:37:29 PM PDT 24
Peak memory 208936 kb
Host smart-ef6c3077-e8c6-44e3-854d-1ba0b5e2f4b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236832559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.1236832559
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.183009099
Short name T3
Test name
Test status
Simulation time 251205691 ps
CPU time 1.01 seconds
Started May 23 03:37:22 PM PDT 24
Finished May 23 03:37:29 PM PDT 24
Peak memory 200364 kb
Host smart-5d8eec7f-51fe-49cf-adbd-edc2194bd517
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183009099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_c
m_ctrl_config_regwen.183009099
Directory /workspace/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.421506853
Short name T1001
Test name
Test status
Simulation time 1105015401 ps
CPU time 2.17 seconds
Started May 23 03:37:30 PM PDT 24
Finished May 23 03:37:37 PM PDT 24
Peak memory 200476 kb
Host smart-a8f78bb1-2e5c-4145-8a61-8b7a114a05a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421506853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.421506853
Directory /workspace/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.636822232
Short name T257
Test name
Test status
Simulation time 3117593991 ps
CPU time 1.97 seconds
Started May 23 03:37:22 PM PDT 24
Finished May 23 03:37:30 PM PDT 24
Peak memory 200668 kb
Host smart-437ee387-ca9a-4a79-8f41-c0a991bf3efd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636822232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.636822232
Directory /workspace/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.3508342305
Short name T443
Test name
Test status
Simulation time 333783541 ps
CPU time 0.86 seconds
Started May 23 03:37:22 PM PDT 24
Finished May 23 03:37:29 PM PDT 24
Peak memory 198784 kb
Host smart-30d22204-57e2-40e2-9b13-b0df0c20a5d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508342305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3508342305
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.277932546
Short name T593
Test name
Test status
Simulation time 102149929 ps
CPU time 0.63 seconds
Started May 23 03:37:26 PM PDT 24
Finished May 23 03:37:34 PM PDT 24
Peak memory 198040 kb
Host smart-a47be724-46ec-4c61-a561-85bd61ae51aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277932546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.277932546
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all.450250968
Short name T37
Test name
Test status
Simulation time 880398001 ps
CPU time 3.36 seconds
Started May 23 03:37:17 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 200668 kb
Host smart-bfbc0224-cb3b-4c5c-a1b5-ee6872e55300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450250968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.450250968
Directory /workspace/24.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all_with_rand_reset.1386021327
Short name T493
Test name
Test status
Simulation time 7054871160 ps
CPU time 16.88 seconds
Started May 23 03:37:21 PM PDT 24
Finished May 23 03:37:45 PM PDT 24
Peak memory 200916 kb
Host smart-c3f8196a-7438-4aad-a16e-49b0d9ced288
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386021327 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all_with_rand_reset.1386021327
Directory /workspace/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup.1301461660
Short name T998
Test name
Test status
Simulation time 72397064 ps
CPU time 0.66 seconds
Started May 23 03:37:25 PM PDT 24
Finished May 23 03:37:33 PM PDT 24
Peak memory 197808 kb
Host smart-df45a04b-16a0-4a4a-8239-fd9a0006db1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301461660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.1301461660
Directory /workspace/24.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup_reset.541224414
Short name T422
Test name
Test status
Simulation time 330338043 ps
CPU time 1.39 seconds
Started May 23 03:37:19 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 200492 kb
Host smart-539f06aa-dd92-4d15-b36d-9983c62cda53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541224414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.541224414
Directory /workspace/24.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.3799961464
Short name T114
Test name
Test status
Simulation time 148316497 ps
CPU time 0.74 seconds
Started May 23 03:37:18 PM PDT 24
Finished May 23 03:37:25 PM PDT 24
Peak memory 199260 kb
Host smart-892ae804-7f00-4848-88eb-d231207fcca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799961464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3799961464
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.2402262083
Short name T985
Test name
Test status
Simulation time 69513682 ps
CPU time 0.67 seconds
Started May 23 03:37:20 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 197836 kb
Host smart-129bac0e-b5e9-4f7c-b885-c927c4290d12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402262083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.2402262083
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.105952654
Short name T288
Test name
Test status
Simulation time 35324297 ps
CPU time 0.63 seconds
Started May 23 03:37:20 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 197556 kb
Host smart-fc5814ea-353b-4ca5-b057-5b08edd59334
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105952654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_
malfunc.105952654
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.1462150082
Short name T886
Test name
Test status
Simulation time 159460295 ps
CPU time 1.05 seconds
Started May 23 03:37:21 PM PDT 24
Finished May 23 03:37:29 PM PDT 24
Peak memory 197992 kb
Host smart-ed82b8c0-7853-4977-bfe3-6d3795f30130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462150082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.1462150082
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.650806305
Short name T528
Test name
Test status
Simulation time 34767566 ps
CPU time 0.61 seconds
Started May 23 03:37:19 PM PDT 24
Finished May 23 03:37:26 PM PDT 24
Peak memory 197560 kb
Host smart-15ea812d-89df-48ca-9fd6-25f60901dee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650806305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.650806305
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.1173879491
Short name T479
Test name
Test status
Simulation time 68049518 ps
CPU time 0.62 seconds
Started May 23 03:37:20 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 197648 kb
Host smart-c05cb6b8-967d-4bdb-b5a5-05e8d277314e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173879491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.1173879491
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.4144476089
Short name T425
Test name
Test status
Simulation time 71108866 ps
CPU time 0.65 seconds
Started May 23 03:37:22 PM PDT 24
Finished May 23 03:37:29 PM PDT 24
Peak memory 200840 kb
Host smart-801a09e6-5219-47a3-9c0a-5928b54c7c23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144476089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.4144476089
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.417458077
Short name T490
Test name
Test status
Simulation time 230244787 ps
CPU time 0.94 seconds
Started May 23 03:37:18 PM PDT 24
Finished May 23 03:37:25 PM PDT 24
Peak memory 199140 kb
Host smart-0208b378-effa-46bd-9927-585444eda97b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417458077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wa
keup_race.417458077
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.2382444994
Short name T876
Test name
Test status
Simulation time 92278860 ps
CPU time 1.04 seconds
Started May 23 03:37:18 PM PDT 24
Finished May 23 03:37:26 PM PDT 24
Peak memory 199548 kb
Host smart-6dcf7734-d9f3-4b33-a80e-b3094ae55150
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382444994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.2382444994
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.579950059
Short name T601
Test name
Test status
Simulation time 300376261 ps
CPU time 0.78 seconds
Started May 23 03:37:20 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 209008 kb
Host smart-e831a717-a82f-4739-8398-d0aadebb6731
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579950059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.579950059
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.62532508
Short name T939
Test name
Test status
Simulation time 179165202 ps
CPU time 1.12 seconds
Started May 23 03:37:21 PM PDT 24
Finished May 23 03:37:29 PM PDT 24
Peak memory 199384 kb
Host smart-71471355-a9c2-4a66-8e1e-81e1d1836a34
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62532508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm
_ctrl_config_regwen.62532508
Directory /workspace/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1071135066
Short name T965
Test name
Test status
Simulation time 1287589501 ps
CPU time 2.11 seconds
Started May 23 03:37:19 PM PDT 24
Finished May 23 03:37:28 PM PDT 24
Peak memory 200648 kb
Host smart-4361f78a-e5a9-4977-80f8-46fa8043e1be
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071135066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1071135066
Directory /workspace/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2032584295
Short name T485
Test name
Test status
Simulation time 930191931 ps
CPU time 2.44 seconds
Started May 23 03:37:31 PM PDT 24
Finished May 23 03:37:38 PM PDT 24
Peak memory 200524 kb
Host smart-6c4f04d5-e41f-4ffc-9ec4-4d569c3ab2d2
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032584295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2032584295
Directory /workspace/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2935570972
Short name T532
Test name
Test status
Simulation time 74680413 ps
CPU time 0.96 seconds
Started May 23 03:37:20 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 198600 kb
Host smart-e5dcd142-7b7f-4f8b-9d57-2563a220dcfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935570972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2935570972
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.2644081614
Short name T356
Test name
Test status
Simulation time 86096042 ps
CPU time 0.62 seconds
Started May 23 03:37:20 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 198856 kb
Host smart-8c6cf984-cd85-496d-85a1-803ef631c555
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644081614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.2644081614
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all.324871921
Short name T509
Test name
Test status
Simulation time 779284517 ps
CPU time 1.65 seconds
Started May 23 03:37:25 PM PDT 24
Finished May 23 03:37:34 PM PDT 24
Peak memory 200480 kb
Host smart-f12144eb-7e0d-45af-bd90-cbecb7a26fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324871921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.324871921
Directory /workspace/25.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all_with_rand_reset.3211712040
Short name T866
Test name
Test status
Simulation time 9889168212 ps
CPU time 7.07 seconds
Started May 23 03:37:30 PM PDT 24
Finished May 23 03:37:42 PM PDT 24
Peak memory 200804 kb
Host smart-9a294bc8-2f81-477f-b6c7-49235b4d4e24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211712040 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all_with_rand_reset.3211712040
Directory /workspace/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup.1535694775
Short name T818
Test name
Test status
Simulation time 184405408 ps
CPU time 1.13 seconds
Started May 23 03:37:17 PM PDT 24
Finished May 23 03:37:24 PM PDT 24
Peak memory 199124 kb
Host smart-dc5b5676-5ac7-4589-8013-9913eccd97d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535694775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.1535694775
Directory /workspace/25.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup_reset.281093628
Short name T239
Test name
Test status
Simulation time 200502017 ps
CPU time 1.2 seconds
Started May 23 03:37:18 PM PDT 24
Finished May 23 03:37:25 PM PDT 24
Peak memory 199656 kb
Host smart-a47c220e-1454-4efe-b3ab-a287b790235e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281093628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.281093628
Directory /workspace/25.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.3504381946
Short name T550
Test name
Test status
Simulation time 22688918 ps
CPU time 0.68 seconds
Started May 23 03:37:23 PM PDT 24
Finished May 23 03:37:31 PM PDT 24
Peak memory 198168 kb
Host smart-2f43303d-e35b-40c6-bb4b-69a0b8611c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504381946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.3504381946
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.3167653862
Short name T858
Test name
Test status
Simulation time 57699480 ps
CPU time 0.86 seconds
Started May 23 03:37:29 PM PDT 24
Finished May 23 03:37:36 PM PDT 24
Peak memory 198596 kb
Host smart-c02c2258-c7bf-4974-b0d8-731d37f71bca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167653862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.3167653862
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.3274688219
Short name T500
Test name
Test status
Simulation time 31946907 ps
CPU time 0.6 seconds
Started May 23 03:37:18 PM PDT 24
Finished May 23 03:37:25 PM PDT 24
Peak memory 197492 kb
Host smart-94063e55-4a50-4a11-bbaa-a72c2905bd84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274688219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.3274688219
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.1489975729
Short name T533
Test name
Test status
Simulation time 165429522 ps
CPU time 1 seconds
Started May 23 03:37:23 PM PDT 24
Finished May 23 03:37:31 PM PDT 24
Peak memory 197932 kb
Host smart-5c493924-c806-46cb-88a2-0bab07fcbcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489975729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.1489975729
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.3567018587
Short name T712
Test name
Test status
Simulation time 42635932 ps
CPU time 0.73 seconds
Started May 23 03:37:29 PM PDT 24
Finished May 23 03:37:35 PM PDT 24
Peak memory 197544 kb
Host smart-f99f7109-1dec-4f8d-aefd-da00741ff907
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567018587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.3567018587
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.2651098330
Short name T986
Test name
Test status
Simulation time 92866986 ps
CPU time 0.61 seconds
Started May 23 03:37:22 PM PDT 24
Finished May 23 03:37:29 PM PDT 24
Peak memory 197628 kb
Host smart-e9a21f88-c76c-4464-91ff-486a35acf18e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651098330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.2651098330
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.2887900309
Short name T668
Test name
Test status
Simulation time 71908434 ps
CPU time 0.69 seconds
Started May 23 03:37:31 PM PDT 24
Finished May 23 03:37:36 PM PDT 24
Peak memory 200812 kb
Host smart-b1176511-17f1-468a-a832-fb00a6d086d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887900309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.2887900309
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_wakeup_race.4271678054
Short name T44
Test name
Test status
Simulation time 80139327 ps
CPU time 0.75 seconds
Started May 23 03:37:20 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 197864 kb
Host smart-f05485a7-8c30-48df-928f-853444235825
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271678054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_w
akeup_race.4271678054
Directory /workspace/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.462961796
Short name T39
Test name
Test status
Simulation time 96011972 ps
CPU time 0.86 seconds
Started May 23 03:37:21 PM PDT 24
Finished May 23 03:37:28 PM PDT 24
Peak memory 198620 kb
Host smart-b48ac22f-eef0-40f1-993e-3e30ec05a76c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462961796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.462961796
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.905576765
Short name T378
Test name
Test status
Simulation time 157974044 ps
CPU time 0.82 seconds
Started May 23 03:37:23 PM PDT 24
Finished May 23 03:37:30 PM PDT 24
Peak memory 209004 kb
Host smart-89f34455-51ee-41c7-9dba-2cb9dc1ac518
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905576765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.905576765
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.3682039444
Short name T377
Test name
Test status
Simulation time 238905190 ps
CPU time 1.24 seconds
Started May 23 03:37:31 PM PDT 24
Finished May 23 03:37:37 PM PDT 24
Peak memory 200332 kb
Host smart-1110b759-ec17-4450-9b4e-3b1cd1e642d5
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682039444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_
cm_ctrl_config_regwen.3682039444
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1726812703
Short name T588
Test name
Test status
Simulation time 854761620 ps
CPU time 3.44 seconds
Started May 23 03:37:21 PM PDT 24
Finished May 23 03:37:31 PM PDT 24
Peak memory 200660 kb
Host smart-cb5d661c-9dfd-4e3a-acff-f0efac0068ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726812703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1726812703
Directory /workspace/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.8611516
Short name T269
Test name
Test status
Simulation time 1089754889 ps
CPU time 2.61 seconds
Started May 23 03:37:23 PM PDT 24
Finished May 23 03:37:33 PM PDT 24
Peak memory 200612 kb
Host smart-a11c91fe-5090-4488-ac1c-ff023917041f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8611516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +
UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.8611516
Directory /workspace/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.600589435
Short name T1000
Test name
Test status
Simulation time 146167570 ps
CPU time 0.84 seconds
Started May 23 03:37:22 PM PDT 24
Finished May 23 03:37:29 PM PDT 24
Peak memory 198916 kb
Host smart-33ca989a-f318-4c1e-8400-e1edfc0d7db8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600589435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_
mubi.600589435
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.1927842588
Short name T400
Test name
Test status
Simulation time 51861975 ps
CPU time 0.62 seconds
Started May 23 03:37:24 PM PDT 24
Finished May 23 03:37:32 PM PDT 24
Peak memory 197976 kb
Host smart-f21b5192-ddce-4218-a88f-c6833ebe4602
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927842588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1927842588
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all.2995287093
Short name T93
Test name
Test status
Simulation time 845570638 ps
CPU time 3.89 seconds
Started May 23 03:37:28 PM PDT 24
Finished May 23 03:37:38 PM PDT 24
Peak memory 200664 kb
Host smart-1ff73697-02a2-46e1-9ec4-5c4f4b4469cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995287093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.2995287093
Directory /workspace/26.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all_with_rand_reset.3271279821
Short name T127
Test name
Test status
Simulation time 17568539539 ps
CPU time 24.32 seconds
Started May 23 03:37:24 PM PDT 24
Finished May 23 03:37:55 PM PDT 24
Peak memory 200836 kb
Host smart-38eb5b12-1c49-472e-b013-0cb3baed652d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271279821 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all_with_rand_reset.3271279821
Directory /workspace/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup.1210932057
Short name T188
Test name
Test status
Simulation time 304394779 ps
CPU time 0.69 seconds
Started May 23 03:37:19 PM PDT 24
Finished May 23 03:37:25 PM PDT 24
Peak memory 197828 kb
Host smart-0438adff-a0c8-4988-b286-1edaa931b676
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210932057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.1210932057
Directory /workspace/26.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup_reset.1048836819
Short name T263
Test name
Test status
Simulation time 257640383 ps
CPU time 1.5 seconds
Started May 23 03:37:29 PM PDT 24
Finished May 23 03:37:36 PM PDT 24
Peak memory 200452 kb
Host smart-b008b05c-6794-4773-b51f-0da109ae1906
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048836819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.1048836819
Directory /workspace/26.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.734696630
Short name T900
Test name
Test status
Simulation time 91037553 ps
CPU time 0.78 seconds
Started May 23 03:37:24 PM PDT 24
Finished May 23 03:37:32 PM PDT 24
Peak memory 199548 kb
Host smart-2fb791d2-493c-4d6f-b5a3-ad4c5aca786b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734696630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.734696630
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.279897399
Short name T167
Test name
Test status
Simulation time 72228255 ps
CPU time 0.77 seconds
Started May 23 03:37:26 PM PDT 24
Finished May 23 03:37:34 PM PDT 24
Peak memory 198632 kb
Host smart-c5c9e1ab-6286-4b12-9a9d-e7490bb4e858
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279897399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disa
ble_rom_integrity_check.279897399
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1091667575
Short name T531
Test name
Test status
Simulation time 36657426 ps
CPU time 0.57 seconds
Started May 23 03:37:24 PM PDT 24
Finished May 23 03:37:32 PM PDT 24
Peak memory 197488 kb
Host smart-f3ff8696-a259-47b0-852d-b74e9af0d30f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091667575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.1091667575
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.1420298767
Short name T929
Test name
Test status
Simulation time 568188465 ps
CPU time 0.92 seconds
Started May 23 03:37:26 PM PDT 24
Finished May 23 03:37:34 PM PDT 24
Peak memory 197640 kb
Host smart-636e3fb6-b510-41ea-885e-7eeba09d3f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420298767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.1420298767
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.518659380
Short name T724
Test name
Test status
Simulation time 60411251 ps
CPU time 0.66 seconds
Started May 23 03:37:13 PM PDT 24
Finished May 23 03:37:21 PM PDT 24
Peak memory 197616 kb
Host smart-99492cbc-87d7-4009-8197-beea50b26df6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518659380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.518659380
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.3261886778
Short name T786
Test name
Test status
Simulation time 120477581 ps
CPU time 0.57 seconds
Started May 23 03:37:22 PM PDT 24
Finished May 23 03:37:30 PM PDT 24
Peak memory 197540 kb
Host smart-6966ceff-8c28-4ce3-bb33-6240c263aaea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261886778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.3261886778
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.2290440781
Short name T832
Test name
Test status
Simulation time 65900520 ps
CPU time 0.67 seconds
Started May 23 03:37:22 PM PDT 24
Finished May 23 03:37:30 PM PDT 24
Peak memory 200880 kb
Host smart-fd181f95-6cb3-42cc-a6e2-34284c0440e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290440781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.2290440781
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_wakeup_race.1021853349
Short name T911
Test name
Test status
Simulation time 192237492 ps
CPU time 0.77 seconds
Started May 23 03:37:30 PM PDT 24
Finished May 23 03:37:36 PM PDT 24
Peak memory 197932 kb
Host smart-92b74303-3d38-46e0-b1d4-20c0ba83b4f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021853349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_w
akeup_race.1021853349
Directory /workspace/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.394486798
Short name T407
Test name
Test status
Simulation time 88696174 ps
CPU time 1 seconds
Started May 23 03:37:29 PM PDT 24
Finished May 23 03:37:36 PM PDT 24
Peak memory 199360 kb
Host smart-0ecdb360-15b8-4487-a439-40039a3b9d51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394486798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.394486798
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.3507084035
Short name T212
Test name
Test status
Simulation time 104371850 ps
CPU time 1.09 seconds
Started May 23 03:37:26 PM PDT 24
Finished May 23 03:37:35 PM PDT 24
Peak memory 208940 kb
Host smart-432dc803-3d29-4920-b9ae-d9a74be78094
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507084035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.3507084035
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.4127663194
Short name T347
Test name
Test status
Simulation time 232861241 ps
CPU time 0.92 seconds
Started May 23 03:37:23 PM PDT 24
Finished May 23 03:37:31 PM PDT 24
Peak memory 199608 kb
Host smart-8e9b51ca-c9a7-4c4b-bd8a-6fd421282022
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127663194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_
cm_ctrl_config_regwen.4127663194
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1936425566
Short name T715
Test name
Test status
Simulation time 849965689 ps
CPU time 2.89 seconds
Started May 23 03:37:23 PM PDT 24
Finished May 23 03:37:34 PM PDT 24
Peak memory 200508 kb
Host smart-c695a67a-a862-4175-850d-274d1e53f802
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936425566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1936425566
Directory /workspace/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3196723053
Short name T209
Test name
Test status
Simulation time 1299989904 ps
CPU time 2.35 seconds
Started May 23 03:37:24 PM PDT 24
Finished May 23 03:37:33 PM PDT 24
Peak memory 200592 kb
Host smart-4fefb33d-8ee7-4885-bee4-000f9a825763
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196723053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3196723053
Directory /workspace/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.2891270042
Short name T696
Test name
Test status
Simulation time 54369346 ps
CPU time 0.86 seconds
Started May 23 03:37:30 PM PDT 24
Finished May 23 03:37:36 PM PDT 24
Peak memory 198696 kb
Host smart-37894181-804a-46ea-8598-cb3d98649ab4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891270042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2891270042
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.4057132674
Short name T667
Test name
Test status
Simulation time 27059479 ps
CPU time 0.66 seconds
Started May 23 03:37:31 PM PDT 24
Finished May 23 03:37:36 PM PDT 24
Peak memory 198824 kb
Host smart-964d930d-df07-40be-bc07-c2d6158a295d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057132674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.4057132674
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all.680122943
Short name T569
Test name
Test status
Simulation time 3129344561 ps
CPU time 4.4 seconds
Started May 23 03:37:23 PM PDT 24
Finished May 23 03:37:35 PM PDT 24
Peak memory 200700 kb
Host smart-b8905ad0-3f1d-4e0e-8173-fd23a5386871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680122943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.680122943
Directory /workspace/27.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all_with_rand_reset.1206523284
Short name T53
Test name
Test status
Simulation time 7695507921 ps
CPU time 9.96 seconds
Started May 23 03:37:23 PM PDT 24
Finished May 23 03:37:39 PM PDT 24
Peak memory 200896 kb
Host smart-6517082b-0b2e-455a-b76c-5d768c334522
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206523284 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all_with_rand_reset.1206523284
Directory /workspace/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup.2709718722
Short name T695
Test name
Test status
Simulation time 110176188 ps
CPU time 0.71 seconds
Started May 23 03:37:24 PM PDT 24
Finished May 23 03:37:32 PM PDT 24
Peak memory 198696 kb
Host smart-3a22795c-8ff4-486b-9755-ebb7a49927b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709718722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.2709718722
Directory /workspace/27.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup_reset.352855653
Short name T339
Test name
Test status
Simulation time 375603115 ps
CPU time 1.14 seconds
Started May 23 03:37:23 PM PDT 24
Finished May 23 03:37:31 PM PDT 24
Peak memory 199952 kb
Host smart-23adf7c1-93e0-442e-bdf0-3483629d00d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352855653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.352855653
Directory /workspace/27.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.1273372839
Short name T198
Test name
Test status
Simulation time 112306351 ps
CPU time 0.75 seconds
Started May 23 03:37:27 PM PDT 24
Finished May 23 03:37:34 PM PDT 24
Peak memory 198356 kb
Host smart-11be3e85-03b9-4234-b820-a0586a3ffa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273372839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.1273372839
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.3770236217
Short name T610
Test name
Test status
Simulation time 61791995 ps
CPU time 0.84 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 198624 kb
Host smart-09615cd7-eb39-46e2-b789-85d89f6c1bfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770236217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.3770236217
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.980727981
Short name T522
Test name
Test status
Simulation time 39634046 ps
CPU time 0.59 seconds
Started May 23 03:37:24 PM PDT 24
Finished May 23 03:37:32 PM PDT 24
Peak memory 197532 kb
Host smart-8f24d099-a64f-4af3-9dcb-3dc3b754cc89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980727981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_
malfunc.980727981
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.4265161749
Short name T132
Test name
Test status
Simulation time 317715428 ps
CPU time 0.98 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 197940 kb
Host smart-c0737db5-182f-4cde-b2ee-4eb9bee199a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265161749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.4265161749
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.3889270773
Short name T472
Test name
Test status
Simulation time 73249175 ps
CPU time 0.62 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:42 PM PDT 24
Peak memory 196940 kb
Host smart-1c609a1d-fb8d-40ba-b7ee-842432f876b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889270773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.3889270773
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.486986270
Short name T432
Test name
Test status
Simulation time 45588933 ps
CPU time 0.62 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:45 PM PDT 24
Peak memory 197568 kb
Host smart-e12ec9ad-66a5-4ba5-83f5-ce0506174c95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486986270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.486986270
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.2528965286
Short name T600
Test name
Test status
Simulation time 44807764 ps
CPU time 0.73 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:45 PM PDT 24
Peak memory 200868 kb
Host smart-c1bcfb53-740f-4242-87ad-9e03b243025b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528965286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.2528965286
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.4070418991
Short name T516
Test name
Test status
Simulation time 309942763 ps
CPU time 1.11 seconds
Started May 23 03:37:21 PM PDT 24
Finished May 23 03:37:28 PM PDT 24
Peak memory 199280 kb
Host smart-67586b3e-7d57-466c-a8cd-a34bcef80a7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070418991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_w
akeup_race.4070418991
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.241237504
Short name T218
Test name
Test status
Simulation time 95707823 ps
CPU time 0.88 seconds
Started May 23 03:37:24 PM PDT 24
Finished May 23 03:37:32 PM PDT 24
Peak memory 199184 kb
Host smart-78a0abd4-324d-42ef-bce7-c6eb13572e98
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241237504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.241237504
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.2545917350
Short name T31
Test name
Test status
Simulation time 147968420 ps
CPU time 0.79 seconds
Started May 23 03:37:38 PM PDT 24
Finished May 23 03:37:41 PM PDT 24
Peak memory 208980 kb
Host smart-cd225998-cb4f-42df-865e-4568af9b49b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545917350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.2545917350
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.1343700561
Short name T310
Test name
Test status
Simulation time 226446358 ps
CPU time 1.24 seconds
Started May 23 03:37:22 PM PDT 24
Finished May 23 03:37:30 PM PDT 24
Peak memory 199584 kb
Host smart-22c85b82-ef58-4554-bb1f-9ad943f4319b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343700561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_
cm_ctrl_config_regwen.1343700561
Directory /workspace/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3410272917
Short name T771
Test name
Test status
Simulation time 763773150 ps
CPU time 2.96 seconds
Started May 23 03:37:19 PM PDT 24
Finished May 23 03:37:28 PM PDT 24
Peak memory 200592 kb
Host smart-519410d4-5f37-4a6f-bab5-eb898cc71c4f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410272917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3410272917
Directory /workspace/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1499127122
Short name T659
Test name
Test status
Simulation time 926748229 ps
CPU time 3.05 seconds
Started May 23 03:37:26 PM PDT 24
Finished May 23 03:37:36 PM PDT 24
Peak memory 200648 kb
Host smart-978552ab-77a7-42fd-a8f6-0d30f0dfd678
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499127122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1499127122
Directory /workspace/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.1825321299
Short name T840
Test name
Test status
Simulation time 460299246 ps
CPU time 0.85 seconds
Started May 23 03:37:27 PM PDT 24
Finished May 23 03:37:34 PM PDT 24
Peak memory 198852 kb
Host smart-0bb8dfd9-ede8-46bc-bd4a-d64193697492
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825321299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1825321299
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.3008648810
Short name T223
Test name
Test status
Simulation time 62989147 ps
CPU time 0.62 seconds
Started May 23 03:37:18 PM PDT 24
Finished May 23 03:37:25 PM PDT 24
Peak memory 197980 kb
Host smart-0f21e1de-1d7f-4e42-afee-dd217d2820b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008648810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.3008648810
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all.1056963060
Short name T94
Test name
Test status
Simulation time 600860765 ps
CPU time 2.91 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:47 PM PDT 24
Peak memory 200608 kb
Host smart-015ec789-c681-4d7e-9dae-2d2b5e5e007f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056963060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.1056963060
Directory /workspace/28.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all_with_rand_reset.1059000900
Short name T55
Test name
Test status
Simulation time 4124160360 ps
CPU time 15.7 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:38:02 PM PDT 24
Peak memory 200920 kb
Host smart-72ed0d8d-eec3-4ee0-8b29-6420e03ba966
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059000900 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all_with_rand_reset.1059000900
Directory /workspace/28.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup.2786872735
Short name T496
Test name
Test status
Simulation time 79978707 ps
CPU time 0.74 seconds
Started May 23 03:37:23 PM PDT 24
Finished May 23 03:37:30 PM PDT 24
Peak memory 197812 kb
Host smart-a80fee84-bac6-4ddd-94a1-0562172f39f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786872735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.2786872735
Directory /workspace/28.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup_reset.2055887597
Short name T790
Test name
Test status
Simulation time 300661134 ps
CPU time 1.48 seconds
Started May 23 03:37:26 PM PDT 24
Finished May 23 03:37:35 PM PDT 24
Peak memory 200636 kb
Host smart-7df0f0ed-fb3c-40e2-bbe8-12c704235df0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055887597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.2055887597
Directory /workspace/28.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.3371498661
Short name T706
Test name
Test status
Simulation time 25434793 ps
CPU time 0.7 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:45 PM PDT 24
Peak memory 198328 kb
Host smart-82d90dfd-f053-47b1-b806-6f36da65e713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371498661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.3371498661
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.3276989255
Short name T686
Test name
Test status
Simulation time 107914946 ps
CPU time 0.7 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:47 PM PDT 24
Peak memory 198712 kb
Host smart-144395cc-302a-413b-9f18-7b039e725012
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276989255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.3276989255
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3134211432
Short name T736
Test name
Test status
Simulation time 53933805 ps
CPU time 0.57 seconds
Started May 23 03:37:38 PM PDT 24
Finished May 23 03:37:42 PM PDT 24
Peak memory 197580 kb
Host smart-a987c761-a423-49fd-8a6b-93fd45256528
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134211432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.3134211432
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.1575106059
Short name T948
Test name
Test status
Simulation time 286006528 ps
CPU time 1.01 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:45 PM PDT 24
Peak memory 197616 kb
Host smart-32d5660f-01dc-41dd-ba20-02a0ae53015a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575106059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1575106059
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.3512174296
Short name T292
Test name
Test status
Simulation time 50513690 ps
CPU time 0.63 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:45 PM PDT 24
Peak memory 197576 kb
Host smart-6d8ee101-d88d-469a-8655-8ebd9cd338c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512174296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.3512174296
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.3488952507
Short name T719
Test name
Test status
Simulation time 29982978 ps
CPU time 0.6 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 197596 kb
Host smart-279e7f00-8dbf-4fcc-ae56-764ed3c177a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488952507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.3488952507
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.1460986999
Short name T596
Test name
Test status
Simulation time 74421272 ps
CPU time 0.67 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 200856 kb
Host smart-e05c8d65-a7fd-45c9-bd6e-45334985c968
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460986999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.1460986999
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.697988523
Short name T903
Test name
Test status
Simulation time 78654179 ps
CPU time 0.77 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:43 PM PDT 24
Peak memory 198112 kb
Host smart-b2fdf811-a113-45e0-b3bd-d86a73b90e82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697988523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wa
keup_race.697988523
Directory /workspace/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.2935663487
Short name T938
Test name
Test status
Simulation time 42271504 ps
CPU time 0.77 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 198108 kb
Host smart-c1678a90-49d7-4e25-ad82-28dae56d8b7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935663487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.2935663487
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.1221696888
Short name T898
Test name
Test status
Simulation time 108014868 ps
CPU time 1.06 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 208876 kb
Host smart-98ab4c0b-065c-4984-ae8f-0cb4a0739366
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221696888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.1221696888
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.3200934015
Short name T579
Test name
Test status
Simulation time 138665159 ps
CPU time 0.75 seconds
Started May 23 03:37:38 PM PDT 24
Finished May 23 03:37:41 PM PDT 24
Peak memory 198680 kb
Host smart-3aaadf97-f5a0-42cf-9aed-6591d56e6593
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200934015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_
cm_ctrl_config_regwen.3200934015
Directory /workspace/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3401008151
Short name T697
Test name
Test status
Simulation time 1054192680 ps
CPU time 2.02 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:45 PM PDT 24
Peak memory 200652 kb
Host smart-610ed378-eb13-4037-9ab0-1a99b74a6ae2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401008151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3401008151
Directory /workspace/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2795367950
Short name T330
Test name
Test status
Simulation time 910811321 ps
CPU time 2.43 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:49 PM PDT 24
Peak memory 200612 kb
Host smart-b6952b44-7ac5-4a5a-9708-39eccc7e9c8c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795367950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2795367950
Directory /workspace/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1698338174
Short name T834
Test name
Test status
Simulation time 65778362 ps
CPU time 0.9 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 199148 kb
Host smart-0c3d5399-1b96-4157-a611-fd03788096d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698338174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1698338174
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.1859668749
Short name T962
Test name
Test status
Simulation time 40419705 ps
CPU time 0.73 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 198860 kb
Host smart-a34c5e53-5fd7-4f19-bd9c-9af5907a31da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859668749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1859668749
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all.3460691134
Short name T251
Test name
Test status
Simulation time 2214438307 ps
CPU time 3.23 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:50 PM PDT 24
Peak memory 200728 kb
Host smart-fb2efa7b-d9bc-4773-a825-bf1cbaad8e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460691134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.3460691134
Directory /workspace/29.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all_with_rand_reset.195062015
Short name T122
Test name
Test status
Simulation time 21664058617 ps
CPU time 22.21 seconds
Started May 23 03:37:38 PM PDT 24
Finished May 23 03:38:02 PM PDT 24
Peak memory 200908 kb
Host smart-eba54f7d-b300-43ee-aae7-4cd7d8093d3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195062015 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all_with_rand_reset.195062015
Directory /workspace/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup.3081942662
Short name T208
Test name
Test status
Simulation time 132805982 ps
CPU time 0.93 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 198692 kb
Host smart-77fb9f33-3d93-41df-8614-73e0cb451c2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081942662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.3081942662
Directory /workspace/29.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup_reset.3303785836
Short name T584
Test name
Test status
Simulation time 79630771 ps
CPU time 0.85 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 198532 kb
Host smart-e3718278-f023-45b2-b2b2-50862f0d9845
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303785836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.3303785836
Directory /workspace/29.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.3911911995
Short name T331
Test name
Test status
Simulation time 41007473 ps
CPU time 0.85 seconds
Started May 23 03:36:11 PM PDT 24
Finished May 23 03:36:18 PM PDT 24
Peak memory 199772 kb
Host smart-2dc61c18-03b1-41ce-8efe-d3ebcc9ea264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911911995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.3911911995
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.356936314
Short name T921
Test name
Test status
Simulation time 57917901 ps
CPU time 0.84 seconds
Started May 23 03:36:09 PM PDT 24
Finished May 23 03:36:14 PM PDT 24
Peak memory 198656 kb
Host smart-2687f6f4-8e4c-45e6-af0c-f863009c2919
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356936314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disab
le_rom_integrity_check.356936314
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3969777417
Short name T385
Test name
Test status
Simulation time 39846527 ps
CPU time 0.6 seconds
Started May 23 03:36:13 PM PDT 24
Finished May 23 03:36:21 PM PDT 24
Peak memory 197528 kb
Host smart-d7759c76-5f25-4b3a-b5a8-4cf4ba377e45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969777417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.3969777417
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.1277858906
Short name T967
Test name
Test status
Simulation time 1164885564 ps
CPU time 0.96 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 197656 kb
Host smart-1d20a910-4095-4705-aa90-57adaad8d7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277858906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.1277858906
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.1589184326
Short name T523
Test name
Test status
Simulation time 48236221 ps
CPU time 0.63 seconds
Started May 23 03:36:08 PM PDT 24
Finished May 23 03:36:12 PM PDT 24
Peak memory 197460 kb
Host smart-59646f1b-aa47-4b91-97c2-c809d3911a14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589184326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.1589184326
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.2604026479
Short name T907
Test name
Test status
Simulation time 62308961 ps
CPU time 0.6 seconds
Started May 23 03:36:14 PM PDT 24
Finished May 23 03:36:22 PM PDT 24
Peak memory 197888 kb
Host smart-ed268f04-fd1b-4df3-bdb1-bc01fc6b40f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604026479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.2604026479
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1156845604
Short name T359
Test name
Test status
Simulation time 51837350 ps
CPU time 0.68 seconds
Started May 23 03:36:11 PM PDT 24
Finished May 23 03:36:18 PM PDT 24
Peak memory 200824 kb
Host smart-be801588-efda-4103-9d90-bafe79002853
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156845604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1156845604
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.614754191
Short name T82
Test name
Test status
Simulation time 181997354 ps
CPU time 0.85 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:30 PM PDT 24
Peak memory 198036 kb
Host smart-99188de3-099c-4b94-8643-025b67508d7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614754191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wak
eup_race.614754191
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.1261985579
Short name T631
Test name
Test status
Simulation time 105744659 ps
CPU time 0.78 seconds
Started May 23 03:36:09 PM PDT 24
Finished May 23 03:36:14 PM PDT 24
Peak memory 197848 kb
Host smart-f4f7d6a2-c7e8-4db7-bad1-3dc82e5dcf8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261985579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.1261985579
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.3037957553
Short name T322
Test name
Test status
Simulation time 470431993 ps
CPU time 1.14 seconds
Started May 23 03:36:08 PM PDT 24
Finished May 23 03:36:13 PM PDT 24
Peak memory 200440 kb
Host smart-564d8199-3e3b-4140-bbd8-d173efade36e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037957553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_c
m_ctrl_config_regwen.3037957553
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2536690186
Short name T328
Test name
Test status
Simulation time 1021108590 ps
CPU time 2.37 seconds
Started May 23 03:36:11 PM PDT 24
Finished May 23 03:36:20 PM PDT 24
Peak memory 200648 kb
Host smart-a0b9d8ea-f7e2-498a-94ec-d02f1bf17e70
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536690186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2536690186
Directory /workspace/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.818596780
Short name T952
Test name
Test status
Simulation time 921275359 ps
CPU time 2.05 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:17 PM PDT 24
Peak memory 200604 kb
Host smart-0b559b8b-1418-4e3c-88ef-25558ad8adeb
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818596780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.818596780
Directory /workspace/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.3435919713
Short name T912
Test name
Test status
Simulation time 74699350 ps
CPU time 0.95 seconds
Started May 23 03:36:12 PM PDT 24
Finished May 23 03:36:19 PM PDT 24
Peak memory 198804 kb
Host smart-6433e753-440f-45a9-8cb7-5db2b9eefb55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435919713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3435919713
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.3353948312
Short name T745
Test name
Test status
Simulation time 102730595 ps
CPU time 0.62 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 198024 kb
Host smart-4809c302-e47b-4e32-86a9-143a70dd386f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353948312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.3353948312
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all.3062490740
Short name T217
Test name
Test status
Simulation time 8411022411 ps
CPU time 3.79 seconds
Started May 23 03:36:11 PM PDT 24
Finished May 23 03:36:22 PM PDT 24
Peak memory 200712 kb
Host smart-ebb45a01-7075-413c-bbe9-ff94a183914c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062490740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.3062490740
Directory /workspace/3.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3925286104
Short name T433
Test name
Test status
Simulation time 15258210496 ps
CPU time 19.79 seconds
Started May 23 03:36:18 PM PDT 24
Finished May 23 03:36:44 PM PDT 24
Peak memory 200904 kb
Host smart-64dd7616-d323-4ecf-a0c7-24b3c0b6512f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925286104 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all_with_rand_reset.3925286104
Directory /workspace/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup.2661442694
Short name T635
Test name
Test status
Simulation time 115395297 ps
CPU time 0.86 seconds
Started May 23 03:36:14 PM PDT 24
Finished May 23 03:36:22 PM PDT 24
Peak memory 198060 kb
Host smart-77d45177-f6d3-4264-b51d-e72f7b4d1de4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661442694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.2661442694
Directory /workspace/3.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup_reset.2061199856
Short name T169
Test name
Test status
Simulation time 307720015 ps
CPU time 1.17 seconds
Started May 23 03:36:14 PM PDT 24
Finished May 23 03:36:23 PM PDT 24
Peak memory 200496 kb
Host smart-d19d37c9-c08b-4a65-bb58-814f522b5d17
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061199856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.2061199856
Directory /workspace/3.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.1421908692
Short name T248
Test name
Test status
Simulation time 259915773 ps
CPU time 0.78 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:45 PM PDT 24
Peak memory 199456 kb
Host smart-f7c2c903-98a5-47a4-86ef-d47278c0b9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421908692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1421908692
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.152580465
Short name T766
Test name
Test status
Simulation time 49960201 ps
CPU time 0.59 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:44 PM PDT 24
Peak memory 197464 kb
Host smart-799ac66f-9bee-4e03-ab87-e42d3cf7c1fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152580465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_
malfunc.152580465
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.2295695199
Short name T983
Test name
Test status
Simulation time 166699221 ps
CPU time 0.95 seconds
Started May 23 03:37:38 PM PDT 24
Finished May 23 03:37:42 PM PDT 24
Peak memory 197616 kb
Host smart-355ef224-0ebb-4956-b69f-ac689ee260db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295695199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.2295695199
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.3191733281
Short name T382
Test name
Test status
Simulation time 50455722 ps
CPU time 0.62 seconds
Started May 23 03:37:42 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 197608 kb
Host smart-14e7fcfc-9cc5-4726-9a7e-63a8395aa2ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191733281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.3191733281
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.3173270249
Short name T213
Test name
Test status
Simulation time 89324663 ps
CPU time 0.64 seconds
Started May 23 03:37:43 PM PDT 24
Finished May 23 03:37:50 PM PDT 24
Peak memory 197596 kb
Host smart-53acb50b-ff21-4234-b778-a869ac6dfbad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173270249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.3173270249
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.1511551332
Short name T192
Test name
Test status
Simulation time 199012796 ps
CPU time 0.92 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:43 PM PDT 24
Peak memory 199336 kb
Host smart-623cd4ea-a403-4ad1-a503-da2721653f7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511551332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_w
akeup_race.1511551332
Directory /workspace/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.4123232240
Short name T595
Test name
Test status
Simulation time 65201701 ps
CPU time 0.95 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:44 PM PDT 24
Peak memory 199300 kb
Host smart-36d34b58-0f35-4799-9dcf-61fc8a07667e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123232240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.4123232240
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.4291279355
Short name T805
Test name
Test status
Simulation time 153297471 ps
CPU time 0.85 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:47 PM PDT 24
Peak memory 208904 kb
Host smart-b93a85a1-31a9-48b8-b202-d115346f59fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291279355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.4291279355
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.4262704702
Short name T181
Test name
Test status
Simulation time 126053530 ps
CPU time 1.07 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 199784 kb
Host smart-f743366e-f1e0-4abd-ba26-c05ce7ab567b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262704702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_
cm_ctrl_config_regwen.4262704702
Directory /workspace/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.330972228
Short name T280
Test name
Test status
Simulation time 841832137 ps
CPU time 3.26 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:47 PM PDT 24
Peak memory 200584 kb
Host smart-814cdee9-7b89-45ab-93ae-ab0b939def72
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330972228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.330972228
Directory /workspace/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3926580648
Short name T585
Test name
Test status
Simulation time 919566645 ps
CPU time 3.27 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:50 PM PDT 24
Peak memory 200636 kb
Host smart-6d5f02e7-dcb3-4ca8-8364-37a092aecf00
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926580648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3926580648
Directory /workspace/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.1568650163
Short name T481
Test name
Test status
Simulation time 141875689 ps
CPU time 0.85 seconds
Started May 23 03:37:38 PM PDT 24
Finished May 23 03:37:40 PM PDT 24
Peak memory 198880 kb
Host smart-dc995d59-35d2-4915-b97d-c1889736eca7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568650163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1568650163
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.3873193491
Short name T741
Test name
Test status
Simulation time 29487434 ps
CPU time 0.73 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 198852 kb
Host smart-8ce2e8c4-31da-48b6-b2a6-d8d895daf1e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873193491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3873193491
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all.2850154379
Short name T642
Test name
Test status
Simulation time 402568537 ps
CPU time 1.9 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 200568 kb
Host smart-099ca3d2-1186-4e05-a4f3-2449c56cf248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850154379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.2850154379
Directory /workspace/30.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all_with_rand_reset.934911683
Short name T85
Test name
Test status
Simulation time 6056312796 ps
CPU time 21.73 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:38:06 PM PDT 24
Peak memory 200792 kb
Host smart-f287aff2-c5f9-4b9d-b5dd-673697279a72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934911683 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all_with_rand_reset.934911683
Directory /workspace/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup.3188858735
Short name T33
Test name
Test status
Simulation time 79413321 ps
CPU time 0.65 seconds
Started May 23 03:37:38 PM PDT 24
Finished May 23 03:37:42 PM PDT 24
Peak memory 197736 kb
Host smart-4d0c05b8-1749-4fb1-abd4-12fa1fdb77fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188858735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.3188858735
Directory /workspace/30.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.2560173151
Short name T759
Test name
Test status
Simulation time 40425037 ps
CPU time 0.67 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:47 PM PDT 24
Peak memory 198824 kb
Host smart-ad3b39c0-e992-400d-907d-d784aa406df1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560173151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.2560173151
Directory /workspace/30.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.972327908
Short name T334
Test name
Test status
Simulation time 52681325 ps
CPU time 0.72 seconds
Started May 23 03:37:38 PM PDT 24
Finished May 23 03:37:41 PM PDT 24
Peak memory 198124 kb
Host smart-a43c94ec-c418-4ab1-b87c-1399f0067bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972327908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.972327908
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.3947541862
Short name T143
Test name
Test status
Simulation time 51184729 ps
CPU time 0.8 seconds
Started May 23 03:37:42 PM PDT 24
Finished May 23 03:37:49 PM PDT 24
Peak memory 198696 kb
Host smart-1e90b9ea-a7a3-44c6-8608-9a23a039e1ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947541862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.3947541862
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2266487354
Short name T134
Test name
Test status
Simulation time 39998418 ps
CPU time 0.6 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:44 PM PDT 24
Peak memory 196840 kb
Host smart-140dd8bc-ad68-44d9-8128-511d2b2dc165
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266487354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.2266487354
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.683314828
Short name T623
Test name
Test status
Simulation time 161084681 ps
CPU time 1.04 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 197632 kb
Host smart-13f5c637-4450-454e-917e-aa8c40ea0065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683314828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.683314828
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.3561057850
Short name T988
Test name
Test status
Simulation time 34353663 ps
CPU time 0.6 seconds
Started May 23 03:37:44 PM PDT 24
Finished May 23 03:37:50 PM PDT 24
Peak memory 196864 kb
Host smart-f41dd310-909a-449b-964c-f255ac5cb8e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561057850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.3561057850
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.4089726927
Short name T5
Test name
Test status
Simulation time 49769108 ps
CPU time 0.66 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 197600 kb
Host smart-21205a0e-b265-42f6-aa6f-1c513858d46d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089726927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.4089726927
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.544388672
Short name T941
Test name
Test status
Simulation time 214678873 ps
CPU time 0.68 seconds
Started May 23 03:37:42 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 200856 kb
Host smart-348ccf3b-ecc6-4175-bc84-42b0c62ff06f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544388672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invali
d.544388672
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.653685455
Short name T720
Test name
Test status
Simulation time 286142823 ps
CPU time 1.18 seconds
Started May 23 03:37:38 PM PDT 24
Finished May 23 03:37:43 PM PDT 24
Peak memory 199092 kb
Host smart-bc9ea529-9118-4475-8339-3e8b50200615
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653685455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wa
keup_race.653685455
Directory /workspace/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.2716301606
Short name T307
Test name
Test status
Simulation time 284113864 ps
CPU time 0.85 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 199472 kb
Host smart-b6fa7e94-5157-441b-a26a-d472bf50631c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716301606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.2716301606
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.2278199325
Short name T243
Test name
Test status
Simulation time 109761634 ps
CPU time 0.97 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:44 PM PDT 24
Peak memory 200696 kb
Host smart-ba37ff58-c004-4916-99da-0342e1cadad0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278199325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.2278199325
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.2535556799
Short name T833
Test name
Test status
Simulation time 183065327 ps
CPU time 1.11 seconds
Started May 23 03:37:38 PM PDT 24
Finished May 23 03:37:41 PM PDT 24
Peak memory 199720 kb
Host smart-5be2e1c8-afb8-47a2-8906-65edc87f6bdd
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535556799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_
cm_ctrl_config_regwen.2535556799
Directory /workspace/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1377092336
Short name T222
Test name
Test status
Simulation time 822365915 ps
CPU time 2.99 seconds
Started May 23 03:37:43 PM PDT 24
Finished May 23 03:37:52 PM PDT 24
Peak memory 200556 kb
Host smart-dd4a259e-feaf-4320-bcc3-c4bdaf480142
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377092336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1377092336
Directory /workspace/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3488621434
Short name T270
Test name
Test status
Simulation time 854185851 ps
CPU time 2.92 seconds
Started May 23 03:37:38 PM PDT 24
Finished May 23 03:37:44 PM PDT 24
Peak memory 200592 kb
Host smart-2b1be728-eb2c-49fa-be27-ba2e49a4d2ae
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488621434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3488621434
Directory /workspace/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1268516745
Short name T913
Test name
Test status
Simulation time 59437208 ps
CPU time 0.87 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:47 PM PDT 24
Peak memory 198868 kb
Host smart-82935cf2-5fbd-4c2d-8fcb-e45c31cce735
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268516745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1268516745
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.155768168
Short name T748
Test name
Test status
Simulation time 55372499 ps
CPU time 0.63 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 198876 kb
Host smart-e2c02bea-34a1-4f8e-a2aa-4c028b87c93c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155768168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.155768168
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all.2921386512
Short name T435
Test name
Test status
Simulation time 369516503 ps
CPU time 1.21 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:47 PM PDT 24
Peak memory 200656 kb
Host smart-5ec0496d-39dc-4f5b-84e1-cc7a84aa4349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921386512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.2921386512
Directory /workspace/31.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all_with_rand_reset.1836311123
Short name T49
Test name
Test status
Simulation time 10341121929 ps
CPU time 33.43 seconds
Started May 23 03:37:42 PM PDT 24
Finished May 23 03:38:21 PM PDT 24
Peak memory 200864 kb
Host smart-30759a8c-f884-4d76-a91c-c3fd4edce2f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836311123 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all_with_rand_reset.1836311123
Directory /workspace/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup.765685732
Short name T633
Test name
Test status
Simulation time 126534451 ps
CPU time 0.99 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:45 PM PDT 24
Peak memory 199112 kb
Host smart-72364165-fdb6-48be-8c29-15e4930827fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765685732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.765685732
Directory /workspace/31.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup_reset.248588922
Short name T576
Test name
Test status
Simulation time 214034081 ps
CPU time 1.12 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:45 PM PDT 24
Peak memory 199732 kb
Host smart-396e6559-37f7-423f-a929-5620f537ab1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248588922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.248588922
Directory /workspace/31.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.3040832235
Short name T711
Test name
Test status
Simulation time 40613815 ps
CPU time 0.88 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 199752 kb
Host smart-86a2aeb0-955b-4cc7-ae23-753222adf1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040832235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.3040832235
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.1892030896
Short name T567
Test name
Test status
Simulation time 75593016 ps
CPU time 0.69 seconds
Started May 23 03:37:44 PM PDT 24
Finished May 23 03:37:50 PM PDT 24
Peak memory 198640 kb
Host smart-5633c3fe-d324-47d6-b82e-5e55d86db725
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892030896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.1892030896
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.3560545191
Short name T505
Test name
Test status
Simulation time 29497080 ps
CPU time 0.64 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 197068 kb
Host smart-18d03d43-ece4-4591-b69b-04d88cb4216e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560545191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.3560545191
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.4162098884
Short name T11
Test name
Test status
Simulation time 634670314 ps
CPU time 0.95 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 197608 kb
Host smart-b6abefed-f398-416f-bf9c-095d9ba2b495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162098884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.4162098884
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.2302468138
Short name T544
Test name
Test status
Simulation time 49251241 ps
CPU time 0.69 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 197612 kb
Host smart-c4fc27a9-18bf-4d75-8acd-67bdb03180c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302468138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.2302468138
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.2979715562
Short name T878
Test name
Test status
Simulation time 43098698 ps
CPU time 0.66 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 197596 kb
Host smart-6dade08a-6df4-4ece-84cc-255b35fc16e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979715562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.2979715562
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.503731086
Short name T268
Test name
Test status
Simulation time 45648576 ps
CPU time 0.71 seconds
Started May 23 03:37:45 PM PDT 24
Finished May 23 03:37:51 PM PDT 24
Peak memory 200864 kb
Host smart-4a5f83dc-0ff0-4082-a285-12f15aa53548
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503731086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invali
d.503731086
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_wakeup_race.3318769045
Short name T859
Test name
Test status
Simulation time 233309699 ps
CPU time 0.84 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 197600 kb
Host smart-494bb571-db2c-4217-b8ed-543fcebd6985
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318769045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_w
akeup_race.3318769045
Directory /workspace/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.323361252
Short name T996
Test name
Test status
Simulation time 32695102 ps
CPU time 0.7 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:47 PM PDT 24
Peak memory 198688 kb
Host smart-2ef6d67b-16eb-4033-9c8c-ed42588b2225
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323361252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.323361252
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.1463742761
Short name T619
Test name
Test status
Simulation time 163388391 ps
CPU time 0.79 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:47 PM PDT 24
Peak memory 209000 kb
Host smart-d956ffeb-6bc5-4b25-8874-85171c375824
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463742761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.1463742761
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.7855391
Short name T314
Test name
Test status
Simulation time 163467354 ps
CPU time 1.05 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:47 PM PDT 24
Peak memory 199720 kb
Host smart-9dbd387d-f3f9-4c74-a2cb-5b696d3e5433
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7855391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_con
fig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_
ctrl_config_regwen.7855391
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.707470700
Short name T640
Test name
Test status
Simulation time 1642280638 ps
CPU time 1.73 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 200620 kb
Host smart-e6790492-8815-45e7-b5ef-4c1b4f150fc7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707470700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.707470700
Directory /workspace/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.12448846
Short name T549
Test name
Test status
Simulation time 858333656 ps
CPU time 3.23 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:50 PM PDT 24
Peak memory 200576 kb
Host smart-bd4459e9-43ed-4b5a-9cbf-3edb62093914
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12448846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.12448846
Directory /workspace/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3906223377
Short name T543
Test name
Test status
Simulation time 146333344 ps
CPU time 0.88 seconds
Started May 23 03:37:43 PM PDT 24
Finished May 23 03:37:50 PM PDT 24
Peak memory 198816 kb
Host smart-393d5e1e-2a46-4aeb-b62b-84b8d0b392a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906223377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3906223377
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.1310885197
Short name T309
Test name
Test status
Simulation time 53514817 ps
CPU time 0.63 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:44 PM PDT 24
Peak memory 198804 kb
Host smart-1cdfe057-4627-4f09-8b1a-2ee60589c4b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310885197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.1310885197
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all.3988306134
Short name T570
Test name
Test status
Simulation time 320749748 ps
CPU time 0.97 seconds
Started May 23 03:37:43 PM PDT 24
Finished May 23 03:37:50 PM PDT 24
Peak memory 199408 kb
Host smart-ec242d1c-bf73-4678-900d-1d37d43384d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988306134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.3988306134
Directory /workspace/32.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.480348437
Short name T925
Test name
Test status
Simulation time 366748639 ps
CPU time 0.98 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 198968 kb
Host smart-079e9c1a-9739-4c6c-9cad-cf999b8086f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480348437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.480348437
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup_reset.1502403359
Short name T434
Test name
Test status
Simulation time 247180576 ps
CPU time 0.91 seconds
Started May 23 03:37:39 PM PDT 24
Finished May 23 03:37:45 PM PDT 24
Peak memory 199684 kb
Host smart-9ed71094-ea40-4101-8993-b46b4e93c3ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502403359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.1502403359
Directory /workspace/32.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.436779318
Short name T81
Test name
Test status
Simulation time 45878032 ps
CPU time 0.72 seconds
Started May 23 03:37:53 PM PDT 24
Finished May 23 03:37:57 PM PDT 24
Peak memory 198208 kb
Host smart-229d38e9-89d6-488b-8df8-9cdd34d9a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436779318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.436779318
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.612648356
Short name T882
Test name
Test status
Simulation time 37625427 ps
CPU time 0.63 seconds
Started May 23 03:37:51 PM PDT 24
Finished May 23 03:37:54 PM PDT 24
Peak memory 197556 kb
Host smart-4a25bf13-d35b-4ae4-acc1-6b2a8afa9f8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612648356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_
malfunc.612648356
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.2146601911
Short name T829
Test name
Test status
Simulation time 650978742 ps
CPU time 0.94 seconds
Started May 23 03:37:53 PM PDT 24
Finished May 23 03:37:57 PM PDT 24
Peak memory 197608 kb
Host smart-96684c28-b73d-4e59-8bfa-50a864872ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146601911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2146601911
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.337920001
Short name T348
Test name
Test status
Simulation time 47598055 ps
CPU time 0.65 seconds
Started May 23 03:37:58 PM PDT 24
Finished May 23 03:38:04 PM PDT 24
Peak memory 196848 kb
Host smart-3d46d4a9-8cc5-4a45-94da-85294272bc21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337920001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.337920001
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.3658020664
Short name T185
Test name
Test status
Simulation time 51827984 ps
CPU time 0.7 seconds
Started May 23 03:37:57 PM PDT 24
Finished May 23 03:38:03 PM PDT 24
Peak memory 197936 kb
Host smart-f933d0f7-ec03-4c0a-a13c-ffb32cf782c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658020664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.3658020664
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.2924923509
Short name T694
Test name
Test status
Simulation time 74905579 ps
CPU time 0.7 seconds
Started May 23 03:37:58 PM PDT 24
Finished May 23 03:38:05 PM PDT 24
Peak memory 200832 kb
Host smart-ce3b3f25-5525-428e-b73d-621c632cc971
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924923509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.2924923509
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.303591521
Short name T404
Test name
Test status
Simulation time 83985293 ps
CPU time 0.7 seconds
Started May 23 03:37:40 PM PDT 24
Finished May 23 03:37:46 PM PDT 24
Peak memory 197836 kb
Host smart-671f1030-d661-4602-b909-68bcfd461684
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303591521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wa
keup_race.303591521
Directory /workspace/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.3488379561
Short name T277
Test name
Test status
Simulation time 149094692 ps
CPU time 0.81 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:47 PM PDT 24
Peak memory 198696 kb
Host smart-33f48b7b-ffb0-4256-9179-19c0f363b419
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488379561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.3488379561
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.4004032679
Short name T955
Test name
Test status
Simulation time 112167369 ps
CPU time 1.06 seconds
Started May 23 03:38:00 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 208904 kb
Host smart-9d526de8-3f36-498d-aa10-27a04e0d2306
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004032679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.4004032679
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.2144271262
Short name T540
Test name
Test status
Simulation time 106586710 ps
CPU time 0.76 seconds
Started May 23 03:37:50 PM PDT 24
Finished May 23 03:37:53 PM PDT 24
Peak memory 198648 kb
Host smart-0cab1f4f-4ad8-4c99-92ba-345af50a3081
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144271262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_
cm_ctrl_config_regwen.2144271262
Directory /workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1456870614
Short name T293
Test name
Test status
Simulation time 858416788 ps
CPU time 2.98 seconds
Started May 23 03:37:51 PM PDT 24
Finished May 23 03:37:57 PM PDT 24
Peak memory 200572 kb
Host smart-982ab7fc-3bb2-4dce-9de9-bedde1d5d909
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456870614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1456870614
Directory /workspace/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2464253878
Short name T689
Test name
Test status
Simulation time 962507841 ps
CPU time 2.93 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:04 PM PDT 24
Peak memory 200444 kb
Host smart-68ab97de-b915-4622-afb7-6db28330f17c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464253878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2464253878
Directory /workspace/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.3855938564
Short name T408
Test name
Test status
Simulation time 54571100 ps
CPU time 0.89 seconds
Started May 23 03:37:51 PM PDT 24
Finished May 23 03:37:54 PM PDT 24
Peak memory 198580 kb
Host smart-96d5b90d-690b-4095-a957-e09e26dc2d57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855938564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3855938564
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.2254342742
Short name T690
Test name
Test status
Simulation time 28573920 ps
CPU time 0.69 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 198896 kb
Host smart-37cffbe9-5fa0-403c-81ed-8b1ce42a7ee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254342742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.2254342742
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all.4137652758
Short name T469
Test name
Test status
Simulation time 1271253281 ps
CPU time 2.43 seconds
Started May 23 03:37:51 PM PDT 24
Finished May 23 03:37:56 PM PDT 24
Peak memory 200672 kb
Host smart-83972113-42e4-400f-bc1a-d08f767288e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137652758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.4137652758
Directory /workspace/33.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all_with_rand_reset.1509766904
Short name T54
Test name
Test status
Simulation time 9773238948 ps
CPU time 34.31 seconds
Started May 23 03:37:54 PM PDT 24
Finished May 23 03:38:33 PM PDT 24
Peak memory 200872 kb
Host smart-ac2674e1-e0e0-465c-91f8-6b225e969870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509766904 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all_with_rand_reset.1509766904
Directory /workspace/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup.2808504090
Short name T451
Test name
Test status
Simulation time 171743152 ps
CPU time 0.99 seconds
Started May 23 03:37:41 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 199132 kb
Host smart-cc423bab-1d9c-4e1d-a193-ab115f8336f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808504090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.2808504090
Directory /workspace/33.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup_reset.941864908
Short name T654
Test name
Test status
Simulation time 245163560 ps
CPU time 1.21 seconds
Started May 23 03:37:57 PM PDT 24
Finished May 23 03:38:04 PM PDT 24
Peak memory 199708 kb
Host smart-17d53aa9-9db8-4d85-b36c-9ffac7665a3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941864908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.941864908
Directory /workspace/33.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.1065001093
Short name T386
Test name
Test status
Simulation time 30850767 ps
CPU time 0.78 seconds
Started May 23 03:37:54 PM PDT 24
Finished May 23 03:37:59 PM PDT 24
Peak memory 198452 kb
Host smart-b49841e1-b8c6-4908-b1b9-76e4cf78c094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065001093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.1065001093
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.3226956409
Short name T521
Test name
Test status
Simulation time 50173879 ps
CPU time 0.88 seconds
Started May 23 03:37:55 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 198604 kb
Host smart-f0ab06c5-4b52-423c-bfae-fbc5bf67503a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226956409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.3226956409
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1713308789
Short name T708
Test name
Test status
Simulation time 31399620 ps
CPU time 0.65 seconds
Started May 23 03:37:58 PM PDT 24
Finished May 23 03:38:04 PM PDT 24
Peak memory 197492 kb
Host smart-610e8053-067a-4a20-8212-cc00873febbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713308789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.1713308789
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.1169003392
Short name T905
Test name
Test status
Simulation time 160286089 ps
CPU time 1.01 seconds
Started May 23 03:37:53 PM PDT 24
Finished May 23 03:37:58 PM PDT 24
Peak memory 197860 kb
Host smart-ca671766-8a44-4462-b134-5b6d2bd20a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169003392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.1169003392
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.4133748912
Short name T608
Test name
Test status
Simulation time 33553578 ps
CPU time 0.63 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:01 PM PDT 24
Peak memory 197424 kb
Host smart-9d5f578b-d58b-4d88-9a46-06e00a7d6173
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133748912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.4133748912
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.3660087675
Short name T650
Test name
Test status
Simulation time 46363878 ps
CPU time 0.6 seconds
Started May 23 03:37:57 PM PDT 24
Finished May 23 03:38:03 PM PDT 24
Peak memory 197592 kb
Host smart-d796c193-77a1-48e2-bc81-e9ca7662b89f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660087675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.3660087675
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.1796493063
Short name T703
Test name
Test status
Simulation time 42396653 ps
CPU time 0.73 seconds
Started May 23 03:37:55 PM PDT 24
Finished May 23 03:38:01 PM PDT 24
Peak memory 200656 kb
Host smart-77e0e608-20f5-4c95-8e5c-81d34ad7b474
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796493063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.1796493063
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.1727539571
Short name T781
Test name
Test status
Simulation time 190123019 ps
CPU time 1.14 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:02 PM PDT 24
Peak memory 199200 kb
Host smart-8d77e89e-35c3-4ee7-9e16-ae807d103d18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727539571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_w
akeup_race.1727539571
Directory /workspace/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.2206141187
Short name T709
Test name
Test status
Simulation time 51586013 ps
CPU time 0.89 seconds
Started May 23 03:37:55 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 198644 kb
Host smart-ba1bc971-0d53-4e59-885d-542e3097e079
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206141187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.2206141187
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.1249309555
Short name T398
Test name
Test status
Simulation time 108303444 ps
CPU time 0.81 seconds
Started May 23 03:38:05 PM PDT 24
Finished May 23 03:38:11 PM PDT 24
Peak memory 208944 kb
Host smart-7e2c88ba-ea2f-49f5-b31c-78d49ec67d39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249309555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.1249309555
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.2517008863
Short name T612
Test name
Test status
Simulation time 132214795 ps
CPU time 0.91 seconds
Started May 23 03:37:54 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 198676 kb
Host smart-4cd8c318-51b0-40bb-b646-a6fd0ad4e5aa
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517008863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_
cm_ctrl_config_regwen.2517008863
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2062222992
Short name T751
Test name
Test status
Simulation time 865216061 ps
CPU time 2.99 seconds
Started May 23 03:37:55 PM PDT 24
Finished May 23 03:38:03 PM PDT 24
Peak memory 200684 kb
Host smart-2f266139-53ef-4c0d-9fb1-a39dc452b1e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062222992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2062222992
Directory /workspace/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3877753509
Short name T916
Test name
Test status
Simulation time 952812187 ps
CPU time 2.79 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:04 PM PDT 24
Peak memory 200620 kb
Host smart-8100a1fd-4f14-4ec7-9609-093e83d72dc1
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877753509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3877753509
Directory /workspace/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.791022244
Short name T665
Test name
Test status
Simulation time 181408145 ps
CPU time 0.9 seconds
Started May 23 03:37:54 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 198700 kb
Host smart-fde29a7c-beee-42e2-bb7b-1b47d1005032
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791022244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_
mubi.791022244
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.2637387070
Short name T32
Test name
Test status
Simulation time 40915316 ps
CPU time 0.68 seconds
Started May 23 03:37:57 PM PDT 24
Finished May 23 03:38:03 PM PDT 24
Peak memory 198844 kb
Host smart-b77ed25b-ead4-4c6f-81e6-97ccda7c2e48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637387070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.2637387070
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all.2468254879
Short name T361
Test name
Test status
Simulation time 2751654355 ps
CPU time 4 seconds
Started May 23 03:37:53 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 200760 kb
Host smart-2d5faecd-0735-4f43-8024-07d6199571ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468254879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.2468254879
Directory /workspace/34.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all_with_rand_reset.2095679743
Short name T126
Test name
Test status
Simulation time 35581813307 ps
CPU time 13.31 seconds
Started May 23 03:37:55 PM PDT 24
Finished May 23 03:38:13 PM PDT 24
Peak memory 200912 kb
Host smart-9483fd4c-53c2-4a40-8bc9-5f753e827456
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095679743 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all_with_rand_reset.2095679743
Directory /workspace/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup.2992533428
Short name T494
Test name
Test status
Simulation time 99689988 ps
CPU time 0.69 seconds
Started May 23 03:37:57 PM PDT 24
Finished May 23 03:38:03 PM PDT 24
Peak memory 197792 kb
Host smart-0b2343fe-9d57-4936-bfaf-704adde2652e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992533428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.2992533428
Directory /workspace/34.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup_reset.3470073329
Short name T393
Test name
Test status
Simulation time 273416223 ps
CPU time 1.5 seconds
Started May 23 03:37:53 PM PDT 24
Finished May 23 03:37:58 PM PDT 24
Peak memory 200528 kb
Host smart-1d273222-5ca3-4460-8455-2e9ef63beefb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470073329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.3470073329
Directory /workspace/34.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.939231922
Short name T677
Test name
Test status
Simulation time 34518560 ps
CPU time 1.01 seconds
Started May 23 03:37:52 PM PDT 24
Finished May 23 03:37:56 PM PDT 24
Peak memory 200404 kb
Host smart-e061a495-9e93-4e37-aaf7-fc6362eeb0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939231922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.939231922
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.3517596292
Short name T324
Test name
Test status
Simulation time 95460461 ps
CPU time 0.71 seconds
Started May 23 03:38:00 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 198228 kb
Host smart-82ddc217-a567-4549-868c-6b8d6f25ce46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517596292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.3517596292
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.906295666
Short name T930
Test name
Test status
Simulation time 29173043 ps
CPU time 0.65 seconds
Started May 23 03:37:55 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 196832 kb
Host smart-462816b3-0f6f-4078-83a8-983cf6745347
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906295666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_
malfunc.906295666
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.3543015415
Short name T418
Test name
Test status
Simulation time 186327024 ps
CPU time 1 seconds
Started May 23 03:38:05 PM PDT 24
Finished May 23 03:38:11 PM PDT 24
Peak memory 197556 kb
Host smart-b63a9f46-e1cb-4a21-b0db-90992f900ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543015415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.3543015415
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.399138454
Short name T457
Test name
Test status
Simulation time 31297005 ps
CPU time 0.6 seconds
Started May 23 03:37:53 PM PDT 24
Finished May 23 03:37:58 PM PDT 24
Peak memory 197644 kb
Host smart-92f9edf3-4be4-4585-bec8-30ad06218dd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399138454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.399138454
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.1704349301
Short name T179
Test name
Test status
Simulation time 45690422 ps
CPU time 0.63 seconds
Started May 23 03:37:57 PM PDT 24
Finished May 23 03:38:03 PM PDT 24
Peak memory 197608 kb
Host smart-d3ff248e-f0d5-428d-b320-df8f7d33b134
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704349301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1704349301
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.3193372799
Short name T244
Test name
Test status
Simulation time 54951686 ps
CPU time 0.7 seconds
Started May 23 03:37:58 PM PDT 24
Finished May 23 03:38:04 PM PDT 24
Peak memory 200852 kb
Host smart-0abe5580-5a79-4188-8772-563c75f8e773
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193372799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.3193372799
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.1602419540
Short name T762
Test name
Test status
Simulation time 529904000 ps
CPU time 0.85 seconds
Started May 23 03:37:55 PM PDT 24
Finished May 23 03:38:01 PM PDT 24
Peak memory 199176 kb
Host smart-34731233-ecfb-4a01-925c-2992026f08db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602419540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_w
akeup_race.1602419540
Directory /workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.1077433237
Short name T414
Test name
Test status
Simulation time 80104437 ps
CPU time 0.64 seconds
Started May 23 03:37:54 PM PDT 24
Finished May 23 03:37:59 PM PDT 24
Peak memory 197788 kb
Host smart-98838720-6bbd-49dd-9ddd-1d81237da7cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077433237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.1077433237
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.2278728717
Short name T375
Test name
Test status
Simulation time 242247788 ps
CPU time 0.79 seconds
Started May 23 03:37:53 PM PDT 24
Finished May 23 03:37:57 PM PDT 24
Peak memory 208928 kb
Host smart-d3709c0e-5342-41d4-bfc6-bed20beaa4c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278728717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.2278728717
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.2270897828
Short name T644
Test name
Test status
Simulation time 166084839 ps
CPU time 1.05 seconds
Started May 23 03:37:54 PM PDT 24
Finished May 23 03:37:59 PM PDT 24
Peak memory 199584 kb
Host smart-4cb8d202-451f-4f20-82b6-5098b97f7399
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270897828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_
cm_ctrl_config_regwen.2270897828
Directory /workspace/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3675319759
Short name T804
Test name
Test status
Simulation time 1026572287 ps
CPU time 1.87 seconds
Started May 23 03:37:54 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 200540 kb
Host smart-56f1753c-5716-4fe1-9d8f-c669b8672d27
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675319759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3675319759
Directory /workspace/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.3653925845
Short name T287
Test name
Test status
Simulation time 77184852 ps
CPU time 0.93 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:02 PM PDT 24
Peak memory 198712 kb
Host smart-ee2b097f-8236-4275-9614-e7292179d453
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653925845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3653925845
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.2754937063
Short name T214
Test name
Test status
Simulation time 32557025 ps
CPU time 0.67 seconds
Started May 23 03:38:05 PM PDT 24
Finished May 23 03:38:10 PM PDT 24
Peak memory 198820 kb
Host smart-56cc2266-c733-42b9-afba-300a77a9394c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754937063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2754937063
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all.1152440001
Short name T83
Test name
Test status
Simulation time 2706248860 ps
CPU time 6.19 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 200760 kb
Host smart-e996cb96-3ba5-4527-9bd3-c86d3f5a01f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152440001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.1152440001
Directory /workspace/35.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all_with_rand_reset.2549480090
Short name T86
Test name
Test status
Simulation time 15459765857 ps
CPU time 24.62 seconds
Started May 23 03:37:53 PM PDT 24
Finished May 23 03:38:22 PM PDT 24
Peak memory 200860 kb
Host smart-60341a3f-c3a2-4e86-8e2c-a81c711816d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549480090 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all_with_rand_reset.2549480090
Directory /workspace/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup.2753523199
Short name T35
Test name
Test status
Simulation time 282830638 ps
CPU time 1.31 seconds
Started May 23 03:37:57 PM PDT 24
Finished May 23 03:38:04 PM PDT 24
Peak memory 199308 kb
Host smart-524f47ac-77f9-4daa-839f-80ea1ee3654b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753523199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.2753523199
Directory /workspace/35.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup_reset.1602831779
Short name T729
Test name
Test status
Simulation time 192860939 ps
CPU time 0.96 seconds
Started May 23 03:37:54 PM PDT 24
Finished May 23 03:37:59 PM PDT 24
Peak memory 199560 kb
Host smart-6d38e08a-afc3-4a28-afd9-4568616f4619
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602831779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.1602831779
Directory /workspace/35.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.3644779899
Short name T189
Test name
Test status
Simulation time 19973379 ps
CPU time 0.66 seconds
Started May 23 03:37:54 PM PDT 24
Finished May 23 03:37:59 PM PDT 24
Peak memory 198200 kb
Host smart-85c92792-8512-4e63-a54b-1ed17bf98eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644779899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.3644779899
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.2241749498
Short name T809
Test name
Test status
Simulation time 57682588 ps
CPU time 0.77 seconds
Started May 23 03:37:59 PM PDT 24
Finished May 23 03:38:06 PM PDT 24
Peak memory 198736 kb
Host smart-6759e275-a9f6-47f7-b886-30c1c75765ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241749498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.2241749498
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2585060885
Short name T305
Test name
Test status
Simulation time 46757888 ps
CPU time 0.64 seconds
Started May 23 03:37:55 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 196856 kb
Host smart-45149d9e-34d9-42d8-a588-40b20d68c119
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585060885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.2585060885
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.2426320474
Short name T249
Test name
Test status
Simulation time 165393297 ps
CPU time 0.97 seconds
Started May 23 03:37:55 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 197616 kb
Host smart-80be9261-b9ae-4499-b026-a55036b8927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426320474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.2426320474
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.998622135
Short name T241
Test name
Test status
Simulation time 41688059 ps
CPU time 0.66 seconds
Started May 23 03:38:01 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 196896 kb
Host smart-deeb5438-1323-4bed-82d2-68da490d56b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998622135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.998622135
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.396608674
Short name T526
Test name
Test status
Simulation time 32061152 ps
CPU time 0.63 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:02 PM PDT 24
Peak memory 197596 kb
Host smart-ff9c7f85-3772-4e5c-9616-6f870a9d877c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396608674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.396608674
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.4289796631
Short name T990
Test name
Test status
Simulation time 55019113 ps
CPU time 0.69 seconds
Started May 23 03:37:55 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 200876 kb
Host smart-fbdf2fbd-d8ea-4dc2-8292-40152c179530
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289796631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.4289796631
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.4007377836
Short name T530
Test name
Test status
Simulation time 146697389 ps
CPU time 0.84 seconds
Started May 23 03:37:57 PM PDT 24
Finished May 23 03:38:03 PM PDT 24
Peak memory 197912 kb
Host smart-51c11c7f-0fbc-4715-a2e2-41955ceb88b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007377836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_w
akeup_race.4007377836
Directory /workspace/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.512629766
Short name T611
Test name
Test status
Simulation time 82369832 ps
CPU time 0.99 seconds
Started May 23 03:37:54 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 199328 kb
Host smart-7d16b247-457c-42f8-a2b1-a5b592ab8007
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512629766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.512629766
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.4274871222
Short name T870
Test name
Test status
Simulation time 95404774 ps
CPU time 1.04 seconds
Started May 23 03:38:05 PM PDT 24
Finished May 23 03:38:11 PM PDT 24
Peak memory 208928 kb
Host smart-bb7bbd10-ebb4-4618-bb66-acb0b95da9b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274871222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.4274871222
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.1855809348
Short name T391
Test name
Test status
Simulation time 105516261 ps
CPU time 0.91 seconds
Started May 23 03:38:01 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 198376 kb
Host smart-075856f6-5276-4529-bd20-64e6948bdd7b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855809348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_
cm_ctrl_config_regwen.1855809348
Directory /workspace/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2941401832
Short name T346
Test name
Test status
Simulation time 978442044 ps
CPU time 2.09 seconds
Started May 23 03:37:54 PM PDT 24
Finished May 23 03:38:01 PM PDT 24
Peak memory 200576 kb
Host smart-48d7c775-95f2-4193-9ac4-4664e763b994
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941401832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2941401832
Directory /workspace/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3050566425
Short name T511
Test name
Test status
Simulation time 839927640 ps
CPU time 3.27 seconds
Started May 23 03:37:58 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 200540 kb
Host smart-01c8da79-a581-4f3e-b0a4-572a40d82eff
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050566425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3050566425
Directory /workspace/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2841290091
Short name T606
Test name
Test status
Simulation time 76190331 ps
CPU time 0.98 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:02 PM PDT 24
Peak memory 198844 kb
Host smart-6b737b93-af12-4783-b167-14e0f24e980c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841290091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2841290091
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.2576578524
Short name T942
Test name
Test status
Simulation time 40947891 ps
CPU time 0.67 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:02 PM PDT 24
Peak memory 198860 kb
Host smart-47f65462-0bbf-4f36-832f-e156e47313fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576578524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.2576578524
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all.3173314835
Short name T403
Test name
Test status
Simulation time 921198326 ps
CPU time 1.8 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:02 PM PDT 24
Peak memory 200640 kb
Host smart-a4cc0ef4-0221-448e-84f4-053e0c52e9df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173314835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.3173314835
Directory /workspace/36.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all_with_rand_reset.3204099301
Short name T67
Test name
Test status
Simulation time 3547533396 ps
CPU time 14.1 seconds
Started May 23 03:38:05 PM PDT 24
Finished May 23 03:38:24 PM PDT 24
Peak memory 200820 kb
Host smart-c2f0acf6-68bd-463f-864c-f9f802a6a6a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204099301 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all_with_rand_reset.3204099301
Directory /workspace/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup.3530839745
Short name T424
Test name
Test status
Simulation time 106146908 ps
CPU time 0.85 seconds
Started May 23 03:37:57 PM PDT 24
Finished May 23 03:38:03 PM PDT 24
Peak memory 198684 kb
Host smart-5d15d99e-bb27-4592-b952-0ec70dade0b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530839745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.3530839745
Directory /workspace/36.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup_reset.214359759
Short name T264
Test name
Test status
Simulation time 161910318 ps
CPU time 1.1 seconds
Started May 23 03:37:53 PM PDT 24
Finished May 23 03:37:58 PM PDT 24
Peak memory 199556 kb
Host smart-67498d78-4892-47ec-be03-193e888c842d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214359759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.214359759
Directory /workspace/36.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.3913521008
Short name T814
Test name
Test status
Simulation time 22158985 ps
CPU time 0.66 seconds
Started May 23 03:38:00 PM PDT 24
Finished May 23 03:38:06 PM PDT 24
Peak memory 198184 kb
Host smart-2a07697c-6ebb-47de-a297-897b94f4882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913521008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.3913521008
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.4220557707
Short name T168
Test name
Test status
Simulation time 52893909 ps
CPU time 0.8 seconds
Started May 23 03:37:59 PM PDT 24
Finished May 23 03:38:05 PM PDT 24
Peak memory 198536 kb
Host smart-b846a323-ae56-446c-9e2e-4d89a96fe91d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220557707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.4220557707
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.989552819
Short name T428
Test name
Test status
Simulation time 30570983 ps
CPU time 0.63 seconds
Started May 23 03:37:55 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 197540 kb
Host smart-2b36faf2-5f76-4573-af6a-c25e8e94b941
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989552819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_
malfunc.989552819
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.421147102
Short name T473
Test name
Test status
Simulation time 585258982 ps
CPU time 0.96 seconds
Started May 23 03:37:58 PM PDT 24
Finished May 23 03:38:04 PM PDT 24
Peak memory 197640 kb
Host smart-85ca225e-8113-4d05-b7b8-1e6cc70b7148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421147102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.421147102
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.1079816105
Short name T641
Test name
Test status
Simulation time 66572091 ps
CPU time 0.58 seconds
Started May 23 03:37:58 PM PDT 24
Finished May 23 03:38:05 PM PDT 24
Peak memory 196916 kb
Host smart-04bcd0eb-2cac-4d55-860f-6f3a6f37eab8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079816105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.1079816105
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.2691213554
Short name T221
Test name
Test status
Simulation time 140647387 ps
CPU time 0.6 seconds
Started May 23 03:38:03 PM PDT 24
Finished May 23 03:38:09 PM PDT 24
Peak memory 197896 kb
Host smart-288b5e75-0141-4c7e-ae0f-bba2ebe60680
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691213554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.2691213554
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.3076606482
Short name T583
Test name
Test status
Simulation time 42555495 ps
CPU time 0.76 seconds
Started May 23 03:37:59 PM PDT 24
Finished May 23 03:38:05 PM PDT 24
Peak memory 200844 kb
Host smart-ab57baed-d4dd-4a5d-b97c-95e648b73dd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076606482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.3076606482
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_wakeup_race.2824155876
Short name T957
Test name
Test status
Simulation time 327435186 ps
CPU time 0.95 seconds
Started May 23 03:38:00 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 199148 kb
Host smart-a3426ff2-6632-4460-8e0f-d14509b10c71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824155876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_w
akeup_race.2824155876
Directory /workspace/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.1592032358
Short name T419
Test name
Test status
Simulation time 31614269 ps
CPU time 0.74 seconds
Started May 23 03:38:00 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 198740 kb
Host smart-923eb90d-d540-4b2b-9853-29dee426b97d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592032358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.1592032358
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.1782001661
Short name T236
Test name
Test status
Simulation time 98285532 ps
CPU time 0.92 seconds
Started May 23 03:37:58 PM PDT 24
Finished May 23 03:38:05 PM PDT 24
Peak memory 208968 kb
Host smart-7b2a0eab-1af5-412f-87b9-bb631ff0c081
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782001661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.1782001661
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.3213535821
Short name T618
Test name
Test status
Simulation time 190534344 ps
CPU time 0.84 seconds
Started May 23 03:38:01 PM PDT 24
Finished May 23 03:38:08 PM PDT 24
Peak memory 199328 kb
Host smart-dd498406-f9ed-4378-96ca-138ec895d498
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213535821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_
cm_ctrl_config_regwen.3213535821
Directory /workspace/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.844888081
Short name T29
Test name
Test status
Simulation time 980974250 ps
CPU time 2.07 seconds
Started May 23 03:37:59 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 200628 kb
Host smart-53586ab4-d6e5-493e-95a1-ddbef6b23e58
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844888081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.844888081
Directory /workspace/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2131216397
Short name T556
Test name
Test status
Simulation time 885153165 ps
CPU time 3.12 seconds
Started May 23 03:38:00 PM PDT 24
Finished May 23 03:38:09 PM PDT 24
Peak memory 200612 kb
Host smart-61d1a160-ba20-481a-8337-0dc48b43e4a6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131216397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2131216397
Directory /workspace/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.741438902
Short name T177
Test name
Test status
Simulation time 53216251 ps
CPU time 0.92 seconds
Started May 23 03:38:03 PM PDT 24
Finished May 23 03:38:09 PM PDT 24
Peak memory 198792 kb
Host smart-89fb4db4-ed25-4626-af2c-4bdc2e07faf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741438902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_
mubi.741438902
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.4117411591
Short name T279
Test name
Test status
Simulation time 81626638 ps
CPU time 0.61 seconds
Started May 23 03:37:59 PM PDT 24
Finished May 23 03:38:05 PM PDT 24
Peak memory 198056 kb
Host smart-af76bbd8-0990-45cf-8b92-aa63f10c5fcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117411591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.4117411591
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all.3590797593
Short name T734
Test name
Test status
Simulation time 3515910702 ps
CPU time 6.04 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 200740 kb
Host smart-9d3a2085-0dc9-4ec0-8117-f820e77e50e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590797593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.3590797593
Directory /workspace/37.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup.3741546990
Short name T717
Test name
Test status
Simulation time 36111355 ps
CPU time 0.66 seconds
Started May 23 03:38:03 PM PDT 24
Finished May 23 03:38:09 PM PDT 24
Peak memory 198028 kb
Host smart-f804ba74-553d-4feb-9298-975a1a25cf4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741546990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.3741546990
Directory /workspace/37.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup_reset.15162406
Short name T673
Test name
Test status
Simulation time 301652557 ps
CPU time 1.47 seconds
Started May 23 03:38:03 PM PDT 24
Finished May 23 03:38:10 PM PDT 24
Peak memory 200472 kb
Host smart-56ae22cb-ae52-46a1-bf9d-583ceeaaf2f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15162406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.15162406
Directory /workspace/37.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.3685264637
Short name T971
Test name
Test status
Simulation time 184938962 ps
CPU time 0.66 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:02 PM PDT 24
Peak memory 198148 kb
Host smart-f1c96869-3bdc-4a48-a2fc-fd1c0241c11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685264637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.3685264637
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.2799124490
Short name T488
Test name
Test status
Simulation time 77136380 ps
CPU time 0.7 seconds
Started May 23 03:37:56 PM PDT 24
Finished May 23 03:38:01 PM PDT 24
Peak memory 198960 kb
Host smart-e6273645-b17c-44b9-8805-12e9663674d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799124490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.2799124490
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.2036961534
Short name T220
Test name
Test status
Simulation time 29975366 ps
CPU time 0.65 seconds
Started May 23 03:37:59 PM PDT 24
Finished May 23 03:38:05 PM PDT 24
Peak memory 196832 kb
Host smart-481fc89a-20f1-4bcc-bbde-bf3e49ade27d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036961534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.2036961534
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.3086946730
Short name T687
Test name
Test status
Simulation time 633000626 ps
CPU time 0.98 seconds
Started May 23 03:37:53 PM PDT 24
Finished May 23 03:37:58 PM PDT 24
Peak memory 197900 kb
Host smart-18857123-82e7-45db-976b-7ee329f8bebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086946730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.3086946730
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.2055625363
Short name T15
Test name
Test status
Simulation time 53420283 ps
CPU time 0.62 seconds
Started May 23 03:38:00 PM PDT 24
Finished May 23 03:38:06 PM PDT 24
Peak memory 196916 kb
Host smart-499a9df9-bed7-49b8-8b1f-b2295a066333
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055625363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.2055625363
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.2824462892
Short name T802
Test name
Test status
Simulation time 23922768 ps
CPU time 0.61 seconds
Started May 23 03:38:01 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 197900 kb
Host smart-1b683d09-72ca-4ba4-92ce-78b5483df2f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824462892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.2824462892
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.100503805
Short name T960
Test name
Test status
Simulation time 40147371 ps
CPU time 0.7 seconds
Started May 23 03:38:00 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 200836 kb
Host smart-c26d19ff-f8e6-4519-8414-36717e0f4cce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100503805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invali
d.100503805
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.2479905298
Short name T893
Test name
Test status
Simulation time 197788277 ps
CPU time 1.08 seconds
Started May 23 03:38:02 PM PDT 24
Finished May 23 03:38:08 PM PDT 24
Peak memory 199236 kb
Host smart-303be8f6-e7fa-4793-8060-d4f7754b122c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479905298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_w
akeup_race.2479905298
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.2536985213
Short name T476
Test name
Test status
Simulation time 97429091 ps
CPU time 0.85 seconds
Started May 23 03:38:01 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 199412 kb
Host smart-1f33fbef-4548-4480-bbb4-3208691e13e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536985213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.2536985213
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.2884415839
Short name T959
Test name
Test status
Simulation time 123752434 ps
CPU time 0.91 seconds
Started May 23 03:38:00 PM PDT 24
Finished May 23 03:38:06 PM PDT 24
Peak memory 208884 kb
Host smart-567e21ce-5137-4d3e-b304-dc1dbd728832
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884415839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.2884415839
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.2994766967
Short name T628
Test name
Test status
Simulation time 141845224 ps
CPU time 0.75 seconds
Started May 23 03:37:59 PM PDT 24
Finished May 23 03:38:05 PM PDT 24
Peak memory 198308 kb
Host smart-a21a23b1-5f78-4e6b-b2cb-722cec31d982
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994766967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_
cm_ctrl_config_regwen.2994766967
Directory /workspace/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1420579687
Short name T426
Test name
Test status
Simulation time 772222196 ps
CPU time 3.07 seconds
Started May 23 03:37:59 PM PDT 24
Finished May 23 03:38:08 PM PDT 24
Peak memory 200608 kb
Host smart-3309a5d8-853d-496f-a752-93c4a980d515
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420579687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1420579687
Directory /workspace/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2341259765
Short name T714
Test name
Test status
Simulation time 1022954895 ps
CPU time 2.16 seconds
Started May 23 03:37:57 PM PDT 24
Finished May 23 03:38:04 PM PDT 24
Peak memory 200568 kb
Host smart-7b164412-7df0-4c20-8ff4-87349fdaab90
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341259765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2341259765
Directory /workspace/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.1969015841
Short name T975
Test name
Test status
Simulation time 94396077 ps
CPU time 0.79 seconds
Started May 23 03:37:58 PM PDT 24
Finished May 23 03:38:04 PM PDT 24
Peak memory 198912 kb
Host smart-e955bdd1-9c03-4276-bcfa-3b103749927a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969015841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1969015841
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.2342715009
Short name T647
Test name
Test status
Simulation time 43308163 ps
CPU time 0.62 seconds
Started May 23 03:38:00 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 198864 kb
Host smart-7fd108f1-9e14-4e45-9a01-7239f5931f7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342715009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.2342715009
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all.2407818754
Short name T89
Test name
Test status
Simulation time 1654828271 ps
CPU time 3.31 seconds
Started May 23 03:37:58 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 200680 kb
Host smart-87960df1-b271-49bd-97cf-28236a701fdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407818754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.2407818754
Directory /workspace/38.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all_with_rand_reset.1638690999
Short name T935
Test name
Test status
Simulation time 4640208673 ps
CPU time 11.64 seconds
Started May 23 03:38:00 PM PDT 24
Finished May 23 03:38:18 PM PDT 24
Peak memory 200848 kb
Host smart-dab7cfc8-9480-4bfe-a8f2-7d36195cf421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638690999 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all_with_rand_reset.1638690999
Directory /workspace/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup.774259033
Short name T286
Test name
Test status
Simulation time 268996454 ps
CPU time 1.05 seconds
Started May 23 03:38:01 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 199304 kb
Host smart-bd739494-14c3-41f7-af75-bf8538f1c825
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774259033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.774259033
Directory /workspace/38.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup_reset.1519381383
Short name T675
Test name
Test status
Simulation time 266002778 ps
CPU time 1.36 seconds
Started May 23 03:38:00 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 199900 kb
Host smart-c5bb2eb2-9966-4b15-8d03-911f140cfb4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519381383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.1519381383
Directory /workspace/38.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.3141524164
Short name T602
Test name
Test status
Simulation time 44422115 ps
CPU time 0.89 seconds
Started May 23 03:38:06 PM PDT 24
Finished May 23 03:38:12 PM PDT 24
Peak memory 199648 kb
Host smart-ada7936f-d3d9-4280-a1a5-596732ef736d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141524164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.3141524164
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.2938741606
Short name T453
Test name
Test status
Simulation time 74899605 ps
CPU time 0.71 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:14 PM PDT 24
Peak memory 198648 kb
Host smart-2ddd6c27-f262-4eca-9390-6a6e67ca072c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938741606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.2938741606
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.322872507
Short name T788
Test name
Test status
Simulation time 29182038 ps
CPU time 0.63 seconds
Started May 23 03:38:05 PM PDT 24
Finished May 23 03:38:11 PM PDT 24
Peak memory 196748 kb
Host smart-c9455e7a-7a54-4c05-8e9b-91a0c2da6a8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322872507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_
malfunc.322872507
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.252276594
Short name T12
Test name
Test status
Simulation time 786397961 ps
CPU time 0.94 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:14 PM PDT 24
Peak memory 197644 kb
Host smart-a4cd13ec-04ac-4f37-b60e-746c75ceb1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252276594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.252276594
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.2947112656
Short name T775
Test name
Test status
Simulation time 58517976 ps
CPU time 0.64 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:13 PM PDT 24
Peak memory 197632 kb
Host smart-d80e585f-0de9-44e8-8cd8-200059ba7a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947112656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.2947112656
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.2865648390
Short name T857
Test name
Test status
Simulation time 57803760 ps
CPU time 0.65 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:13 PM PDT 24
Peak memory 197604 kb
Host smart-e4d4adb5-1bfc-4301-ab3e-357a49b14099
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865648390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.2865648390
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.2989668663
Short name T541
Test name
Test status
Simulation time 49502423 ps
CPU time 0.67 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:13 PM PDT 24
Peak memory 200872 kb
Host smart-09cc3456-b50d-4d36-85ae-4522e20f0cd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989668663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.2989668663
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.1782675357
Short name T819
Test name
Test status
Simulation time 184603370 ps
CPU time 1.07 seconds
Started May 23 03:38:11 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 197984 kb
Host smart-7ae3a6f1-e974-465f-85b6-11b931d0d6e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782675357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_w
akeup_race.1782675357
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.3172314775
Short name T423
Test name
Test status
Simulation time 95790762 ps
CPU time 0.76 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 197952 kb
Host smart-bfc76a70-ff1a-4ea8-8e05-8fb1b9f3a77b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172314775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.3172314775
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.507434186
Short name T261
Test name
Test status
Simulation time 162014589 ps
CPU time 0.81 seconds
Started May 23 03:38:09 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 208904 kb
Host smart-7ca68032-40c7-4a5e-9b69-0aa92b050032
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507434186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.507434186
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.3256941826
Short name T340
Test name
Test status
Simulation time 72324191 ps
CPU time 0.82 seconds
Started May 23 03:38:09 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 198596 kb
Host smart-ba878247-cd7c-409d-841e-ae0e3dee96d7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256941826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_
cm_ctrl_config_regwen.3256941826
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1526141388
Short name T326
Test name
Test status
Simulation time 1564181632 ps
CPU time 2.19 seconds
Started May 23 03:38:05 PM PDT 24
Finished May 23 03:38:11 PM PDT 24
Peak memory 200536 kb
Host smart-a4c72958-7974-422e-92ec-96a9e335b949
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526141388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1526141388
Directory /workspace/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1768685532
Short name T302
Test name
Test status
Simulation time 870587891 ps
CPU time 3.24 seconds
Started May 23 03:38:07 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 200616 kb
Host smart-1f9fb5f5-f15a-4d19-86e0-2b31d8d452ae
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768685532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1768685532
Directory /workspace/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.1754455951
Short name T442
Test name
Test status
Simulation time 51846719 ps
CPU time 0.9 seconds
Started May 23 03:38:05 PM PDT 24
Finished May 23 03:38:11 PM PDT 24
Peak memory 198732 kb
Host smart-f4f444a2-91c3-4afb-8038-d5b18f507edd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754455951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1754455951
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.37981215
Short name T542
Test name
Test status
Simulation time 30432014 ps
CPU time 0.68 seconds
Started May 23 03:38:09 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 198044 kb
Host smart-2148b4ab-29ed-430a-96d3-b699f7f91345
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37981215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.37981215
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all.922901585
Short name T539
Test name
Test status
Simulation time 2589737142 ps
CPU time 2.86 seconds
Started May 23 03:38:09 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 200728 kb
Host smart-97cc8644-161b-483a-8e90-cb6b28130bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922901585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.922901585
Directory /workspace/39.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all_with_rand_reset.2311425059
Short name T754
Test name
Test status
Simulation time 5140991341 ps
CPU time 18.3 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 200916 kb
Host smart-340ea2de-98b6-49b7-af97-28467ed4f7ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311425059 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all_with_rand_reset.2311425059
Directory /workspace/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup.2716500652
Short name T884
Test name
Test status
Simulation time 238731852 ps
CPU time 1.26 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 199228 kb
Host smart-d366cbcc-61c1-4641-bc6a-795b14ca8fe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716500652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.2716500652
Directory /workspace/39.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup_reset.3464540861
Short name T837
Test name
Test status
Simulation time 108194283 ps
CPU time 0.92 seconds
Started May 23 03:38:05 PM PDT 24
Finished May 23 03:38:11 PM PDT 24
Peak memory 198892 kb
Host smart-1964d243-1d8e-47d4-8a49-6ffe2e3bf114
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464540861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.3464540861
Directory /workspace/39.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.1647157781
Short name T947
Test name
Test status
Simulation time 58290851 ps
CPU time 0.95 seconds
Started May 23 03:36:04 PM PDT 24
Finished May 23 03:36:09 PM PDT 24
Peak memory 199856 kb
Host smart-b36dbe3a-95d8-4c73-a427-86c7b23e1a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647157781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.1647157781
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.606300224
Short name T499
Test name
Test status
Simulation time 61372317 ps
CPU time 0.85 seconds
Started May 23 03:36:13 PM PDT 24
Finished May 23 03:36:21 PM PDT 24
Peak memory 198648 kb
Host smart-62aa31f1-2fde-4ff5-8e09-182827394cf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606300224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disab
le_rom_integrity_check.606300224
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.453835583
Short name T413
Test name
Test status
Simulation time 58684513 ps
CPU time 0.56 seconds
Started May 23 03:36:15 PM PDT 24
Finished May 23 03:36:23 PM PDT 24
Peak memory 197512 kb
Host smart-0b98002d-38e2-4c85-9b6f-c883327b2936
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453835583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_m
alfunc.453835583
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.1216634393
Short name T282
Test name
Test status
Simulation time 600339758 ps
CPU time 0.95 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:17 PM PDT 24
Peak memory 197636 kb
Host smart-2c3f8d6a-5860-4393-9662-20a65e743b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216634393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.1216634393
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.397614837
Short name T856
Test name
Test status
Simulation time 71723559 ps
CPU time 0.66 seconds
Started May 23 03:36:14 PM PDT 24
Finished May 23 03:36:22 PM PDT 24
Peak memory 197576 kb
Host smart-0952bedf-a711-4ccf-ba11-04c0c44f2980
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397614837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.397614837
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.642273915
Short name T518
Test name
Test status
Simulation time 54175395 ps
CPU time 0.57 seconds
Started May 23 03:36:14 PM PDT 24
Finished May 23 03:36:22 PM PDT 24
Peak memory 197576 kb
Host smart-63793958-046c-4760-a27d-8e6bb60b35c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642273915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.642273915
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.1234189459
Short name T299
Test name
Test status
Simulation time 129900498 ps
CPU time 0.69 seconds
Started May 23 03:36:14 PM PDT 24
Finished May 23 03:36:22 PM PDT 24
Peak memory 200872 kb
Host smart-238f0119-c032-41f3-992a-55b4f5decfcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234189459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.1234189459
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.3144466671
Short name T387
Test name
Test status
Simulation time 220620650 ps
CPU time 0.75 seconds
Started May 23 03:36:13 PM PDT 24
Finished May 23 03:36:20 PM PDT 24
Peak memory 198096 kb
Host smart-43e924fc-0dd4-4aa7-a1b6-b9d660417f31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144466671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa
keup_race.3144466671
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.1319764109
Short name T848
Test name
Test status
Simulation time 42160235 ps
CPU time 0.68 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 197884 kb
Host smart-85280f30-9441-42a8-9bdd-a39678a6acdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319764109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.1319764109
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.316862791
Short name T362
Test name
Test status
Simulation time 123199432 ps
CPU time 0.89 seconds
Started May 23 03:36:13 PM PDT 24
Finished May 23 03:36:21 PM PDT 24
Peak memory 208980 kb
Host smart-c63e2942-7674-4bcc-8cc1-0e865afe82dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316862791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.316862791
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.2271700992
Short name T26
Test name
Test status
Simulation time 624049092 ps
CPU time 2.14 seconds
Started May 23 03:36:17 PM PDT 24
Finished May 23 03:36:26 PM PDT 24
Peak memory 217420 kb
Host smart-b6bcee1d-263e-4b51-a80a-3fd7124027ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271700992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2271700992
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.1268496816
Short name T43
Test name
Test status
Simulation time 277766091 ps
CPU time 0.91 seconds
Started May 23 03:36:16 PM PDT 24
Finished May 23 03:36:24 PM PDT 24
Peak memory 199596 kb
Host smart-e4f71fb3-3cf2-4a8d-baea-5ed2d27ae1a0
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268496816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_c
m_ctrl_config_regwen.1268496816
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2583217546
Short name T850
Test name
Test status
Simulation time 844007691 ps
CPU time 3.12 seconds
Started May 23 03:36:18 PM PDT 24
Finished May 23 03:36:28 PM PDT 24
Peak memory 200584 kb
Host smart-7f673be8-dcc2-45a0-813c-b9c94109b5ee
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583217546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2583217546
Directory /workspace/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.460418191
Short name T937
Test name
Test status
Simulation time 1807925462 ps
CPU time 1.9 seconds
Started May 23 03:36:18 PM PDT 24
Finished May 23 03:36:27 PM PDT 24
Peak memory 200580 kb
Host smart-ab26bc9a-8626-4fa3-83b0-b0016cd2c27e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460418191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.460418191
Directory /workspace/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1961284545
Short name T341
Test name
Test status
Simulation time 67364328 ps
CPU time 0.86 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:17 PM PDT 24
Peak memory 198860 kb
Host smart-c94fc74f-a753-41f5-b3fe-a0a145295822
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961284545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1961284545
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.1625181360
Short name T342
Test name
Test status
Simulation time 39092775 ps
CPU time 0.66 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 198064 kb
Host smart-377bb20d-ea2d-4eae-97b0-53134cb0c0b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625181360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.1625181360
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all.1897452480
Short name T796
Test name
Test status
Simulation time 1694555542 ps
CPU time 4.57 seconds
Started May 23 03:36:12 PM PDT 24
Finished May 23 03:36:23 PM PDT 24
Peak memory 200620 kb
Host smart-f6b51db4-45e1-430b-a73d-ee716d0b92a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897452480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.1897452480
Directory /workspace/4.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all_with_rand_reset.1621226900
Short name T230
Test name
Test status
Simulation time 18183498180 ps
CPU time 26.53 seconds
Started May 23 03:36:14 PM PDT 24
Finished May 23 03:36:47 PM PDT 24
Peak memory 200868 kb
Host smart-ff0f0232-d90f-40ad-bec1-08e14c8f7a46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621226900 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all_with_rand_reset.1621226900
Directory /workspace/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup.1384028864
Short name T778
Test name
Test status
Simulation time 201369094 ps
CPU time 1.08 seconds
Started May 23 03:36:10 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 200116 kb
Host smart-9b645cf4-f04a-4466-a5a1-74ac9c8bc3ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384028864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.1384028864
Directory /workspace/4.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.4277317570
Short name T744
Test name
Test status
Simulation time 52831999 ps
CPU time 0.8 seconds
Started May 23 03:36:16 PM PDT 24
Finished May 23 03:36:24 PM PDT 24
Peak memory 198800 kb
Host smart-44a82847-0c54-489f-8bac-d1016e71b6b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277317570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.4277317570
Directory /workspace/4.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.1464236401
Short name T1005
Test name
Test status
Simulation time 37767393 ps
CPU time 0.74 seconds
Started May 23 03:38:06 PM PDT 24
Finished May 23 03:38:11 PM PDT 24
Peak memory 198656 kb
Host smart-f693f0cc-c1b8-4429-b9f4-887405dc5238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464236401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1464236401
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.525866333
Short name T847
Test name
Test status
Simulation time 84706370 ps
CPU time 0.7 seconds
Started May 23 03:38:06 PM PDT 24
Finished May 23 03:38:11 PM PDT 24
Peak memory 198068 kb
Host smart-c135df36-a320-48b7-8a56-36d5f000c66c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525866333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disa
ble_rom_integrity_check.525866333
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.3666316270
Short name T131
Test name
Test status
Simulation time 39608941 ps
CPU time 0.59 seconds
Started May 23 03:38:09 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 196840 kb
Host smart-54af7b4b-5691-46d0-b3d2-bcfc44e3d783
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666316270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.3666316270
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.1364065837
Short name T332
Test name
Test status
Simulation time 163350373 ps
CPU time 1.03 seconds
Started May 23 03:38:07 PM PDT 24
Finished May 23 03:38:13 PM PDT 24
Peak memory 197628 kb
Host smart-3b01ae3d-ec43-487e-98cb-a5712fac6f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364065837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.1364065837
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.1321564351
Short name T598
Test name
Test status
Simulation time 52853175 ps
CPU time 0.63 seconds
Started May 23 03:38:05 PM PDT 24
Finished May 23 03:38:10 PM PDT 24
Peak memory 197568 kb
Host smart-6987d48c-0dce-4d47-868f-74e796a5492d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321564351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.1321564351
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.3183410968
Short name T313
Test name
Test status
Simulation time 41586080 ps
CPU time 0.62 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:14 PM PDT 24
Peak memory 197568 kb
Host smart-1898a3f1-fcb0-4676-82e4-dee43183c518
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183410968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.3183410968
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.4266604044
Short name T568
Test name
Test status
Simulation time 70603933 ps
CPU time 0.67 seconds
Started May 23 03:38:04 PM PDT 24
Finished May 23 03:38:09 PM PDT 24
Peak memory 200816 kb
Host smart-ef6860e1-0684-47d2-8a11-c00a939fdf61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266604044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.4266604044
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.1844795489
Short name T389
Test name
Test status
Simulation time 140386651 ps
CPU time 0.95 seconds
Started May 23 03:38:18 PM PDT 24
Finished May 23 03:38:22 PM PDT 24
Peak memory 198672 kb
Host smart-73a72353-ff49-4f9e-9c00-c664bb670f36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844795489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_w
akeup_race.1844795489
Directory /workspace/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.2297893197
Short name T684
Test name
Test status
Simulation time 28837038 ps
CPU time 0.64 seconds
Started May 23 03:38:07 PM PDT 24
Finished May 23 03:38:12 PM PDT 24
Peak memory 198640 kb
Host smart-dd2407b3-f50f-4778-8b58-ad407d338a30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297893197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.2297893197
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.3529449626
Short name T933
Test name
Test status
Simulation time 162379420 ps
CPU time 0.78 seconds
Started May 23 03:38:11 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 208936 kb
Host smart-ade13bf8-8a93-48df-8ded-f96fe0baf172
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529449626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.3529449626
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.2559858730
Short name T710
Test name
Test status
Simulation time 175163327 ps
CPU time 0.81 seconds
Started May 23 03:38:07 PM PDT 24
Finished May 23 03:38:12 PM PDT 24
Peak memory 199476 kb
Host smart-45d2fc5e-8d83-4cb5-8a5f-a4dba10c6532
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559858730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_
cm_ctrl_config_regwen.2559858730
Directory /workspace/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.490562420
Short name T231
Test name
Test status
Simulation time 764103719 ps
CPU time 2.9 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:19 PM PDT 24
Peak memory 200656 kb
Host smart-ff6ebf5c-d807-465b-9fc0-7a608dccdd6e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490562420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.490562420
Directory /workspace/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1795961777
Short name T572
Test name
Test status
Simulation time 1051535311 ps
CPU time 2.64 seconds
Started May 23 03:38:06 PM PDT 24
Finished May 23 03:38:13 PM PDT 24
Peak memory 200604 kb
Host smart-3e33aa62-8345-4602-87c9-84f7f25a77d0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795961777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1795961777
Directory /workspace/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1207613045
Short name T613
Test name
Test status
Simulation time 74204116 ps
CPU time 0.94 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:16 PM PDT 24
Peak memory 198908 kb
Host smart-1f2fe8bc-181c-45f9-9cd8-3c11c429acae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207613045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1207613045
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.419548974
Short name T885
Test name
Test status
Simulation time 107534948 ps
CPU time 0.64 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:14 PM PDT 24
Peak memory 198036 kb
Host smart-ff095e5f-d8a8-4aaa-a3b6-2790efb532df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419548974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.419548974
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all.177381771
Short name T376
Test name
Test status
Simulation time 892186578 ps
CPU time 2.01 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:14 PM PDT 24
Peak memory 200684 kb
Host smart-da09343a-005d-4786-a969-c43c4a7319fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177381771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.177381771
Directory /workspace/40.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all_with_rand_reset.1262933917
Short name T290
Test name
Test status
Simulation time 8183619522 ps
CPU time 5.8 seconds
Started May 23 03:38:07 PM PDT 24
Finished May 23 03:38:18 PM PDT 24
Peak memory 200872 kb
Host smart-67cfdbd4-e214-480b-8823-3423ff06effa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262933917 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all_with_rand_reset.1262933917
Directory /workspace/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup.2767024160
Short name T910
Test name
Test status
Simulation time 206807075 ps
CPU time 1.15 seconds
Started May 23 03:38:06 PM PDT 24
Finished May 23 03:38:11 PM PDT 24
Peak memory 199280 kb
Host smart-5db3433f-ab45-412a-b0be-04295e28abee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767024160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.2767024160
Directory /workspace/40.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup_reset.3409115512
Short name T480
Test name
Test status
Simulation time 251357455 ps
CPU time 1.42 seconds
Started May 23 03:38:04 PM PDT 24
Finished May 23 03:38:10 PM PDT 24
Peak memory 199852 kb
Host smart-7646994c-8a6a-4106-91f0-997cc9afcc73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409115512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.3409115512
Directory /workspace/40.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.1938737824
Short name T95
Test name
Test status
Simulation time 67106377 ps
CPU time 0.9 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:13 PM PDT 24
Peak memory 200356 kb
Host smart-e9c94888-77f3-4056-835d-76fc6586b1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938737824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.1938737824
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.819690070
Short name T874
Test name
Test status
Simulation time 116389845 ps
CPU time 0.68 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:13 PM PDT 24
Peak memory 198644 kb
Host smart-4aed41ba-6448-446a-a678-8d78686c058c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819690070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disa
ble_rom_integrity_check.819690070
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.525696667
Short name T233
Test name
Test status
Simulation time 31168049 ps
CPU time 0.63 seconds
Started May 23 03:38:07 PM PDT 24
Finished May 23 03:38:12 PM PDT 24
Peak memory 196848 kb
Host smart-f106d49b-d9bb-4adb-8312-0acea59bd9b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525696667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_
malfunc.525696667
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.37811675
Short name T133
Test name
Test status
Simulation time 311055947 ps
CPU time 0.94 seconds
Started May 23 03:38:09 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 197624 kb
Host smart-cfc8ab33-5420-4b8e-a8d8-b6f13d293622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37811675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.37811675
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.1955319558
Short name T487
Test name
Test status
Simulation time 38911839 ps
CPU time 0.58 seconds
Started May 23 03:38:07 PM PDT 24
Finished May 23 03:38:12 PM PDT 24
Peak memory 196872 kb
Host smart-e08baf3a-7b60-4832-b062-8bb8a6b96922
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955319558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.1955319558
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.3255980066
Short name T867
Test name
Test status
Simulation time 21157745 ps
CPU time 0.62 seconds
Started May 23 03:38:06 PM PDT 24
Finished May 23 03:38:11 PM PDT 24
Peak memory 197924 kb
Host smart-33f849dd-24f8-445b-8f31-c998fbbbc123
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255980066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.3255980066
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.3193507887
Short name T205
Test name
Test status
Simulation time 72588111 ps
CPU time 0.67 seconds
Started May 23 03:38:07 PM PDT 24
Finished May 23 03:38:13 PM PDT 24
Peak memory 200884 kb
Host smart-db27d6a3-544f-40e8-b3d2-d26a89c20534
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193507887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.3193507887
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.1838214215
Short name T547
Test name
Test status
Simulation time 316234637 ps
CPU time 0.92 seconds
Started May 23 03:38:09 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 199156 kb
Host smart-9964b000-1137-488c-9d32-44f366a3f047
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838214215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_w
akeup_race.1838214215
Directory /workspace/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.3262217507
Short name T174
Test name
Test status
Simulation time 79102922 ps
CPU time 1.04 seconds
Started May 23 03:38:05 PM PDT 24
Finished May 23 03:38:11 PM PDT 24
Peak memory 199220 kb
Host smart-c8b96a6e-701d-4930-b9b4-e24b0bc01921
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262217507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.3262217507
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1795946480
Short name T649
Test name
Test status
Simulation time 114180487 ps
CPU time 0.91 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:16 PM PDT 24
Peak memory 208960 kb
Host smart-51d337f4-e02f-4006-935e-27fe5c61ea99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795946480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1795946480
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.3856760447
Short name T899
Test name
Test status
Simulation time 142416897 ps
CPU time 0.9 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 199296 kb
Host smart-c0aa86e4-9804-4fa6-9e5d-ea296a177cae
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856760447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_
cm_ctrl_config_regwen.3856760447
Directory /workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2527284190
Short name T23
Test name
Test status
Simulation time 1283631552 ps
CPU time 2.02 seconds
Started May 23 03:38:11 PM PDT 24
Finished May 23 03:38:19 PM PDT 24
Peak memory 200584 kb
Host smart-40979c46-7193-4d91-a4df-67cff3b412cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527284190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2527284190
Directory /workspace/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3981176187
Short name T704
Test name
Test status
Simulation time 1421682046 ps
CPU time 2.36 seconds
Started May 23 03:38:09 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 200568 kb
Host smart-44f6e960-378c-4ee6-aa19-3b1e116f085c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981176187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3981176187
Directory /workspace/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.1017516526
Short name T801
Test name
Test status
Simulation time 219109622 ps
CPU time 0.83 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:14 PM PDT 24
Peak memory 198952 kb
Host smart-bec34f0c-5f0c-4e4b-9b23-1a6bdbee5e6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017516526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1017516526
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.2656614290
Short name T624
Test name
Test status
Simulation time 40741717 ps
CPU time 0.66 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:13 PM PDT 24
Peak memory 198080 kb
Host smart-93cc1d36-0e8e-418c-8762-f6476055372d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656614290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.2656614290
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all.280821466
Short name T454
Test name
Test status
Simulation time 281226475 ps
CPU time 1.39 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:14 PM PDT 24
Peak memory 200176 kb
Host smart-8b7c19c2-7d6a-4ae7-8917-3394eadc3820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280821466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.280821466
Directory /workspace/41.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all_with_rand_reset.2365161641
Short name T119
Test name
Test status
Simulation time 9566215523 ps
CPU time 28.06 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:44 PM PDT 24
Peak memory 200876 kb
Host smart-d7200166-e6b4-4fb5-9bd9-fd7c1bd03427
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365161641 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all_with_rand_reset.2365161641
Directory /workspace/41.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup.1567664682
Short name T571
Test name
Test status
Simulation time 133325818 ps
CPU time 0.8 seconds
Started May 23 03:38:09 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 197932 kb
Host smart-428d9004-019c-47fa-9f25-03fe8b555e24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567664682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.1567664682
Directory /workspace/41.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup_reset.398406114
Short name T183
Test name
Test status
Simulation time 31258408 ps
CPU time 0.73 seconds
Started May 23 03:38:06 PM PDT 24
Finished May 23 03:38:12 PM PDT 24
Peak memory 198052 kb
Host smart-e4bdb19a-3093-46dd-a540-0990665f6340
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398406114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.398406114
Directory /workspace/41.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.517633857
Short name T355
Test name
Test status
Simulation time 42372633 ps
CPU time 0.9 seconds
Started May 23 03:38:12 PM PDT 24
Finished May 23 03:38:19 PM PDT 24
Peak memory 199668 kb
Host smart-f0b30e6d-83d8-4eed-8d08-69667c95c070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517633857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.517633857
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.3845247845
Short name T267
Test name
Test status
Simulation time 63461800 ps
CPU time 0.81 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:14 PM PDT 24
Peak memory 198208 kb
Host smart-e8b5b491-2f8d-41ab-8b3f-81aec1653dbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845247845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.3845247845
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.4165263711
Short name T318
Test name
Test status
Simulation time 29897195 ps
CPU time 0.62 seconds
Started May 23 03:38:09 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 196844 kb
Host smart-9eda7ecb-8a79-43ae-b45c-2579bc95cc35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165263711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.4165263711
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.81719468
Short name T688
Test name
Test status
Simulation time 1144234643 ps
CPU time 0.95 seconds
Started May 23 03:38:12 PM PDT 24
Finished May 23 03:38:19 PM PDT 24
Peak memory 197608 kb
Host smart-7ca86f4e-b341-4773-a1b1-36d3aa13c7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81719468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.81719468
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.428452133
Short name T256
Test name
Test status
Simulation time 56465860 ps
CPU time 0.61 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:14 PM PDT 24
Peak memory 196856 kb
Host smart-ffac2272-76c1-4337-9584-ad4199a3244f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428452133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.428452133
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.2128869662
Short name T498
Test name
Test status
Simulation time 48166992 ps
CPU time 0.6 seconds
Started May 23 03:38:12 PM PDT 24
Finished May 23 03:38:18 PM PDT 24
Peak memory 197588 kb
Host smart-2aa94779-0586-4c60-b5b3-5103d5c293ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128869662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.2128869662
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.3120915970
Short name T237
Test name
Test status
Simulation time 41834796 ps
CPU time 0.77 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:13 PM PDT 24
Peak memory 200840 kb
Host smart-a1c0e452-e7a2-497f-9f7c-2f128ef59650
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120915970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.3120915970
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.3998566782
Short name T681
Test name
Test status
Simulation time 392723333 ps
CPU time 1.02 seconds
Started May 23 03:38:09 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 199100 kb
Host smart-70342091-086d-4784-88cc-1a9b2f4bfad7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998566782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_w
akeup_race.3998566782
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.3932249101
Short name T353
Test name
Test status
Simulation time 71099547 ps
CPU time 0.9 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:16 PM PDT 24
Peak memory 198304 kb
Host smart-578432c0-191c-4fe7-bd66-360c87b67320
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932249101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.3932249101
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.1958275532
Short name T573
Test name
Test status
Simulation time 159866366 ps
CPU time 0.79 seconds
Started May 23 03:38:18 PM PDT 24
Finished May 23 03:38:21 PM PDT 24
Peak memory 208908 kb
Host smart-25363aba-8dfd-409d-b377-7cfded595af4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958275532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.1958275532
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.1335789149
Short name T799
Test name
Test status
Simulation time 257396331 ps
CPU time 1.32 seconds
Started May 23 03:38:13 PM PDT 24
Finished May 23 03:38:20 PM PDT 24
Peak memory 200480 kb
Host smart-e079858f-28ae-4620-8d87-be690055bbc7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335789149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_
cm_ctrl_config_regwen.1335789149
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.802571949
Short name T961
Test name
Test status
Simulation time 895597512 ps
CPU time 2.96 seconds
Started May 23 03:38:19 PM PDT 24
Finished May 23 03:38:24 PM PDT 24
Peak memory 200332 kb
Host smart-62a33682-3b59-4195-8a4d-bdc2d31c3b7b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802571949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.802571949
Directory /workspace/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3802857504
Short name T722
Test name
Test status
Simulation time 991382839 ps
CPU time 2.42 seconds
Started May 23 03:38:12 PM PDT 24
Finished May 23 03:38:20 PM PDT 24
Peak memory 200652 kb
Host smart-1c259186-e262-4ee1-94ba-50c71fe72edd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802857504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3802857504
Directory /workspace/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.187306106
Short name T501
Test name
Test status
Simulation time 63888846 ps
CPU time 0.83 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 198860 kb
Host smart-04c6ed9c-21b6-49b7-a0ec-d2d3ae8050f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187306106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_
mubi.187306106
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.508507094
Short name T811
Test name
Test status
Simulation time 53159520 ps
CPU time 0.65 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 198900 kb
Host smart-b52d6491-8935-454b-8992-50910eaad6c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508507094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.508507094
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all.3031248035
Short name T489
Test name
Test status
Simulation time 942253897 ps
CPU time 3.19 seconds
Started May 23 03:38:13 PM PDT 24
Finished May 23 03:38:22 PM PDT 24
Peak memory 200672 kb
Host smart-74c40182-29bc-440d-a4f1-3f6116b40c0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031248035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.3031248035
Directory /workspace/42.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all_with_rand_reset.2750460384
Short name T789
Test name
Test status
Simulation time 12808740355 ps
CPU time 12.9 seconds
Started May 23 03:38:13 PM PDT 24
Finished May 23 03:38:31 PM PDT 24
Peak memory 200852 kb
Host smart-56366869-3d6f-4bcc-9aa5-3d3852c9ac66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750460384 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all_with_rand_reset.2750460384
Directory /workspace/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup.3918802717
Short name T614
Test name
Test status
Simulation time 51616052 ps
CPU time 0.68 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:16 PM PDT 24
Peak memory 198036 kb
Host smart-29bca19a-45e0-4314-8d1e-bd53ce599ac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918802717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.3918802717
Directory /workspace/42.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup_reset.3659114640
Short name T452
Test name
Test status
Simulation time 175372784 ps
CPU time 1.1 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:14 PM PDT 24
Peak memory 199552 kb
Host smart-0566c976-cb4c-4882-bc3e-fd411815bfad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659114640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.3659114640
Directory /workspace/42.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.855762780
Short name T765
Test name
Test status
Simulation time 70434194 ps
CPU time 0.7 seconds
Started May 23 03:38:21 PM PDT 24
Finished May 23 03:38:25 PM PDT 24
Peak memory 198220 kb
Host smart-4d52122f-ef55-4242-9e1d-16a1c2c274de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855762780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.855762780
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.939186653
Short name T141
Test name
Test status
Simulation time 56772910 ps
CPU time 0.85 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:14 PM PDT 24
Peak memory 198700 kb
Host smart-b2d82461-ebf1-4f26-a308-77ffd7989a96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939186653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disa
ble_rom_integrity_check.939186653
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3070777381
Short name T951
Test name
Test status
Simulation time 38456465 ps
CPU time 0.59 seconds
Started May 23 03:38:18 PM PDT 24
Finished May 23 03:38:26 PM PDT 24
Peak memory 197564 kb
Host smart-f97ab08a-2270-40b6-b78f-be2dac543528
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070777381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.3070777381
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.1333967753
Short name T315
Test name
Test status
Simulation time 164787649 ps
CPU time 0.97 seconds
Started May 23 03:38:11 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 197644 kb
Host smart-d3c8db14-42b3-4805-8aa5-b5c62bb97f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333967753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.1333967753
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.2885201526
Short name T1
Test name
Test status
Simulation time 52047963 ps
CPU time 0.61 seconds
Started May 23 03:38:16 PM PDT 24
Finished May 23 03:38:20 PM PDT 24
Peak memory 196464 kb
Host smart-96616605-2c8e-46d8-b412-9d6327ed7157
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885201526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.2885201526
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.3506764663
Short name T764
Test name
Test status
Simulation time 45154918 ps
CPU time 0.61 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:14 PM PDT 24
Peak memory 197636 kb
Host smart-872343cf-fb39-4e01-9693-13465dae751b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506764663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.3506764663
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.3162192288
Short name T456
Test name
Test status
Simulation time 42888704 ps
CPU time 0.71 seconds
Started May 23 03:38:11 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 200296 kb
Host smart-89613b23-0b4d-4d33-9ab7-d28d76f0fdfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162192288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.3162192288
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.4057817648
Short name T250
Test name
Test status
Simulation time 331139999 ps
CPU time 0.95 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 199272 kb
Host smart-ab14daad-6ef5-4ded-8983-eb918702258c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057817648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_w
akeup_race.4057817648
Directory /workspace/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.460636535
Short name T173
Test name
Test status
Simulation time 54121108 ps
CPU time 0.62 seconds
Started May 23 03:38:13 PM PDT 24
Finished May 23 03:38:19 PM PDT 24
Peak memory 197844 kb
Host smart-af0b24aa-b7e0-472a-a4a1-288558248659
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460636535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.460636535
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.1506461655
Short name T888
Test name
Test status
Simulation time 173413819 ps
CPU time 0.78 seconds
Started May 23 03:38:09 PM PDT 24
Finished May 23 03:38:15 PM PDT 24
Peak memory 208972 kb
Host smart-96860c72-850b-4d71-be35-1b0e2a704287
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506461655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.1506461655
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.991364352
Short name T396
Test name
Test status
Simulation time 252072062 ps
CPU time 1.22 seconds
Started May 23 03:38:18 PM PDT 24
Finished May 23 03:38:22 PM PDT 24
Peak memory 199536 kb
Host smart-aa74964c-447c-48a0-ba2f-4ef1aba2d2e8
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991364352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_c
m_ctrl_config_regwen.991364352
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3075343049
Short name T145
Test name
Test status
Simulation time 779088401 ps
CPU time 2.91 seconds
Started May 23 03:38:08 PM PDT 24
Finished May 23 03:38:16 PM PDT 24
Peak memory 200624 kb
Host smart-3126e3b0-aefe-4c63-a8d7-93c8adb767fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075343049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3075343049
Directory /workspace/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.630582151
Short name T465
Test name
Test status
Simulation time 1665888575 ps
CPU time 2.16 seconds
Started May 23 03:38:16 PM PDT 24
Finished May 23 03:38:22 PM PDT 24
Peak memory 200172 kb
Host smart-972a3603-8689-489f-b37c-0fefe06459dc
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630582151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.630582151
Directory /workspace/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.41602351
Short name T806
Test name
Test status
Simulation time 129701531 ps
CPU time 0.85 seconds
Started May 23 03:38:17 PM PDT 24
Finished May 23 03:38:21 PM PDT 24
Peak memory 198664 kb
Host smart-9a97d475-6ede-4df1-9f58-58037b3b2358
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41602351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.41602351
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.2865031464
Short name T384
Test name
Test status
Simulation time 47597302 ps
CPU time 0.62 seconds
Started May 23 03:38:13 PM PDT 24
Finished May 23 03:38:19 PM PDT 24
Peak memory 198072 kb
Host smart-b0b3aa7f-48a8-4621-9dbd-e6d4b1025081
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865031464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.2865031464
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all.2774416240
Short name T816
Test name
Test status
Simulation time 2523560076 ps
CPU time 5.37 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:21 PM PDT 24
Peak memory 200740 kb
Host smart-da295b4f-f84f-43e3-a0b0-6f8ddd4742fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774416240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.2774416240
Directory /workspace/43.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all_with_rand_reset.121492666
Short name T753
Test name
Test status
Simulation time 12971675419 ps
CPU time 24.87 seconds
Started May 23 03:38:11 PM PDT 24
Finished May 23 03:38:41 PM PDT 24
Peak memory 200364 kb
Host smart-c606deec-0f3a-43c8-9aea-18748b5ea54b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121492666 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all_with_rand_reset.121492666
Directory /workspace/43.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup.3736672857
Short name T460
Test name
Test status
Simulation time 197127471 ps
CPU time 1.06 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:16 PM PDT 24
Peak memory 199136 kb
Host smart-b1a1d552-7978-4a85-8c87-5fc701d748db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736672857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.3736672857
Directory /workspace/43.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.1286413866
Short name T808
Test name
Test status
Simulation time 105849152 ps
CPU time 0.77 seconds
Started May 23 03:38:11 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 198836 kb
Host smart-63a0324a-9639-4857-9e25-edec2199790d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286413866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.1286413866
Directory /workspace/43.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.1662129968
Short name T897
Test name
Test status
Simulation time 95649617 ps
CPU time 0.77 seconds
Started May 23 03:38:38 PM PDT 24
Finished May 23 03:38:44 PM PDT 24
Peak memory 199436 kb
Host smart-2c8e8b45-43f9-40b7-b68d-cdd401dec531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662129968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.1662129968
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.2372105685
Short name T402
Test name
Test status
Simulation time 83566185 ps
CPU time 0.68 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:33 PM PDT 24
Peak memory 198660 kb
Host smart-b95412b1-c834-44ee-bd4e-9fb711a9dd36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372105685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.2372105685
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.456159738
Short name T798
Test name
Test status
Simulation time 29766710 ps
CPU time 0.64 seconds
Started May 23 03:38:34 PM PDT 24
Finished May 23 03:38:41 PM PDT 24
Peak memory 196800 kb
Host smart-f9a0482e-554d-4c3f-a937-4f33093921d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456159738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_
malfunc.456159738
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.1224828560
Short name T718
Test name
Test status
Simulation time 1061401562 ps
CPU time 0.93 seconds
Started May 23 03:38:29 PM PDT 24
Finished May 23 03:38:36 PM PDT 24
Peak memory 197644 kb
Host smart-15b70e6d-2184-4c76-ba70-b5a46a7d75ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224828560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.1224828560
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.159764152
Short name T841
Test name
Test status
Simulation time 46908978 ps
CPU time 0.67 seconds
Started May 23 03:38:35 PM PDT 24
Finished May 23 03:38:42 PM PDT 24
Peak memory 197624 kb
Host smart-24f8e904-ab6f-4605-a343-a6694af0c1e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159764152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.159764152
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.1655512064
Short name T783
Test name
Test status
Simulation time 24022418 ps
CPU time 0.6 seconds
Started May 23 03:38:31 PM PDT 24
Finished May 23 03:38:39 PM PDT 24
Peak memory 197888 kb
Host smart-3b8185ca-50dc-42a5-936d-2b8b9eb0691a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655512064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.1655512064
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.2263961716
Short name T278
Test name
Test status
Simulation time 43983392 ps
CPU time 0.7 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 200808 kb
Host smart-8cb95e8a-3080-4844-8c4d-7aebd310925e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263961716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.2263961716
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_wakeup_race.2935173834
Short name T420
Test name
Test status
Simulation time 202106876 ps
CPU time 1 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 199144 kb
Host smart-88586bf5-e0f5-4824-8292-9d1688fb13f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935173834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_w
akeup_race.2935173834
Directory /workspace/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.4268392708
Short name T735
Test name
Test status
Simulation time 36252880 ps
CPU time 0.6 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 197804 kb
Host smart-4782365c-f67f-48fb-87c0-17bf06b8b00f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268392708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.4268392708
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.4091325418
Short name T252
Test name
Test status
Simulation time 156378356 ps
CPU time 0.83 seconds
Started May 23 03:38:24 PM PDT 24
Finished May 23 03:38:27 PM PDT 24
Peak memory 208972 kb
Host smart-ff1c5778-0f59-4391-926c-041f22db88d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091325418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.4091325418
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.343727145
Short name T560
Test name
Test status
Simulation time 53349340 ps
CPU time 0.71 seconds
Started May 23 03:38:29 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 198624 kb
Host smart-9684dcc8-1864-46d9-835d-8cbf077f8ad1
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343727145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_c
m_ctrl_config_regwen.343727145
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1911070287
Short name T554
Test name
Test status
Simulation time 1315169163 ps
CPU time 2.1 seconds
Started May 23 03:38:19 PM PDT 24
Finished May 23 03:38:24 PM PDT 24
Peak memory 200432 kb
Host smart-260cb4c7-44bc-40af-9dcf-82e4c680ec8a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911070287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1911070287
Directory /workspace/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1223950455
Short name T607
Test name
Test status
Simulation time 874939562 ps
CPU time 3.15 seconds
Started May 23 03:38:20 PM PDT 24
Finished May 23 03:38:26 PM PDT 24
Peak memory 200584 kb
Host smart-30e177bb-8ade-45c0-94f7-ed7a2c5d801a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223950455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1223950455
Directory /workspace/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1048089976
Short name T253
Test name
Test status
Simulation time 109122219 ps
CPU time 0.81 seconds
Started May 23 03:38:24 PM PDT 24
Finished May 23 03:38:27 PM PDT 24
Peak memory 198760 kb
Host smart-f8625351-8e51-4f73-9f62-6b36a5fdead8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048089976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1048089976
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1330741595
Short name T234
Test name
Test status
Simulation time 39738347 ps
CPU time 0.64 seconds
Started May 23 03:38:10 PM PDT 24
Finished May 23 03:38:16 PM PDT 24
Peak memory 198832 kb
Host smart-f8042747-f042-4899-b544-bd37e99d1ed1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330741595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1330741595
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all.445550448
Short name T632
Test name
Test status
Simulation time 41931048 ps
CPU time 0.72 seconds
Started May 23 03:38:21 PM PDT 24
Finished May 23 03:38:25 PM PDT 24
Peak memory 198852 kb
Host smart-adf139e1-556f-41e3-aec8-4f869cae386a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445550448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.445550448
Directory /workspace/44.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all_with_rand_reset.3592272183
Short name T79
Test name
Test status
Simulation time 10158856644 ps
CPU time 28.64 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:39:00 PM PDT 24
Peak memory 200920 kb
Host smart-bda270fa-4a85-46e9-98b7-2f960711ca10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592272183 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all_with_rand_reset.3592272183
Directory /workspace/44.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup.1308049518
Short name T657
Test name
Test status
Simulation time 306979590 ps
CPU time 1.32 seconds
Started May 23 03:38:27 PM PDT 24
Finished May 23 03:38:33 PM PDT 24
Peak memory 199360 kb
Host smart-ab4677fb-e7fd-4a4c-b87f-8b273cbbd2f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308049518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.1308049518
Directory /workspace/44.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup_reset.722062949
Short name T838
Test name
Test status
Simulation time 221439056 ps
CPU time 0.89 seconds
Started May 23 03:38:20 PM PDT 24
Finished May 23 03:38:24 PM PDT 24
Peak memory 199612 kb
Host smart-9028ece2-4b27-4be9-bd3f-49fba510f3a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722062949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.722062949
Directory /workspace/44.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.2043443526
Short name T887
Test name
Test status
Simulation time 109160843 ps
CPU time 0.61 seconds
Started May 23 03:38:22 PM PDT 24
Finished May 23 03:38:26 PM PDT 24
Peak memory 198076 kb
Host smart-3e753cfd-1037-42af-92b0-6fc8bac14e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043443526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.2043443526
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.2655700494
Short name T780
Test name
Test status
Simulation time 81923123 ps
CPU time 0.69 seconds
Started May 23 03:38:20 PM PDT 24
Finished May 23 03:38:23 PM PDT 24
Peak memory 198652 kb
Host smart-45ff1dc6-e9ef-49d5-8720-19a7ad02e7b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655700494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.2655700494
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2117297756
Short name T380
Test name
Test status
Simulation time 32834600 ps
CPU time 0.61 seconds
Started May 23 03:38:27 PM PDT 24
Finished May 23 03:38:32 PM PDT 24
Peak memory 196848 kb
Host smart-9ab1f90b-d6fb-4d65-8294-eb3a25c45bda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117297756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.2117297756
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.2440416398
Short name T932
Test name
Test status
Simulation time 164857441 ps
CPU time 0.95 seconds
Started May 23 03:38:19 PM PDT 24
Finished May 23 03:38:22 PM PDT 24
Peak memory 197676 kb
Host smart-7f7ef31e-d15a-46f7-9f4a-86bc3763f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440416398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.2440416398
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.1313043546
Short name T738
Test name
Test status
Simulation time 46094552 ps
CPU time 0.6 seconds
Started May 23 03:38:21 PM PDT 24
Finished May 23 03:38:24 PM PDT 24
Peak memory 196872 kb
Host smart-17d3044a-94ad-4260-911d-c5879048f671
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313043546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.1313043546
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.367205307
Short name T639
Test name
Test status
Simulation time 46130238 ps
CPU time 0.59 seconds
Started May 23 03:38:30 PM PDT 24
Finished May 23 03:38:38 PM PDT 24
Peak memory 197524 kb
Host smart-07dae130-deb9-4cf0-9db7-6d887a72d00f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367205307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.367205307
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.869949184
Short name T548
Test name
Test status
Simulation time 70996737 ps
CPU time 0.67 seconds
Started May 23 03:38:27 PM PDT 24
Finished May 23 03:38:32 PM PDT 24
Peak memory 200864 kb
Host smart-46d1647a-a975-423f-9ab9-2762de858376
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869949184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_invali
d.869949184
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_wakeup_race.1951907929
Short name T439
Test name
Test status
Simulation time 265479239 ps
CPU time 1.16 seconds
Started May 23 03:38:20 PM PDT 24
Finished May 23 03:38:24 PM PDT 24
Peak memory 199096 kb
Host smart-8cebadf4-a25d-4082-ac8d-2fde4b02c9d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951907929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_w
akeup_race.1951907929
Directory /workspace/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.2090118405
Short name T830
Test name
Test status
Simulation time 36254361 ps
CPU time 0.65 seconds
Started May 23 03:38:24 PM PDT 24
Finished May 23 03:38:27 PM PDT 24
Peak memory 198596 kb
Host smart-7a941e83-d2e9-4f85-b379-24badfc696b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090118405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2090118405
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.2120085302
Short name T676
Test name
Test status
Simulation time 98716887 ps
CPU time 1.08 seconds
Started May 23 03:38:40 PM PDT 24
Finished May 23 03:38:47 PM PDT 24
Peak memory 208948 kb
Host smart-65ebb297-b424-4669-a11b-8b3d7fbf0eb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120085302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.2120085302
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.3020954863
Short name T265
Test name
Test status
Simulation time 207081738 ps
CPU time 0.83 seconds
Started May 23 03:38:25 PM PDT 24
Finished May 23 03:38:28 PM PDT 24
Peak memory 199472 kb
Host smart-907025f9-259e-4445-9c22-6be0112604c7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020954863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_
cm_ctrl_config_regwen.3020954863
Directory /workspace/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2053839513
Short name T525
Test name
Test status
Simulation time 731118863 ps
CPU time 2.89 seconds
Started May 23 03:38:37 PM PDT 24
Finished May 23 03:38:46 PM PDT 24
Peak memory 200568 kb
Host smart-f2426b6f-c531-4681-bbb4-8e43b3f5fbaf
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053839513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2053839513
Directory /workspace/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1396802924
Short name T427
Test name
Test status
Simulation time 702560982 ps
CPU time 2.93 seconds
Started May 23 03:38:26 PM PDT 24
Finished May 23 03:38:33 PM PDT 24
Peak memory 200420 kb
Host smart-f91ca8f0-2842-476a-816d-573a52d9e482
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396802924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1396802924
Directory /workspace/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.3458757453
Short name T895
Test name
Test status
Simulation time 90467369 ps
CPU time 0.84 seconds
Started May 23 03:38:20 PM PDT 24
Finished May 23 03:38:24 PM PDT 24
Peak memory 198948 kb
Host smart-0329985b-317c-473a-835c-85c7cac56753
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458757453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3458757453
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.4195209945
Short name T468
Test name
Test status
Simulation time 57465790 ps
CPU time 0.62 seconds
Started May 23 03:38:19 PM PDT 24
Finished May 23 03:38:22 PM PDT 24
Peak memory 198852 kb
Host smart-762918d9-07ac-420f-9736-c711774cfd91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195209945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.4195209945
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all.1944784135
Short name T669
Test name
Test status
Simulation time 2448735826 ps
CPU time 4.1 seconds
Started May 23 03:38:32 PM PDT 24
Finished May 23 03:38:43 PM PDT 24
Peak memory 200752 kb
Host smart-2ad23375-ec8a-421d-8835-5e49e5bbf97e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944784135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.1944784135
Directory /workspace/45.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all_with_rand_reset.1152147351
Short name T317
Test name
Test status
Simulation time 7430857233 ps
CPU time 28.42 seconds
Started May 23 03:38:29 PM PDT 24
Finished May 23 03:39:03 PM PDT 24
Peak memory 200836 kb
Host smart-d8cb3fe2-0483-45de-af9b-52e2f9afc190
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152147351 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all_with_rand_reset.1152147351
Directory /workspace/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup.753525936
Short name T629
Test name
Test status
Simulation time 209914470 ps
CPU time 0.82 seconds
Started May 23 03:38:29 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 198988 kb
Host smart-b8aa8091-5c74-415e-9c61-c3a179081cfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753525936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.753525936
Directory /workspace/45.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup_reset.2901876072
Short name T557
Test name
Test status
Simulation time 276778345 ps
CPU time 1.34 seconds
Started May 23 03:38:27 PM PDT 24
Finished May 23 03:38:32 PM PDT 24
Peak memory 200200 kb
Host smart-0c5d9f04-80c6-4ab5-8639-00ad7d6c365b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901876072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.2901876072
Directory /workspace/45.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.2809651423
Short name T562
Test name
Test status
Simulation time 40411581 ps
CPU time 0.67 seconds
Started May 23 03:38:21 PM PDT 24
Finished May 23 03:38:25 PM PDT 24
Peak memory 198104 kb
Host smart-a366b6e2-2bcf-4173-9bb0-dc29e0f3c037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809651423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.2809651423
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.3034856157
Short name T922
Test name
Test status
Simulation time 62560464 ps
CPU time 0.76 seconds
Started May 23 03:38:29 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 197924 kb
Host smart-068893ff-c348-4585-9b28-dc07e09a4ec5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034856157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.3034856157
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3398111031
Short name T289
Test name
Test status
Simulation time 32464631 ps
CPU time 0.61 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:33 PM PDT 24
Peak memory 196796 kb
Host smart-1f299923-3f37-4c5b-8769-51d2563b2ff1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398111031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.3398111031
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.3997627590
Short name T474
Test name
Test status
Simulation time 207873278 ps
CPU time 1.01 seconds
Started May 23 03:38:27 PM PDT 24
Finished May 23 03:38:31 PM PDT 24
Peak memory 197572 kb
Host smart-a92effed-3762-440b-823a-267fdcde52f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997627590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.3997627590
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.711022477
Short name T760
Test name
Test status
Simulation time 63920364 ps
CPU time 0.61 seconds
Started May 23 03:38:32 PM PDT 24
Finished May 23 03:38:40 PM PDT 24
Peak memory 197548 kb
Host smart-79ef7298-a2df-430a-aca1-806936c2c958
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711022477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.711022477
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.1383629906
Short name T643
Test name
Test status
Simulation time 49029348 ps
CPU time 0.64 seconds
Started May 23 03:38:29 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 197908 kb
Host smart-dfde813e-2f50-4f63-b59d-4ac057c1d2fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383629906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.1383629906
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.34223000
Short name T365
Test name
Test status
Simulation time 64714170 ps
CPU time 0.67 seconds
Started May 23 03:38:29 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 200852 kb
Host smart-e968a7dc-b970-47dc-8f2f-19d3273cbc1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34223000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invalid
.34223000
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.3374101157
Short name T191
Test name
Test status
Simulation time 637672707 ps
CPU time 0.89 seconds
Started May 23 03:38:30 PM PDT 24
Finished May 23 03:38:37 PM PDT 24
Peak memory 198556 kb
Host smart-40f943e6-19f1-4ed9-919f-7f283a1f4cd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374101157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_w
akeup_race.3374101157
Directory /workspace/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.2665877568
Short name T1004
Test name
Test status
Simulation time 166646915 ps
CPU time 0.86 seconds
Started May 23 03:38:21 PM PDT 24
Finished May 23 03:38:25 PM PDT 24
Peak memory 199416 kb
Host smart-e70c68e4-55e4-432c-ac6e-c13c8b834ca2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665877568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.2665877568
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.2329222309
Short name T682
Test name
Test status
Simulation time 101407172 ps
CPU time 0.94 seconds
Started May 23 03:38:29 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 208944 kb
Host smart-3b38530c-d43a-412f-b184-99f8c507ad21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329222309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.2329222309
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.2961859438
Short name T664
Test name
Test status
Simulation time 213582301 ps
CPU time 0.79 seconds
Started May 23 03:38:21 PM PDT 24
Finished May 23 03:38:24 PM PDT 24
Peak memory 199384 kb
Host smart-e62b914f-cc68-4fbf-b4ba-da9388076e38
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961859438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_
cm_ctrl_config_regwen.2961859438
Directory /workspace/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2404809406
Short name T409
Test name
Test status
Simulation time 869624704 ps
CPU time 3.03 seconds
Started May 23 03:38:35 PM PDT 24
Finished May 23 03:38:45 PM PDT 24
Peak memory 200672 kb
Host smart-60aa3608-5fda-4273-9717-c99408a11d04
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404809406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2404809406
Directory /workspace/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2782532279
Short name T909
Test name
Test status
Simulation time 996589976 ps
CPU time 2.12 seconds
Started May 23 03:38:25 PM PDT 24
Finished May 23 03:38:30 PM PDT 24
Peak memory 200584 kb
Host smart-85efabd5-ab0a-489f-a60e-05ad5db756e3
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782532279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2782532279
Directory /workspace/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.488398908
Short name T284
Test name
Test status
Simulation time 65246364 ps
CPU time 0.97 seconds
Started May 23 03:38:27 PM PDT 24
Finished May 23 03:38:31 PM PDT 24
Peak memory 198876 kb
Host smart-7fa0bed2-0d24-4881-9f27-9dc82cb43deb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488398908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_
mubi.488398908
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.4149032176
Short name T196
Test name
Test status
Simulation time 44406479 ps
CPU time 0.65 seconds
Started May 23 03:38:27 PM PDT 24
Finished May 23 03:38:32 PM PDT 24
Peak memory 198052 kb
Host smart-499c7c5e-c628-4db4-ae49-a00fcad38ba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149032176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.4149032176
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all.2874139253
Short name T755
Test name
Test status
Simulation time 216616882 ps
CPU time 0.93 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 200256 kb
Host smart-eeca5f50-03e1-404d-a26d-8a613e7d5835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874139253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.2874139253
Directory /workspace/46.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all_with_rand_reset.3921479485
Short name T117
Test name
Test status
Simulation time 5358453459 ps
CPU time 7.87 seconds
Started May 23 03:38:35 PM PDT 24
Finished May 23 03:38:49 PM PDT 24
Peak memory 200860 kb
Host smart-f3ddc3a2-cc16-4dcf-836e-6064f3d99c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921479485 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all_with_rand_reset.3921479485
Directory /workspace/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup.2908339020
Short name T630
Test name
Test status
Simulation time 398901164 ps
CPU time 1.21 seconds
Started May 23 03:38:34 PM PDT 24
Finished May 23 03:38:42 PM PDT 24
Peak memory 199356 kb
Host smart-49dd07b6-7d17-4780-bf11-2fdd5e63300b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908339020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.2908339020
Directory /workspace/46.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup_reset.2492241815
Short name T486
Test name
Test status
Simulation time 33212890 ps
CPU time 0.65 seconds
Started May 23 03:38:30 PM PDT 24
Finished May 23 03:38:38 PM PDT 24
Peak memory 198128 kb
Host smart-0b877cc0-3bcb-4ea1-9488-8ed2f97e599a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492241815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.2492241815
Directory /workspace/46.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.2666822802
Short name T890
Test name
Test status
Simulation time 100458898 ps
CPU time 0.63 seconds
Started May 23 03:38:34 PM PDT 24
Finished May 23 03:38:41 PM PDT 24
Peak memory 198116 kb
Host smart-1577f464-d6ef-4bbe-8909-664cc4bea9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666822802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.2666822802
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.1412935977
Short name T992
Test name
Test status
Simulation time 88755276 ps
CPU time 0.72 seconds
Started May 23 03:38:35 PM PDT 24
Finished May 23 03:38:41 PM PDT 24
Peak memory 198672 kb
Host smart-8f24f4e7-f8a1-44a6-804e-c2c73b863947
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412935977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.1412935977
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.2453221364
Short name T989
Test name
Test status
Simulation time 28704854 ps
CPU time 0.62 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 197524 kb
Host smart-8f807606-cace-413c-89ea-abb74fd79f2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453221364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.2453221364
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.52605487
Short name T171
Test name
Test status
Simulation time 36238583 ps
CPU time 0.59 seconds
Started May 23 03:38:27 PM PDT 24
Finished May 23 03:38:31 PM PDT 24
Peak memory 197596 kb
Host smart-fc541311-aef0-48bf-85da-c595f441a21a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52605487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.52605487
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.1093000776
Short name T873
Test name
Test status
Simulation time 34083823 ps
CPU time 0.61 seconds
Started May 23 03:38:25 PM PDT 24
Finished May 23 03:38:28 PM PDT 24
Peak memory 197568 kb
Host smart-42094937-983d-4f0a-bd94-733f7aebec2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093000776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.1093000776
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.1692528006
Short name T10
Test name
Test status
Simulation time 46046901 ps
CPU time 0.69 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 200836 kb
Host smart-9d3070e1-f3a4-4f8c-b348-14145c22845a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692528006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.1692528006
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.504319111
Short name T725
Test name
Test status
Simulation time 248662852 ps
CPU time 1.06 seconds
Started May 23 03:38:23 PM PDT 24
Finished May 23 03:38:27 PM PDT 24
Peak memory 199228 kb
Host smart-a7951349-cbee-49a5-b803-391dceda180e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504319111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_wa
keup_race.504319111
Directory /workspace/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.2646947717
Short name T312
Test name
Test status
Simulation time 68653048 ps
CPU time 0.99 seconds
Started May 23 03:38:30 PM PDT 24
Finished May 23 03:38:39 PM PDT 24
Peak memory 199184 kb
Host smart-f8627b39-f56e-47ea-be6a-918f43f7aab0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646947717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.2646947717
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.314767723
Short name T843
Test name
Test status
Simulation time 97717647 ps
CPU time 1.07 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 208952 kb
Host smart-098f877e-49d4-4841-b784-e5309dc689a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314767723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.314767723
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.58393964
Short name T636
Test name
Test status
Simulation time 738511520 ps
CPU time 0.96 seconds
Started May 23 03:38:36 PM PDT 24
Finished May 23 03:38:43 PM PDT 24
Peak memory 200340 kb
Host smart-03c2c579-d840-491b-8cf4-d1b2cf205bf4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58393964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm
_ctrl_config_regwen.58393964
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3195887872
Short name T24
Test name
Test status
Simulation time 991413872 ps
CPU time 2.03 seconds
Started May 23 03:38:40 PM PDT 24
Finished May 23 03:38:48 PM PDT 24
Peak memory 200568 kb
Host smart-ac89e19b-1e83-40e7-b268-9ade0d5f1d80
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195887872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3195887872
Directory /workspace/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.835455280
Short name T638
Test name
Test status
Simulation time 874206618 ps
CPU time 2.36 seconds
Started May 23 03:38:32 PM PDT 24
Finished May 23 03:38:41 PM PDT 24
Peak memory 200600 kb
Host smart-31739f50-a03e-487e-b906-f7a2af814390
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835455280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.835455280
Directory /workspace/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1464347221
Short name T383
Test name
Test status
Simulation time 66691961 ps
CPU time 0.91 seconds
Started May 23 03:38:20 PM PDT 24
Finished May 23 03:38:23 PM PDT 24
Peak memory 198640 kb
Host smart-d6a3318f-b9c2-4673-b3e8-ccc75b99be0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464347221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1464347221
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.2272109155
Short name T875
Test name
Test status
Simulation time 80440765 ps
CPU time 0.63 seconds
Started May 23 03:38:34 PM PDT 24
Finished May 23 03:38:41 PM PDT 24
Peak memory 198848 kb
Host smart-7427f29a-08f7-4cc1-93d4-94fbb4100f64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272109155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.2272109155
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all.2542346941
Short name T412
Test name
Test status
Simulation time 744644181 ps
CPU time 2.66 seconds
Started May 23 03:38:25 PM PDT 24
Finished May 23 03:38:30 PM PDT 24
Peak memory 200680 kb
Host smart-38757d1d-7aed-42af-b86c-762ab8e245dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542346941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.2542346941
Directory /workspace/47.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all_with_rand_reset.4219662945
Short name T536
Test name
Test status
Simulation time 6154388222 ps
CPU time 14.36 seconds
Started May 23 03:38:38 PM PDT 24
Finished May 23 03:38:58 PM PDT 24
Peak memory 200860 kb
Host smart-dc4c8657-4df2-4af4-b61a-fa7d4f6b3f7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219662945 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all_with_rand_reset.4219662945
Directory /workspace/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup.2922498836
Short name T743
Test name
Test status
Simulation time 94422080 ps
CPU time 0.88 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 197640 kb
Host smart-e199a8cf-5b9c-4096-9873-03227af6d291
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922498836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.2922498836
Directory /workspace/47.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup_reset.1656305242
Short name T34
Test name
Test status
Simulation time 97590047 ps
CPU time 0.81 seconds
Started May 23 03:38:43 PM PDT 24
Finished May 23 03:38:49 PM PDT 24
Peak memory 198104 kb
Host smart-ee41e273-2a18-4db0-b439-2de67f021075
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656305242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.1656305242
Directory /workspace/47.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.3552751030
Short name T262
Test name
Test status
Simulation time 71425773 ps
CPU time 0.85 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 199624 kb
Host smart-d92303cc-8cd5-4666-a90f-c052280ccfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552751030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.3552751030
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.3111230006
Short name T22
Test name
Test status
Simulation time 83279166 ps
CPU time 0.69 seconds
Started May 23 03:38:21 PM PDT 24
Finished May 23 03:38:24 PM PDT 24
Peak memory 198088 kb
Host smart-cb038759-e776-47ed-b28a-4c47518d80a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111230006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.3111230006
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.103772519
Short name T399
Test name
Test status
Simulation time 30466111 ps
CPU time 0.64 seconds
Started May 23 03:38:23 PM PDT 24
Finished May 23 03:38:27 PM PDT 24
Peak memory 196824 kb
Host smart-31505b5f-81b0-42e9-8f95-4930d8eb128b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103772519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_
malfunc.103772519
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.861464916
Short name T991
Test name
Test status
Simulation time 192409588 ps
CPU time 0.98 seconds
Started May 23 03:38:25 PM PDT 24
Finished May 23 03:38:28 PM PDT 24
Peak memory 197948 kb
Host smart-c6cb4ccb-c2cc-49d1-88e5-11ab79735413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861464916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.861464916
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.2789882075
Short name T892
Test name
Test status
Simulation time 53465115 ps
CPU time 0.59 seconds
Started May 23 03:38:25 PM PDT 24
Finished May 23 03:38:27 PM PDT 24
Peak memory 197676 kb
Host smart-b77c810a-a5d2-4b4a-9a16-e5a0246e47f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789882075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.2789882075
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.331650282
Short name T138
Test name
Test status
Simulation time 53995421 ps
CPU time 0.59 seconds
Started May 23 03:38:29 PM PDT 24
Finished May 23 03:38:35 PM PDT 24
Peak memory 197608 kb
Host smart-9c83c230-809d-4ac6-964c-1e5dd9080b27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331650282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.331650282
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.889526218
Short name T190
Test name
Test status
Simulation time 50930478 ps
CPU time 0.67 seconds
Started May 23 03:38:21 PM PDT 24
Finished May 23 03:38:25 PM PDT 24
Peak memory 200864 kb
Host smart-86503a49-147f-4e70-a983-8762701545e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889526218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_invali
d.889526218
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.3988210260
Short name T392
Test name
Test status
Simulation time 83932127 ps
CPU time 0.65 seconds
Started May 23 03:38:26 PM PDT 24
Finished May 23 03:38:30 PM PDT 24
Peak memory 198032 kb
Host smart-28f808c4-97ed-4296-9bf5-8ad3f3303660
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988210260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_w
akeup_race.3988210260
Directory /workspace/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.1400786206
Short name T354
Test name
Test status
Simulation time 67258805 ps
CPU time 0.71 seconds
Started May 23 03:38:34 PM PDT 24
Finished May 23 03:38:41 PM PDT 24
Peak memory 198036 kb
Host smart-b17891e0-2acb-4d6c-b8e3-d2c57bacd0f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400786206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.1400786206
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.2022470098
Short name T987
Test name
Test status
Simulation time 496085549 ps
CPU time 0.85 seconds
Started May 23 03:38:25 PM PDT 24
Finished May 23 03:38:28 PM PDT 24
Peak memory 208880 kb
Host smart-22f67193-fe88-48fc-b260-4b3d81574e99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022470098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.2022470098
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.1011016686
Short name T513
Test name
Test status
Simulation time 256147844 ps
CPU time 0.93 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:33 PM PDT 24
Peak memory 199520 kb
Host smart-add0e083-2573-4b0a-b8db-128bb527ef37
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011016686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_
cm_ctrl_config_regwen.1011016686
Directory /workspace/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.124818127
Short name T683
Test name
Test status
Simulation time 1181919930 ps
CPU time 2.17 seconds
Started May 23 03:38:32 PM PDT 24
Finished May 23 03:38:41 PM PDT 24
Peak memory 200632 kb
Host smart-967f01d7-6a75-44bb-adf0-0fb5196a9a4d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124818127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.124818127
Directory /workspace/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.486637112
Short name T350
Test name
Test status
Simulation time 884363701 ps
CPU time 2.39 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:35 PM PDT 24
Peak memory 200464 kb
Host smart-1c4cb9d5-6719-4a15-9152-0029b903246b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486637112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.486637112
Directory /workspace/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1612868034
Short name T219
Test name
Test status
Simulation time 74553193 ps
CPU time 0.96 seconds
Started May 23 03:38:41 PM PDT 24
Finished May 23 03:38:47 PM PDT 24
Peak memory 198912 kb
Host smart-a147bab9-6e32-4e60-92e9-d8226a4846f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612868034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1612868034
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.1353138139
Short name T259
Test name
Test status
Simulation time 57792770 ps
CPU time 0.61 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 198840 kb
Host smart-0156d4f9-8b9c-4bc9-a78b-b1eb0a030fd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353138139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.1353138139
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all.2120252742
Short name T96
Test name
Test status
Simulation time 1696137150 ps
CPU time 1.72 seconds
Started May 23 03:38:24 PM PDT 24
Finished May 23 03:38:28 PM PDT 24
Peak memory 200680 kb
Host smart-ad11d671-ac21-46aa-8161-1dcc4e8cec90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120252742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.2120252742
Directory /workspace/48.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all_with_rand_reset.1273207188
Short name T128
Test name
Test status
Simulation time 7193529672 ps
CPU time 21.28 seconds
Started May 23 03:38:21 PM PDT 24
Finished May 23 03:38:46 PM PDT 24
Peak memory 200924 kb
Host smart-2d3aadc4-61e0-439a-8e89-c58a1037e07d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273207188 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all_with_rand_reset.1273207188
Directory /workspace/48.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup.2007037807
Short name T944
Test name
Test status
Simulation time 409794003 ps
CPU time 1.08 seconds
Started May 23 03:38:21 PM PDT 24
Finished May 23 03:38:25 PM PDT 24
Peak memory 199108 kb
Host smart-cd0e2569-fcee-4526-a7b7-ca2e3fba7921
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007037807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.2007037807
Directory /workspace/48.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup_reset.4165704197
Short name T954
Test name
Test status
Simulation time 178311372 ps
CPU time 0.79 seconds
Started May 23 03:38:29 PM PDT 24
Finished May 23 03:38:36 PM PDT 24
Peak memory 198860 kb
Host smart-462c2dea-45b6-43fe-855b-32eed79e872e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165704197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.4165704197
Directory /workspace/48.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.1372398414
Short name T767
Test name
Test status
Simulation time 64901740 ps
CPU time 0.9 seconds
Started May 23 03:38:27 PM PDT 24
Finished May 23 03:38:32 PM PDT 24
Peak memory 200000 kb
Host smart-6e98c740-7634-4c6a-99bf-54286a75732e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372398414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.1372398414
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.2596048208
Short name T671
Test name
Test status
Simulation time 61746034 ps
CPU time 0.86 seconds
Started May 23 03:38:43 PM PDT 24
Finished May 23 03:38:49 PM PDT 24
Peak memory 198624 kb
Host smart-fedc8c96-feea-43c7-af9c-b0c656a3cda8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596048208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.2596048208
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3817863099
Short name T964
Test name
Test status
Simulation time 28506042 ps
CPU time 0.62 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:32 PM PDT 24
Peak memory 197528 kb
Host smart-5ebf100f-bf0e-4918-a47a-d2515b39248f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817863099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.3817863099
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.1693593514
Short name T520
Test name
Test status
Simulation time 1085807959 ps
CPU time 0.95 seconds
Started May 23 03:38:35 PM PDT 24
Finished May 23 03:38:42 PM PDT 24
Peak memory 197620 kb
Host smart-8367d364-6720-484f-a0b6-b1026b2c0cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693593514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.1693593514
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.599839788
Short name T558
Test name
Test status
Simulation time 47847684 ps
CPU time 0.63 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 196816 kb
Host smart-3121bc6f-6732-4951-a147-14e77252e63c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599839788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.599839788
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.2653000186
Short name T337
Test name
Test status
Simulation time 96931432 ps
CPU time 0.66 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:34 PM PDT 24
Peak memory 197876 kb
Host smart-19875158-cb78-402b-a06d-481f62d3c5f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653000186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.2653000186
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.2517711907
Short name T928
Test name
Test status
Simulation time 115691004 ps
CPU time 0.67 seconds
Started May 23 03:38:27 PM PDT 24
Finished May 23 03:38:31 PM PDT 24
Peak memory 200816 kb
Host smart-ecd40ec1-9646-4ff4-a769-661ecf7d521e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517711907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.2517711907
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.819995159
Short name T506
Test name
Test status
Simulation time 267444283 ps
CPU time 1.24 seconds
Started May 23 03:38:36 PM PDT 24
Finished May 23 03:38:43 PM PDT 24
Peak memory 199020 kb
Host smart-aa3324a1-9a46-4a72-ac2b-647579b4f15b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819995159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wa
keup_race.819995159
Directory /workspace/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.2665892565
Short name T839
Test name
Test status
Simulation time 71451892 ps
CPU time 0.91 seconds
Started May 23 03:38:27 PM PDT 24
Finished May 23 03:38:32 PM PDT 24
Peak memory 198104 kb
Host smart-b53db63a-377a-431a-a52e-786c88dd0c3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665892565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2665892565
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.1039259377
Short name T240
Test name
Test status
Simulation time 109135694 ps
CPU time 0.81 seconds
Started May 23 03:38:30 PM PDT 24
Finished May 23 03:38:37 PM PDT 24
Peak memory 208980 kb
Host smart-71e08d1f-3dad-442d-822a-ae57a8759d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039259377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.1039259377
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.3691402143
Short name T294
Test name
Test status
Simulation time 256703640 ps
CPU time 1.29 seconds
Started May 23 03:38:28 PM PDT 24
Finished May 23 03:38:33 PM PDT 24
Peak memory 200360 kb
Host smart-7c854fa9-8b61-4544-bc37-474775573fbe
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691402143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_
cm_ctrl_config_regwen.3691402143
Directory /workspace/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3598794892
Short name T924
Test name
Test status
Simulation time 1046221903 ps
CPU time 2 seconds
Started May 23 03:38:38 PM PDT 24
Finished May 23 03:38:45 PM PDT 24
Peak memory 200576 kb
Host smart-e4b3c227-e8b2-4bda-afb2-6511ad1f89b5
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598794892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3598794892
Directory /workspace/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1788935111
Short name T195
Test name
Test status
Simulation time 1326339028 ps
CPU time 1.86 seconds
Started May 23 03:38:40 PM PDT 24
Finished May 23 03:38:47 PM PDT 24
Peak memory 200640 kb
Host smart-486e2cbd-5ce4-4d06-8895-c64640e69930
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788935111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1788935111
Directory /workspace/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1961339760
Short name T182
Test name
Test status
Simulation time 54170270 ps
CPU time 0.88 seconds
Started May 23 03:38:31 PM PDT 24
Finished May 23 03:38:39 PM PDT 24
Peak memory 198792 kb
Host smart-4d75815d-5343-4885-8630-556869bf7ffb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961339760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1961339760
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.3782903512
Short name T295
Test name
Test status
Simulation time 29374927 ps
CPU time 0.69 seconds
Started May 23 03:38:27 PM PDT 24
Finished May 23 03:38:32 PM PDT 24
Peak memory 198836 kb
Host smart-28f8d7f9-8ca8-4ae4-a348-f03dc076cf5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782903512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.3782903512
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all.910245435
Short name T617
Test name
Test status
Simulation time 4300569778 ps
CPU time 3.82 seconds
Started May 23 03:38:19 PM PDT 24
Finished May 23 03:38:26 PM PDT 24
Peak memory 200748 kb
Host smart-b96c8ce2-59ac-4b29-a2d9-d113e9b76c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910245435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.910245435
Directory /workspace/49.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all_with_rand_reset.168196440
Short name T627
Test name
Test status
Simulation time 4411555921 ps
CPU time 15.45 seconds
Started May 23 03:38:26 PM PDT 24
Finished May 23 03:38:44 PM PDT 24
Peak memory 200860 kb
Host smart-3d6861cb-be62-45c0-9826-a99422a10041
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168196440 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all_with_rand_reset.168196440
Directory /workspace/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup.493408526
Short name T868
Test name
Test status
Simulation time 179808239 ps
CPU time 0.88 seconds
Started May 23 03:38:38 PM PDT 24
Finished May 23 03:38:44 PM PDT 24
Peak memory 198044 kb
Host smart-7c758c84-05c0-4cae-ad0b-a4237b437d37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493408526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.493408526
Directory /workspace/49.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup_reset.1149053551
Short name T461
Test name
Test status
Simulation time 54637486 ps
CPU time 0.66 seconds
Started May 23 03:38:21 PM PDT 24
Finished May 23 03:38:25 PM PDT 24
Peak memory 197896 kb
Host smart-b303f3d0-a588-4a76-979a-a73e948236bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149053551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.1149053551
Directory /workspace/49.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.440292728
Short name T184
Test name
Test status
Simulation time 47881844 ps
CPU time 0.95 seconds
Started May 23 03:36:13 PM PDT 24
Finished May 23 03:36:22 PM PDT 24
Peak memory 200360 kb
Host smart-9d5eca2b-d424-421c-8df7-3f748f5978e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440292728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.440292728
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.1255197735
Short name T446
Test name
Test status
Simulation time 73238385 ps
CPU time 0.72 seconds
Started May 23 03:36:15 PM PDT 24
Finished May 23 03:36:23 PM PDT 24
Peak memory 198620 kb
Host smart-9ca15f47-d934-4d96-8ce7-0332af5ce1ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255197735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.1255197735
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.164927084
Short name T335
Test name
Test status
Simulation time 39568344 ps
CPU time 0.59 seconds
Started May 23 03:36:18 PM PDT 24
Finished May 23 03:36:26 PM PDT 24
Peak memory 196848 kb
Host smart-8e5b4e6f-738e-415a-b042-d9aee22018d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164927084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_m
alfunc.164927084
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.1507205447
Short name T776
Test name
Test status
Simulation time 201348349 ps
CPU time 0.94 seconds
Started May 23 03:36:18 PM PDT 24
Finished May 23 03:36:25 PM PDT 24
Peak memory 197556 kb
Host smart-0b31037a-22a3-485b-b32c-a16b6855f7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507205447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.1507205447
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.2970508668
Short name T238
Test name
Test status
Simulation time 49101718 ps
CPU time 0.67 seconds
Started May 23 03:36:11 PM PDT 24
Finished May 23 03:36:18 PM PDT 24
Peak memory 196796 kb
Host smart-e05a19f2-3923-44fa-a3e0-9ab94f2cb932
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970508668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.2970508668
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.2434252367
Short name T517
Test name
Test status
Simulation time 34470900 ps
CPU time 0.64 seconds
Started May 23 03:36:18 PM PDT 24
Finished May 23 03:36:25 PM PDT 24
Peak memory 197600 kb
Host smart-c41868bb-a32b-4224-b2c7-ca61df167acb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434252367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.2434252367
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.2487614133
Short name T817
Test name
Test status
Simulation time 88073929 ps
CPU time 0.69 seconds
Started May 23 03:36:15 PM PDT 24
Finished May 23 03:36:23 PM PDT 24
Peak memory 200848 kb
Host smart-54eb117a-131b-4b17-9e5f-b67f5f14555b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487614133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.2487614133
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.1112144138
Short name T826
Test name
Test status
Simulation time 598391530 ps
CPU time 0.92 seconds
Started May 23 03:36:12 PM PDT 24
Finished May 23 03:36:20 PM PDT 24
Peak memory 199036 kb
Host smart-d784d718-3331-4fab-851c-3211ab5bf597
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112144138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wa
keup_race.1112144138
Directory /workspace/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.2226388432
Short name T254
Test name
Test status
Simulation time 106895766 ps
CPU time 0.84 seconds
Started May 23 03:36:09 PM PDT 24
Finished May 23 03:36:14 PM PDT 24
Peak memory 199396 kb
Host smart-f00ff2f6-77a9-46d3-b1d8-b56723d1e586
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226388432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.2226388432
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.147047462
Short name T723
Test name
Test status
Simulation time 113460686 ps
CPU time 0.91 seconds
Started May 23 03:36:18 PM PDT 24
Finished May 23 03:36:25 PM PDT 24
Peak memory 200676 kb
Host smart-3d45ee35-f439-4f1f-8eb7-28141c0ade17
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147047462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.147047462
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3482060748
Short name T835
Test name
Test status
Simulation time 508547790 ps
CPU time 0.94 seconds
Started May 23 03:36:17 PM PDT 24
Finished May 23 03:36:25 PM PDT 24
Peak memory 199716 kb
Host smart-aebc42c4-e75a-4b51-a01f-17e554d59bb9
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482060748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_c
m_ctrl_config_regwen.3482060748
Directory /workspace/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.709249036
Short name T982
Test name
Test status
Simulation time 807393943 ps
CPU time 2.76 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:32 PM PDT 24
Peak memory 200644 kb
Host smart-cc08a3e7-42fe-4181-983c-30def3562c4b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709249036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.709249036
Directory /workspace/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3379354286
Short name T297
Test name
Test status
Simulation time 1026851465 ps
CPU time 2.08 seconds
Started May 23 03:36:13 PM PDT 24
Finished May 23 03:36:22 PM PDT 24
Peak memory 200512 kb
Host smart-3edde58b-10f4-4549-9758-f2e817003cdc
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379354286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3379354286
Directory /workspace/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1211656204
Short name T421
Test name
Test status
Simulation time 97417532 ps
CPU time 0.85 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:30 PM PDT 24
Peak memory 199200 kb
Host smart-46ae5ec0-4d7f-4625-ae02-2d66f854c517
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211656204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1211656204
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.949165935
Short name T210
Test name
Test status
Simulation time 29677495 ps
CPU time 0.72 seconds
Started May 23 03:36:15 PM PDT 24
Finished May 23 03:36:23 PM PDT 24
Peak memory 198872 kb
Host smart-755de3f1-3445-41bd-b360-a80108a9b9b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949165935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.949165935
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all.2522593122
Short name T731
Test name
Test status
Simulation time 1575574856 ps
CPU time 3.56 seconds
Started May 23 03:36:25 PM PDT 24
Finished May 23 03:36:35 PM PDT 24
Peak memory 200660 kb
Host smart-e84a5669-3ddb-4954-b17c-41d182cb11c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522593122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.2522593122
Directory /workspace/5.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all_with_rand_reset.2229548174
Short name T120
Test name
Test status
Simulation time 4191841532 ps
CPU time 6.61 seconds
Started May 23 03:36:15 PM PDT 24
Finished May 23 03:36:29 PM PDT 24
Peak memory 200856 kb
Host smart-fff06400-e40e-48bf-a81e-0b225f8775b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229548174 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all_with_rand_reset.2229548174
Directory /workspace/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.235336086
Short name T9
Test name
Test status
Simulation time 171172660 ps
CPU time 0.8 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:30 PM PDT 24
Peak memory 197980 kb
Host smart-78d5b384-7ca3-4e95-8107-ec360b54d320
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235336086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.235336086
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup_reset.931924780
Short name T372
Test name
Test status
Simulation time 267234413 ps
CPU time 0.84 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:30 PM PDT 24
Peak memory 199480 kb
Host smart-3a853ec2-c654-49d6-bcbd-e89cc02b51d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931924780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.931924780
Directory /workspace/5.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.2386504910
Short name T92
Test name
Test status
Simulation time 84794764 ps
CPU time 0.73 seconds
Started May 23 03:36:26 PM PDT 24
Finished May 23 03:36:32 PM PDT 24
Peak memory 198224 kb
Host smart-7680cae1-3b5d-415b-99de-3b1eaef01bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386504910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.2386504910
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.2359083224
Short name T968
Test name
Test status
Simulation time 93342416 ps
CPU time 0.69 seconds
Started May 23 03:36:28 PM PDT 24
Finished May 23 03:36:33 PM PDT 24
Peak memory 198628 kb
Host smart-8a7b17dc-820e-4572-9392-e822a9964073
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359083224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.2359083224
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2389554871
Short name T492
Test name
Test status
Simulation time 33013425 ps
CPU time 0.61 seconds
Started May 23 03:36:20 PM PDT 24
Finished May 23 03:36:27 PM PDT 24
Peak memory 197560 kb
Host smart-ee0b0c8d-54d2-412a-9876-50b867f0fbc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389554871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.2389554871
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.2918084285
Short name T777
Test name
Test status
Simulation time 611330396 ps
CPU time 0.95 seconds
Started May 23 03:36:24 PM PDT 24
Finished May 23 03:36:31 PM PDT 24
Peak memory 197548 kb
Host smart-931427eb-4182-4bb7-9c93-099d5d343282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918084285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.2918084285
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.1026125040
Short name T797
Test name
Test status
Simulation time 65346287 ps
CPU time 0.59 seconds
Started May 23 03:36:26 PM PDT 24
Finished May 23 03:36:32 PM PDT 24
Peak memory 196884 kb
Host smart-8916eaf3-52b3-4ba2-97da-d6a7902c2c9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026125040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.1026125040
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.630177329
Short name T495
Test name
Test status
Simulation time 88309128 ps
CPU time 0.61 seconds
Started May 23 03:36:20 PM PDT 24
Finished May 23 03:36:28 PM PDT 24
Peak memory 197580 kb
Host smart-416b409a-fbe6-4db0-a759-73b72b00c1e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630177329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.630177329
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.747128808
Short name T514
Test name
Test status
Simulation time 51079370 ps
CPU time 0.66 seconds
Started May 23 03:36:20 PM PDT 24
Finished May 23 03:36:28 PM PDT 24
Peak memory 200880 kb
Host smart-735b6ebb-10b3-4225-a52d-e33477fd00f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747128808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invalid
.747128808
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.280758001
Short name T504
Test name
Test status
Simulation time 170828119 ps
CPU time 0.99 seconds
Started May 23 03:36:21 PM PDT 24
Finished May 23 03:36:28 PM PDT 24
Peak memory 198120 kb
Host smart-deb0656e-fce5-4a07-a067-ab83e4381e4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280758001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wak
eup_race.280758001
Directory /workspace/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.4052316837
Short name T792
Test name
Test status
Simulation time 60461692 ps
CPU time 1.05 seconds
Started May 23 03:36:21 PM PDT 24
Finished May 23 03:36:28 PM PDT 24
Peak memory 198584 kb
Host smart-429a159b-0027-4836-b3df-2ba900ee6c56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052316837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.4052316837
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.446986017
Short name T919
Test name
Test status
Simulation time 113766958 ps
CPU time 0.99 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:30 PM PDT 24
Peak memory 208856 kb
Host smart-f2965d84-4055-4b9a-8a62-1997e07c2977
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446986017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.446986017
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.4141994705
Short name T351
Test name
Test status
Simulation time 140655066 ps
CPU time 1.07 seconds
Started May 23 03:36:25 PM PDT 24
Finished May 23 03:36:32 PM PDT 24
Peak memory 199252 kb
Host smart-64e808e1-fd17-41c4-b8d2-fa84b02d6703
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141994705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_c
m_ctrl_config_regwen.4141994705
Directory /workspace/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2301674317
Short name T395
Test name
Test status
Simulation time 853708202 ps
CPU time 2.44 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:31 PM PDT 24
Peak memory 200664 kb
Host smart-3b2d062b-b355-4120-ab6a-9af65c4de118
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301674317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2301674317
Directory /workspace/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2863150358
Short name T449
Test name
Test status
Simulation time 1091496825 ps
CPU time 2.06 seconds
Started May 23 03:36:27 PM PDT 24
Finished May 23 03:36:34 PM PDT 24
Peak memory 200336 kb
Host smart-3e4e6445-c759-4d37-957b-196eda8cf818
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863150358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2863150358
Directory /workspace/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2294241927
Short name T308
Test name
Test status
Simulation time 92963564 ps
CPU time 0.78 seconds
Started May 23 03:36:30 PM PDT 24
Finished May 23 03:36:34 PM PDT 24
Peak memory 198864 kb
Host smart-a0810862-3e4a-4558-8b50-19392e40258f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294241927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2294241927
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.3270092319
Short name T202
Test name
Test status
Simulation time 29056342 ps
CPU time 0.68 seconds
Started May 23 03:36:22 PM PDT 24
Finished May 23 03:36:29 PM PDT 24
Peak memory 198796 kb
Host smart-7887928a-be34-4cd1-8673-d84dd63e9e18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270092319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.3270092319
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all.3822284760
Short name T394
Test name
Test status
Simulation time 1511344857 ps
CPU time 5.57 seconds
Started May 23 03:36:21 PM PDT 24
Finished May 23 03:36:33 PM PDT 24
Peak memory 200680 kb
Host smart-8c259a45-8b04-4efe-9936-e999b536c10d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822284760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.3822284760
Directory /workspace/6.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all_with_rand_reset.3322959516
Short name T415
Test name
Test status
Simulation time 9537142029 ps
CPU time 19.84 seconds
Started May 23 03:36:25 PM PDT 24
Finished May 23 03:36:50 PM PDT 24
Peak memory 200872 kb
Host smart-4eda2bde-c1bd-4739-b53b-1925350a5afb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322959516 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all_with_rand_reset.3322959516
Directory /workspace/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup.1055613014
Short name T761
Test name
Test status
Simulation time 207750968 ps
CPU time 1.15 seconds
Started May 23 03:36:30 PM PDT 24
Finished May 23 03:36:35 PM PDT 24
Peak memory 199100 kb
Host smart-32272704-001c-4165-a1c0-7c5faa6e717e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055613014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.1055613014
Directory /workspace/6.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup_reset.2407683481
Short name T692
Test name
Test status
Simulation time 484820960 ps
CPU time 1.14 seconds
Started May 23 03:36:30 PM PDT 24
Finished May 23 03:36:35 PM PDT 24
Peak memory 200492 kb
Host smart-e2d1553e-6c4d-4909-95e8-012120d16814
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407683481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.2407683481
Directory /workspace/6.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.1447024943
Short name T90
Test name
Test status
Simulation time 29825087 ps
CPU time 0.83 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:30 PM PDT 24
Peak memory 199704 kb
Host smart-f04f490b-1eff-4ffc-b157-6a0543d4856d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447024943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.1447024943
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.391756623
Short name T159
Test name
Test status
Simulation time 52396521 ps
CPU time 0.83 seconds
Started May 23 03:36:25 PM PDT 24
Finished May 23 03:36:32 PM PDT 24
Peak memory 198716 kb
Host smart-1b6a9b81-9dac-44c8-9b7d-1ea24380e602
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391756623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disab
le_rom_integrity_check.391756623
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2857675232
Short name T477
Test name
Test status
Simulation time 31286028 ps
CPU time 0.64 seconds
Started May 23 03:36:28 PM PDT 24
Finished May 23 03:36:33 PM PDT 24
Peak memory 197544 kb
Host smart-964f85c2-6b45-4971-a128-712cea5745ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857675232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.2857675232
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.4212746085
Short name T565
Test name
Test status
Simulation time 635818254 ps
CPU time 1 seconds
Started May 23 03:36:20 PM PDT 24
Finished May 23 03:36:28 PM PDT 24
Peak memory 197608 kb
Host smart-667dec7a-08ac-4b0b-8f2d-8acd0462c1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212746085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.4212746085
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.3292739657
Short name T304
Test name
Test status
Simulation time 54039438 ps
CPU time 0.67 seconds
Started May 23 03:36:26 PM PDT 24
Finished May 23 03:36:32 PM PDT 24
Peak memory 197392 kb
Host smart-0c0c13e2-08ea-4680-a1be-900a252f53c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292739657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.3292739657
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.1839958640
Short name T7
Test name
Test status
Simulation time 118555466 ps
CPU time 0.63 seconds
Started May 23 03:36:27 PM PDT 24
Finished May 23 03:36:33 PM PDT 24
Peak memory 197604 kb
Host smart-680a2251-4c9b-4086-a271-773279ddd670
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839958640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.1839958640
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.2836634578
Short name T564
Test name
Test status
Simulation time 286624883 ps
CPU time 0.65 seconds
Started May 23 03:36:22 PM PDT 24
Finished May 23 03:36:28 PM PDT 24
Peak memory 200860 kb
Host smart-8b685461-1a03-4360-8bf6-bf9b186ff1fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836634578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.2836634578
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.2249591161
Short name T663
Test name
Test status
Simulation time 83546862 ps
CPU time 0.69 seconds
Started May 23 03:36:22 PM PDT 24
Finished May 23 03:36:29 PM PDT 24
Peak memory 197896 kb
Host smart-08aede75-8dd8-449f-82e5-a99b2dd70941
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249591161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wa
keup_race.2249591161
Directory /workspace/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.3437575758
Short name T281
Test name
Test status
Simulation time 66092133 ps
CPU time 0.68 seconds
Started May 23 03:36:21 PM PDT 24
Finished May 23 03:36:28 PM PDT 24
Peak memory 198168 kb
Host smart-15dae319-989c-4fce-be97-3f1fc64e4003
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437575758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.3437575758
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.1729543485
Short name T740
Test name
Test status
Simulation time 107226825 ps
CPU time 0.97 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:30 PM PDT 24
Peak memory 208860 kb
Host smart-b6ed06d8-119b-4832-883b-7e2e79838b89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729543485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.1729543485
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.1187705821
Short name T800
Test name
Test status
Simulation time 603389490 ps
CPU time 0.89 seconds
Started May 23 03:36:29 PM PDT 24
Finished May 23 03:36:34 PM PDT 24
Peak memory 199388 kb
Host smart-1282aba6-0c03-4442-b353-13c7b022d745
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187705821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_c
m_ctrl_config_regwen.1187705821
Directory /workspace/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3918004044
Short name T730
Test name
Test status
Simulation time 861625908 ps
CPU time 2.9 seconds
Started May 23 03:36:24 PM PDT 24
Finished May 23 03:36:33 PM PDT 24
Peak memory 200596 kb
Host smart-e9db6303-c834-4dae-b9e5-5a99cf5e3909
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918004044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3918004044
Directory /workspace/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3853299574
Short name T904
Test name
Test status
Simulation time 1940725582 ps
CPU time 2.21 seconds
Started May 23 03:36:27 PM PDT 24
Finished May 23 03:36:34 PM PDT 24
Peak memory 200680 kb
Host smart-aba68e4a-23cb-4a42-8d74-871e4cc5b79e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853299574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3853299574
Directory /workspace/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.4042975065
Short name T345
Test name
Test status
Simulation time 88857443 ps
CPU time 0.92 seconds
Started May 23 03:36:26 PM PDT 24
Finished May 23 03:36:32 PM PDT 24
Peak memory 198944 kb
Host smart-eeb7b350-6651-443c-82aa-f61d205e2317
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042975065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4042975065
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.1167371448
Short name T374
Test name
Test status
Simulation time 32499200 ps
CPU time 0.73 seconds
Started May 23 03:36:20 PM PDT 24
Finished May 23 03:36:27 PM PDT 24
Peak memory 198872 kb
Host smart-5cadc457-c7b0-4e75-84b6-ff64ac3456fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167371448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.1167371448
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all.681748328
Short name T674
Test name
Test status
Simulation time 2288352989 ps
CPU time 4.84 seconds
Started May 23 03:36:25 PM PDT 24
Finished May 23 03:36:36 PM PDT 24
Peak memory 200796 kb
Host smart-709c590a-cfc5-49b8-a624-b123b1b409fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681748328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.681748328
Directory /workspace/7.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all_with_rand_reset.1566967165
Short name T74
Test name
Test status
Simulation time 4078530146 ps
CPU time 7.92 seconds
Started May 23 03:36:30 PM PDT 24
Finished May 23 03:36:42 PM PDT 24
Peak memory 200856 kb
Host smart-d8094a17-7f4b-4c22-8b68-353f53911133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566967165 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all_with_rand_reset.1566967165
Directory /workspace/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup.3801443655
Short name T458
Test name
Test status
Simulation time 36791904 ps
CPU time 0.68 seconds
Started May 23 03:36:25 PM PDT 24
Finished May 23 03:36:32 PM PDT 24
Peak memory 197800 kb
Host smart-b556a611-275f-43b9-adf6-aea30493f333
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801443655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.3801443655
Directory /workspace/7.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup_reset.1385553601
Short name T768
Test name
Test status
Simulation time 486461270 ps
CPU time 1.17 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:31 PM PDT 24
Peak memory 200508 kb
Host smart-940f543c-2489-4638-af83-8dab5c0348b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385553601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.1385553601
Directory /workspace/7.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.1755845034
Short name T274
Test name
Test status
Simulation time 20519012 ps
CPU time 0.72 seconds
Started May 23 03:36:27 PM PDT 24
Finished May 23 03:36:33 PM PDT 24
Peak memory 198668 kb
Host smart-c1961055-4ce1-4608-baab-2f26b01a2d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755845034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.1755845034
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.3056169910
Short name T163
Test name
Test status
Simulation time 80762963 ps
CPU time 0.65 seconds
Started May 23 03:36:20 PM PDT 24
Finished May 23 03:36:27 PM PDT 24
Peak memory 198096 kb
Host smart-ddf4b54a-b613-44cd-9f3c-1cdfc3d7635e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056169910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.3056169910
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3858315864
Short name T137
Test name
Test status
Simulation time 38320620 ps
CPU time 0.56 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:30 PM PDT 24
Peak memory 197532 kb
Host smart-2499dae3-aa08-44bd-897a-0665492c6909
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858315864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.3858315864
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.1656885246
Short name T945
Test name
Test status
Simulation time 1141434571 ps
CPU time 1.01 seconds
Started May 23 03:36:24 PM PDT 24
Finished May 23 03:36:31 PM PDT 24
Peak memory 197648 kb
Host smart-1f5af6d8-8df6-4c8d-9050-9a7ed906171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656885246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.1656885246
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.2503461877
Short name T484
Test name
Test status
Simulation time 57723166 ps
CPU time 0.62 seconds
Started May 23 03:36:31 PM PDT 24
Finished May 23 03:36:35 PM PDT 24
Peak memory 197592 kb
Host smart-d443e168-20a8-4a19-8bb1-51cba7077f48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503461877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2503461877
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.1197088658
Short name T555
Test name
Test status
Simulation time 47408330 ps
CPU time 0.65 seconds
Started May 23 03:36:22 PM PDT 24
Finished May 23 03:36:29 PM PDT 24
Peak memory 197552 kb
Host smart-f923e714-f44a-4206-a402-601efdceacfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197088658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.1197088658
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.1547899891
Short name T881
Test name
Test status
Simulation time 41573963 ps
CPU time 0.79 seconds
Started May 23 03:36:29 PM PDT 24
Finished May 23 03:36:34 PM PDT 24
Peak memory 200852 kb
Host smart-f1cce6ab-3540-46e5-83cc-9a16825f955f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547899891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.1547899891
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.3360608460
Short name T599
Test name
Test status
Simulation time 203748468 ps
CPU time 0.72 seconds
Started May 23 03:36:25 PM PDT 24
Finished May 23 03:36:31 PM PDT 24
Peak memory 198588 kb
Host smart-fd53ab66-585d-4523-8bcf-116175ff8f5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360608460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wa
keup_race.3360608460
Directory /workspace/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.3624808675
Short name T807
Test name
Test status
Simulation time 86342700 ps
CPU time 0.68 seconds
Started May 23 03:36:27 PM PDT 24
Finished May 23 03:36:32 PM PDT 24
Peak memory 198664 kb
Host smart-6ebe56fb-969a-484b-9d9c-543e7f00176a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624808675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.3624808675
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.3543134399
Short name T344
Test name
Test status
Simulation time 148871827 ps
CPU time 0.84 seconds
Started May 23 03:36:29 PM PDT 24
Finished May 23 03:36:34 PM PDT 24
Peak memory 208908 kb
Host smart-3b37f548-68c3-4df6-80d9-edb57874a4a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543134399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.3543134399
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.3003015984
Short name T787
Test name
Test status
Simulation time 128679410 ps
CPU time 0.96 seconds
Started May 23 03:36:29 PM PDT 24
Finished May 23 03:36:34 PM PDT 24
Peak memory 199464 kb
Host smart-4fef840f-25af-4ef8-a5f9-d29b406b3887
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003015984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_c
m_ctrl_config_regwen.3003015984
Directory /workspace/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1605666738
Short name T976
Test name
Test status
Simulation time 1600958878 ps
CPU time 2.45 seconds
Started May 23 03:36:21 PM PDT 24
Finished May 23 03:36:30 PM PDT 24
Peak memory 200664 kb
Host smart-c011f8a2-abca-4ec0-ab70-19316cb87923
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605666738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1605666738
Directory /workspace/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3350198832
Short name T371
Test name
Test status
Simulation time 781252350 ps
CPU time 2.75 seconds
Started May 23 03:36:21 PM PDT 24
Finished May 23 03:36:30 PM PDT 24
Peak memory 200608 kb
Host smart-59a74312-ad64-49e9-b37d-16d40fc40b42
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350198832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3350198832
Directory /workspace/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1365652294
Short name T580
Test name
Test status
Simulation time 68217491 ps
CPU time 0.84 seconds
Started May 23 03:36:26 PM PDT 24
Finished May 23 03:36:32 PM PDT 24
Peak memory 198796 kb
Host smart-64997d1e-ee5a-4435-bcc9-beb5d4e51e36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365652294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1365652294
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.3663870054
Short name T824
Test name
Test status
Simulation time 29543704 ps
CPU time 0.67 seconds
Started May 23 03:36:23 PM PDT 24
Finished May 23 03:36:30 PM PDT 24
Peak memory 198876 kb
Host smart-e79b8e06-84dd-4b79-bd34-12a7c345ddc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663870054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.3663870054
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all.3573726737
Short name T115
Test name
Test status
Simulation time 1473184511 ps
CPU time 6.49 seconds
Started May 23 03:36:34 PM PDT 24
Finished May 23 03:36:43 PM PDT 24
Peak memory 200676 kb
Host smart-62dfde81-1c92-4ccf-b65a-ef3876b13988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573726737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.3573726737
Directory /workspace/8.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all_with_rand_reset.749456783
Short name T121
Test name
Test status
Simulation time 6767305956 ps
CPU time 23.13 seconds
Started May 23 03:36:26 PM PDT 24
Finished May 23 03:36:55 PM PDT 24
Peak memory 200908 kb
Host smart-530d7dea-81f8-4d75-8dc1-65ccde81a070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749456783 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all_with_rand_reset.749456783
Directory /workspace/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup.1714821360
Short name T194
Test name
Test status
Simulation time 53889518 ps
CPU time 0.74 seconds
Started May 23 03:36:29 PM PDT 24
Finished May 23 03:36:34 PM PDT 24
Peak memory 197844 kb
Host smart-47a1b0ec-b75e-46f6-8e7d-17780d7dd8e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714821360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.1714821360
Directory /workspace/8.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup_reset.3674719232
Short name T390
Test name
Test status
Simulation time 220891778 ps
CPU time 1.37 seconds
Started May 23 03:36:22 PM PDT 24
Finished May 23 03:36:29 PM PDT 24
Peak memory 199784 kb
Host smart-ecedbd35-a092-4e4a-ace4-21c2b9ced582
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674719232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.3674719232
Directory /workspace/8.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.2824392366
Short name T381
Test name
Test status
Simulation time 36382568 ps
CPU time 0.82 seconds
Started May 23 03:36:36 PM PDT 24
Finished May 23 03:36:39 PM PDT 24
Peak memory 198452 kb
Host smart-8d9e10b0-ce2f-42f3-a18c-dd6d80fe98ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824392366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.2824392366
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.3235666370
Short name T316
Test name
Test status
Simulation time 63710746 ps
CPU time 0.68 seconds
Started May 23 03:36:37 PM PDT 24
Finished May 23 03:36:42 PM PDT 24
Peak memory 198636 kb
Host smart-d0de6bd5-f56e-4f5b-9d00-e85576520a2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235666370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.3235666370
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3448366092
Short name T772
Test name
Test status
Simulation time 30728602 ps
CPU time 0.68 seconds
Started May 23 03:36:36 PM PDT 24
Finished May 23 03:36:39 PM PDT 24
Peak memory 197548 kb
Host smart-2f013d4d-964f-4c8c-996c-68c1c8ba6891
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448366092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.3448366092
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.3217626506
Short name T828
Test name
Test status
Simulation time 161089916 ps
CPU time 0.93 seconds
Started May 23 03:36:32 PM PDT 24
Finished May 23 03:36:36 PM PDT 24
Peak memory 197612 kb
Host smart-b69a210c-2374-401d-9820-18768f524ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217626506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.3217626506
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.533988453
Short name T444
Test name
Test status
Simulation time 46131643 ps
CPU time 0.61 seconds
Started May 23 03:36:39 PM PDT 24
Finished May 23 03:36:43 PM PDT 24
Peak memory 196848 kb
Host smart-aece5fc1-96dc-40df-a474-2fd2cf2e1bfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533988453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.533988453
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.2487124563
Short name T970
Test name
Test status
Simulation time 101794939 ps
CPU time 0.63 seconds
Started May 23 03:36:35 PM PDT 24
Finished May 23 03:36:38 PM PDT 24
Peak memory 197580 kb
Host smart-1a39d5bf-9f06-41d2-bcfd-3ba9a49915f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487124563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.2487124563
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.3897188710
Short name T685
Test name
Test status
Simulation time 43296554 ps
CPU time 0.7 seconds
Started May 23 03:36:41 PM PDT 24
Finished May 23 03:36:47 PM PDT 24
Peak memory 200860 kb
Host smart-29b97f4c-52ed-41b5-be59-ee3f5ef609b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897188710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.3897188710
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.1866577669
Short name T464
Test name
Test status
Simulation time 207071361 ps
CPU time 1.05 seconds
Started May 23 03:36:37 PM PDT 24
Finished May 23 03:36:41 PM PDT 24
Peak memory 199184 kb
Host smart-66f1dde0-24a8-4188-81e1-390965ab4468
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866577669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wa
keup_race.1866577669
Directory /workspace/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.3939365192
Short name T38
Test name
Test status
Simulation time 32395735 ps
CPU time 0.72 seconds
Started May 23 03:36:34 PM PDT 24
Finished May 23 03:36:37 PM PDT 24
Peak memory 198112 kb
Host smart-4b2a3ec9-e779-4fe4-b89f-f37571f6abeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939365192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.3939365192
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.552349076
Short name T851
Test name
Test status
Simulation time 167090327 ps
CPU time 0.88 seconds
Started May 23 03:36:35 PM PDT 24
Finished May 23 03:36:38 PM PDT 24
Peak memory 208916 kb
Host smart-90724453-1d4d-4884-9965-f0875c0cf43d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552349076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.552349076
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.779631449
Short name T653
Test name
Test status
Simulation time 160189034 ps
CPU time 1.07 seconds
Started May 23 03:36:36 PM PDT 24
Finished May 23 03:36:40 PM PDT 24
Peak memory 199472 kb
Host smart-edb14c2e-bb5b-4912-8276-09b0bd036182
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779631449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm
_ctrl_config_regwen.779631449
Directory /workspace/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.884427419
Short name T211
Test name
Test status
Simulation time 2088303219 ps
CPU time 2.04 seconds
Started May 23 03:36:38 PM PDT 24
Finished May 23 03:36:43 PM PDT 24
Peak memory 200576 kb
Host smart-6e07001d-b45c-48b5-bff0-4f40ff11c7e1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884427419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.884427419
Directory /workspace/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3929918390
Short name T997
Test name
Test status
Simulation time 937932979 ps
CPU time 2.37 seconds
Started May 23 03:36:37 PM PDT 24
Finished May 23 03:36:43 PM PDT 24
Peak memory 200532 kb
Host smart-01c7d9cd-ce0e-4cfc-91bb-5b0cd4b618db
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929918390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3929918390
Directory /workspace/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1565105160
Short name T950
Test name
Test status
Simulation time 75947010 ps
CPU time 0.95 seconds
Started May 23 03:36:36 PM PDT 24
Finished May 23 03:36:40 PM PDT 24
Peak memory 198728 kb
Host smart-3b025ce6-bdf5-4f32-919a-bb0adf26eb1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565105160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1565105160
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.3358375204
Short name T445
Test name
Test status
Simulation time 60223269 ps
CPU time 0.65 seconds
Started May 23 03:36:34 PM PDT 24
Finished May 23 03:36:37 PM PDT 24
Peak memory 198880 kb
Host smart-46f75de4-7995-4639-91ab-0cbee7b017d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358375204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.3358375204
Directory /workspace/9.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all.1832505014
Short name T28
Test name
Test status
Simulation time 2744914362 ps
CPU time 3.58 seconds
Started May 23 03:36:34 PM PDT 24
Finished May 23 03:36:40 PM PDT 24
Peak memory 200732 kb
Host smart-023ce001-c4de-409d-aace-d8e73db8e40a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832505014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.1832505014
Directory /workspace/9.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all_with_rand_reset.3683913009
Short name T896
Test name
Test status
Simulation time 4954610811 ps
CPU time 18.48 seconds
Started May 23 03:36:37 PM PDT 24
Finished May 23 03:36:58 PM PDT 24
Peak memory 200876 kb
Host smart-3c6d64a6-348d-4204-9ca6-d3bd5f620d0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683913009 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all_with_rand_reset.3683913009
Directory /workspace/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup.1481614234
Short name T795
Test name
Test status
Simulation time 91693634 ps
CPU time 0.8 seconds
Started May 23 03:36:40 PM PDT 24
Finished May 23 03:36:46 PM PDT 24
Peak memory 198608 kb
Host smart-bcb1fd1d-8fff-4b36-9345-608abf459626
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481614234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.1481614234
Directory /workspace/9.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup_reset.1038114091
Short name T662
Test name
Test status
Simulation time 286832468 ps
CPU time 1.21 seconds
Started May 23 03:36:34 PM PDT 24
Finished May 23 03:36:37 PM PDT 24
Peak memory 199812 kb
Host smart-2d35c1ef-b859-4221-9029-76583c33839a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038114091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.1038114091
Directory /workspace/9.pwrmgr_wakeup_reset/latest
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