Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33666

1

T3

2

T4

6

T6

77

auto[1]

32146

1

T3

4

T4

4

T6

90

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33581

1

T4

4

T6

92

T8

1

auto[1]

32231

1

T3

6

T4

6

T6

75

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32282

1

T3

5

T4

2

T6

77

auto[1]

33530

1

T3

1

T4

8

T6

90

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37679

1

T3

4

T4

5

T6

102

auto[1]

28133

1

T3

2

T4

5

T6

65

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32076

1

T3

1

T4

6

T6

85

auto[1]

33736

1

T3

5

T4

4

T6

82

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33677

1

T3

3

T4

6

T6

83

auto[1]

32135

1

T3

3

T4

4

T6

84

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1152

1

T4

1

T6

2

T9

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

900

1

T4

1

T6

1

T9

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1166

1

T6

4

T9

1

T14

9

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

862

1

T6

2

T9

1

T14

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1154

1

T6

3

T9

2

T14

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

871

1

T6

1

T9

2

T14

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1817

1

T6

9

T9

4

T14

18

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1526

1

T6

9

T9

4

T14

15

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1132

1

T6

2

T8

1

T14

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

862

1

T6

2

T14

8

T21

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1201

1

T6

3

T9

1

T14

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

850

1

T6

2

T9

1

T14

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1112

1

T6

3

T9

2

T14

13

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

801

1

T6

1

T9

2

T14

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1161

1

T9

4

T14

6

T21

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

865

1

T9

4

T14

6

T21

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1113

1

T6

1

T9

1

T14

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

812

1

T6

1

T9

1

T14

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1173

1

T6

2

T9

2

T14

13

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

879

1

T6

2

T9

2

T14

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1207

1

T6

3

T14

8

T21

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

888

1

T6

2

T14

7

T21

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1144

1

T3

1

T6

2

T9

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

853

1

T6

1

T9

1

T14

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1184

1

T3

1

T6

3

T9

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

874

1

T6

3

T9

3

T14

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1144

1

T4

2

T6

4

T9

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

865

1

T4

2

T6

1

T9

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1167

1

T6

2

T9

2

T14

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

861

1

T9

2

T14

4

T21

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1181

1

T6

4

T9

1

T14

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

889

1

T6

2

T9

1

T14

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1166

1

T6

4

T9

5

T14

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

861

1

T6

2

T9

5

T14

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1139

1

T6

3

T9

1

T14

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

851

1

T9

1

T14

6

T21

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1218

1

T6

4

T9

2

T14

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

894

1

T6

4

T9

2

T14

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1113

1

T4

1

T6

2

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

839

1

T4

1

T9

1

T14

9

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1139

1

T6

3

T9

2

T14

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

828

1

T6

2

T9

2

T14

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1150

1

T6

7

T9

2

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

877

1

T6

5

T9

2

T14

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1166

1

T6

5

T9

2

T14

10

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

870

1

T6

3

T9

2

T14

10

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1155

1

T6

2

T9

3

T14

9

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

883

1

T6

2

T9

3

T14

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1120

1

T6

3

T9

1

T10

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

845

1

T6

2

T9

1

T14

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1154

1

T6

4

T14

12

T21

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

839

1

T6

2

T14

7

T21

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1218

1

T3

1

T6

2

T8

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

889

1

T3

1

T6

2

T8

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1154

1

T4

1

T6

2

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

860

1

T4

1

T6

2

T9

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1119

1

T6

5

T8

1

T9

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

814

1

T6

3

T8

1

T9

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1158

1

T6

3

T10

1

T14

12

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

847

1

T6

2

T14

6

T21

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1186

1

T3

1

T6

2

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

859

1

T3

1

T6

1

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1116

1

T6

4

T10

1

T14

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

819

1

T6

3

T14

4

T38

3