Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30849 1 T2 1 T7 6 T9 54
auto[1] 29810 1 T2 2 T9 46 T13 424


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30923 1 T2 1 T7 3 T9 52
auto[1] 29736 1 T2 2 T7 3 T9 48


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29520 1 T2 3 T7 4 T9 44
auto[1] 31139 1 T7 2 T9 56 T13 443


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34667 1 T2 3 T7 4 T9 50
auto[1] 25992 1 T7 2 T9 50 T13 389


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29352 1 T2 3 T7 2 T9 40
auto[1] 31307 1 T7 4 T9 60 T13 443


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30931 1 T2 1 T7 5 T9 48
auto[1] 29728 1 T2 2 T7 1 T9 52


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1056 1 T9 1 T13 14 T20 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 779 1 T9 1 T13 11 T20 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1093 1 T7 1 T13 16 T20 3
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 818 1 T13 13 T20 3 T21 6
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1128 1 T7 1 T9 1 T13 17
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 869 1 T7 1 T9 1 T13 11
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1643 1 T9 3 T13 21 T21 4
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1378 1 T9 3 T13 19 T21 3
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1042 1 T13 13 T21 6 T22 10
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 779 1 T13 10 T21 3 T22 6
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1095 1 T9 1 T13 8 T20 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 825 1 T9 1 T13 5 T20 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1032 1 T9 2 T13 15 T20 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 764 1 T9 2 T13 14 T20 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1047 1 T9 5 T13 22 T14 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 773 1 T9 5 T13 16 T21 6
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1038 1 T9 1 T13 16 T21 9
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 782 1 T9 1 T13 15 T21 7
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1025 1 T9 3 T13 14 T20 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 759 1 T9 3 T13 12 T20 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1103 1 T7 1 T9 1 T13 13
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 833 1 T7 1 T9 1 T13 12
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1045 1 T9 3 T13 15 T20 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 779 1 T9 3 T13 13 T20 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1069 1 T2 1 T9 1 T13 14
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 795 1 T9 1 T13 12 T20 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1052 1 T7 1 T9 1 T13 21
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 783 1 T9 1 T13 18 T20 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1054 1 T9 2 T13 14 T20 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 763 1 T9 2 T13 12 T20 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1064 1 T9 2 T13 14 T20 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 784 1 T9 2 T13 10 T20 3
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 984 1 T2 1 T9 2 T13 9
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 737 1 T9 2 T13 7 T21 10
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1024 1 T9 2 T13 19 T20 4
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 774 1 T9 2 T13 15 T20 4
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1107 1 T9 1 T13 12 T21 18
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 829 1 T9 1 T13 10 T21 8
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1086 1 T9 1 T13 13 T20 3
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 826 1 T9 1 T13 11 T20 3
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1088 1 T9 3 T13 17 T20 2
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 805 1 T9 3 T13 16 T20 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1048 1 T9 1 T13 16 T20 7
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 766 1 T9 1 T13 13 T20 7
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1003 1 T9 2 T13 17 T20 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 738 1 T9 2 T13 9 T20 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1136 1 T9 1 T13 13 T20 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 851 1 T9 1 T13 8 T20 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1029 1 T9 1 T13 15 T21 10
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 754 1 T9 1 T13 12 T21 7
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1041 1 T13 15 T20 2 T21 12
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 785 1 T13 12 T20 2 T21 6
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1069 1 T9 2 T13 14 T20 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 774 1 T9 2 T13 10 T20 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1131 1 T9 2 T13 14 T20 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 853 1 T9 2 T13 12 T20 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1035 1 T2 1 T9 1 T13 18
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 765 1 T9 1 T13 14 T21 6
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1101 1 T9 2 T13 12 T14 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 826 1 T9 2 T13 9 T21 4
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1096 1 T9 1 T13 21 T20 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 821 1 T9 1 T13 17 T20 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1103 1 T9 1 T13 13 T20 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 825 1 T9 1 T13 11 T20 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%