Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31713 1 T1 8 T3 16 T4 542
auto[1] 30451 1 T1 10 T3 8 T4 533


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31811 1 T1 8 T3 12 T4 596
auto[1] 30353 1 T1 10 T3 12 T4 479


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30076 1 T1 10 T3 2 T4 501
auto[1] 32088 1 T1 8 T3 22 T4 574


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35558 1 T1 9 T3 12 T4 600
auto[1] 26606 1 T1 9 T3 12 T4 475


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30378 1 T1 8 T3 16 T4 519
auto[1] 31786 1 T1 10 T3 8 T4 556


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31733 1 T1 16 T3 8 T4 598
auto[1] 30431 1 T1 2 T3 16 T4 477


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1088 1 T4 24 T5 4 T6 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 794 1 T4 21 T5 4 T6 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1067 1 T1 1 T3 1 T4 17
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 798 1 T1 1 T3 1 T4 14
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1051 1 T1 1 T4 16 T5 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 788 1 T1 1 T4 10 T5 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1758 1 T4 42 T5 3 T6 3
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1492 1 T4 37 T5 3 T6 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1093 1 T4 20 T6 1 T10 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 793 1 T4 16 T6 1 T10 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1077 1 T3 2 T4 20 T10 4
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 813 1 T3 2 T4 15 T10 4
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1134 1 T4 18 T5 4 T6 4
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 865 1 T4 17 T5 4 T6 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1058 1 T3 1 T4 8 T6 3
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 810 1 T3 1 T4 8 T6 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1066 1 T4 13 T5 3 T6 5
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 787 1 T4 9 T5 3 T6 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1129 1 T3 1 T4 21 T6 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 848 1 T3 1 T4 15 T6 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1090 1 T1 1 T4 11 T5 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 812 1 T1 1 T4 9 T5 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1097 1 T3 1 T4 21 T6 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 840 1 T3 1 T4 13 T6 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1096 1 T4 18 T6 2 T14 14
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 788 1 T4 11 T6 1 T14 9
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1096 1 T3 1 T4 20 T5 3
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 834 1 T3 1 T4 18 T5 3
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1092 1 T1 1 T4 11 T5 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 807 1 T1 1 T4 7 T5 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1072 1 T3 1 T4 24 T5 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 780 1 T3 1 T4 18 T5 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1081 1 T4 24 T5 2 T6 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 787 1 T4 20 T5 2 T6 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1111 1 T1 2 T4 18 T6 4
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 839 1 T1 2 T4 16 T6 3
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1074 1 T4 25 T5 1 T10 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 791 1 T4 21 T5 1 T10 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1103 1 T4 25 T5 1 T6 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 839 1 T4 20 T5 1 T7 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1138 1 T3 1 T4 19 T6 6
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 839 1 T3 1 T4 16 T6 3
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1123 1 T4 12 T5 2 T6 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 803 1 T4 9 T5 2 T10 4
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1077 1 T4 19 T5 2 T6 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 795 1 T4 15 T5 2 T6 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1106 1 T3 1 T4 20 T5 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 826 1 T3 1 T4 14 T5 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1051 1 T1 1 T4 23 T6 4
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 798 1 T1 1 T4 20 T6 3
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1101 1 T3 1 T4 14 T5 2
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 826 1 T3 1 T4 13 T5 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1047 1 T1 1 T4 12 T5 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 770 1 T1 1 T4 10 T5 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1153 1 T1 1 T4 25 T5 5
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 857 1 T1 1 T4 19 T5 5
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1034 1 T4 8 T5 3 T6 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 771 1 T4 6 T5 3 T6 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1109 1 T3 1 T4 16 T5 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 800 1 T3 1 T4 13 T5 2
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1086 1 T4 19 T6 3 T14 16
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 793 1 T4 13 T14 13 T22 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1100 1 T4 17 T5 1 T6 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 823 1 T4 12 T5 1 T6 1

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