Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02


Total test records in report: 1117
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T804 /workspace/coverage/default/24.pwrmgr_smoke.2836125450 May 30 02:37:43 PM PDT 24 May 30 02:37:49 PM PDT 24 41672474 ps
T805 /workspace/coverage/default/18.pwrmgr_smoke.1479357299 May 30 02:37:29 PM PDT 24 May 30 02:37:36 PM PDT 24 46155423 ps
T806 /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.2729615402 May 30 02:37:26 PM PDT 24 May 30 02:37:32 PM PDT 24 158374686 ps
T807 /workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3224886661 May 30 02:38:13 PM PDT 24 May 30 02:38:18 PM PDT 24 766563649 ps
T808 /workspace/coverage/default/48.pwrmgr_reset_invalid.2586951604 May 30 02:38:35 PM PDT 24 May 30 02:38:41 PM PDT 24 166336539 ps
T809 /workspace/coverage/default/47.pwrmgr_reset.1789407990 May 30 02:38:55 PM PDT 24 May 30 02:38:57 PM PDT 24 72595682 ps
T810 /workspace/coverage/default/7.pwrmgr_reset.1036974145 May 30 02:36:55 PM PDT 24 May 30 02:36:57 PM PDT 24 58614606 ps
T811 /workspace/coverage/default/18.pwrmgr_reset.1619937053 May 30 02:37:27 PM PDT 24 May 30 02:37:33 PM PDT 24 44742163 ps
T812 /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2756832065 May 30 02:37:57 PM PDT 24 May 30 02:38:00 PM PDT 24 30516222 ps
T813 /workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2673958034 May 30 02:36:41 PM PDT 24 May 30 02:36:47 PM PDT 24 1742120295 ps
T814 /workspace/coverage/default/24.pwrmgr_global_esc.1975550168 May 30 02:37:37 PM PDT 24 May 30 02:37:44 PM PDT 24 76766164 ps
T815 /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2743773449 May 30 02:37:10 PM PDT 24 May 30 02:37:15 PM PDT 24 895343870 ps
T816 /workspace/coverage/default/47.pwrmgr_escalation_timeout.286850430 May 30 02:38:52 PM PDT 24 May 30 02:38:54 PM PDT 24 161867583 ps
T817 /workspace/coverage/default/39.pwrmgr_wakeup.2616070105 May 30 02:38:25 PM PDT 24 May 30 02:38:33 PM PDT 24 56778799 ps
T818 /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4210650000 May 30 02:38:07 PM PDT 24 May 30 02:38:12 PM PDT 24 784125777 ps
T819 /workspace/coverage/default/24.pwrmgr_escalation_timeout.1628622071 May 30 02:37:43 PM PDT 24 May 30 02:37:50 PM PDT 24 162000488 ps
T820 /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.797251539 May 30 02:37:28 PM PDT 24 May 30 02:37:36 PM PDT 24 284584481 ps
T821 /workspace/coverage/default/0.pwrmgr_global_esc.4270551947 May 30 02:36:33 PM PDT 24 May 30 02:36:37 PM PDT 24 48415997 ps
T822 /workspace/coverage/default/31.pwrmgr_glitch.474768034 May 30 02:38:03 PM PDT 24 May 30 02:38:06 PM PDT 24 49090045 ps
T823 /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.765859885 May 30 02:37:28 PM PDT 24 May 30 02:37:36 PM PDT 24 207268374 ps
T824 /workspace/coverage/default/36.pwrmgr_stress_all_with_rand_reset.1606309415 May 30 02:38:25 PM PDT 24 May 30 02:38:39 PM PDT 24 3480453371 ps
T825 /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1174463186 May 30 02:38:33 PM PDT 24 May 30 02:38:40 PM PDT 24 30105077 ps
T826 /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.2361696540 May 30 02:37:12 PM PDT 24 May 30 02:37:16 PM PDT 24 37273574 ps
T827 /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.2283679047 May 30 02:37:16 PM PDT 24 May 30 02:37:21 PM PDT 24 62194238 ps
T828 /workspace/coverage/default/34.pwrmgr_lowpower_invalid.1429500117 May 30 02:38:19 PM PDT 24 May 30 02:38:23 PM PDT 24 63789650 ps
T829 /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.968460397 May 30 02:38:04 PM PDT 24 May 30 02:38:07 PM PDT 24 38752302 ps
T830 /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2378182561 May 30 02:37:12 PM PDT 24 May 30 02:37:15 PM PDT 24 54814206 ps
T831 /workspace/coverage/default/11.pwrmgr_lowpower_invalid.3943067797 May 30 02:37:15 PM PDT 24 May 30 02:37:20 PM PDT 24 70130843 ps
T832 /workspace/coverage/default/26.pwrmgr_smoke.1448695611 May 30 02:37:36 PM PDT 24 May 30 02:37:44 PM PDT 24 66250688 ps
T833 /workspace/coverage/default/35.pwrmgr_lowpower_invalid.2811697199 May 30 02:38:25 PM PDT 24 May 30 02:38:33 PM PDT 24 81455410 ps
T834 /workspace/coverage/default/33.pwrmgr_wakeup.3854548149 May 30 02:38:25 PM PDT 24 May 30 02:38:33 PM PDT 24 193372932 ps
T835 /workspace/coverage/default/45.pwrmgr_lowpower_invalid.3334078841 May 30 02:38:40 PM PDT 24 May 30 02:38:45 PM PDT 24 77647391 ps
T836 /workspace/coverage/default/38.pwrmgr_reset.2912732509 May 30 02:38:15 PM PDT 24 May 30 02:38:18 PM PDT 24 74077091 ps
T837 /workspace/coverage/default/15.pwrmgr_glitch.2890789148 May 30 02:37:13 PM PDT 24 May 30 02:37:18 PM PDT 24 61940811 ps
T838 /workspace/coverage/default/0.pwrmgr_wakeup.74586499 May 30 02:36:29 PM PDT 24 May 30 02:36:33 PM PDT 24 114072053 ps
T839 /workspace/coverage/default/43.pwrmgr_escalation_timeout.1700824391 May 30 02:38:26 PM PDT 24 May 30 02:38:35 PM PDT 24 163656380 ps
T840 /workspace/coverage/default/44.pwrmgr_reset_invalid.3087920024 May 30 02:38:39 PM PDT 24 May 30 02:38:44 PM PDT 24 96658483 ps
T841 /workspace/coverage/default/40.pwrmgr_reset_invalid.1862033705 May 30 02:38:30 PM PDT 24 May 30 02:38:38 PM PDT 24 112398857 ps
T842 /workspace/coverage/default/37.pwrmgr_glitch.1383021111 May 30 02:38:27 PM PDT 24 May 30 02:38:36 PM PDT 24 63464444 ps
T843 /workspace/coverage/default/26.pwrmgr_glitch.2411876432 May 30 02:37:46 PM PDT 24 May 30 02:37:53 PM PDT 24 43179226 ps
T844 /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.903690585 May 30 02:36:38 PM PDT 24 May 30 02:36:42 PM PDT 24 109087671 ps
T845 /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.456680263 May 30 02:37:17 PM PDT 24 May 30 02:37:22 PM PDT 24 31289596 ps
T846 /workspace/coverage/default/20.pwrmgr_global_esc.3664711776 May 30 02:37:27 PM PDT 24 May 30 02:37:34 PM PDT 24 75459169 ps
T847 /workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.4119537363 May 30 02:38:22 PM PDT 24 May 30 02:38:29 PM PDT 24 166446940 ps
T848 /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3008431550 May 30 02:36:28 PM PDT 24 May 30 02:36:34 PM PDT 24 876882602 ps
T849 /workspace/coverage/default/27.pwrmgr_lowpower_wakeup_race.2507383269 May 30 02:37:43 PM PDT 24 May 30 02:37:50 PM PDT 24 87481638 ps
T850 /workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1889846225 May 30 02:38:39 PM PDT 24 May 30 02:38:45 PM PDT 24 882002020 ps
T851 /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.3869728665 May 30 02:36:56 PM PDT 24 May 30 02:36:59 PM PDT 24 70370090 ps
T852 /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1103735975 May 30 02:38:01 PM PDT 24 May 30 02:38:06 PM PDT 24 1278328820 ps
T853 /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2311694078 May 30 02:36:39 PM PDT 24 May 30 02:36:45 PM PDT 24 975715108 ps
T854 /workspace/coverage/default/10.pwrmgr_smoke.1187397316 May 30 02:37:11 PM PDT 24 May 30 02:37:13 PM PDT 24 61513631 ps
T855 /workspace/coverage/default/9.pwrmgr_wakeup_reset.2599380830 May 30 02:37:01 PM PDT 24 May 30 02:37:04 PM PDT 24 445599405 ps
T856 /workspace/coverage/default/16.pwrmgr_lowpower_invalid.2548864146 May 30 02:37:26 PM PDT 24 May 30 02:37:32 PM PDT 24 43593284 ps
T857 /workspace/coverage/default/31.pwrmgr_reset.2653162718 May 30 02:38:00 PM PDT 24 May 30 02:38:03 PM PDT 24 70352976 ps
T858 /workspace/coverage/default/12.pwrmgr_wakeup_reset.2445227023 May 30 02:37:10 PM PDT 24 May 30 02:37:12 PM PDT 24 167055738 ps
T859 /workspace/coverage/default/17.pwrmgr_smoke.3549398172 May 30 02:37:12 PM PDT 24 May 30 02:37:15 PM PDT 24 60446652 ps
T860 /workspace/coverage/default/41.pwrmgr_reset_invalid.1160467246 May 30 02:38:28 PM PDT 24 May 30 02:38:37 PM PDT 24 128134205 ps
T861 /workspace/coverage/default/6.pwrmgr_stress_all_with_rand_reset.799656676 May 30 02:36:59 PM PDT 24 May 30 02:37:24 PM PDT 24 9248387136 ps
T862 /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3468528406 May 30 02:38:16 PM PDT 24 May 30 02:38:21 PM PDT 24 1188245633 ps
T863 /workspace/coverage/default/32.pwrmgr_reset_invalid.2402130745 May 30 02:38:21 PM PDT 24 May 30 02:38:27 PM PDT 24 113503548 ps
T864 /workspace/coverage/default/4.pwrmgr_global_esc.4273843084 May 30 02:36:39 PM PDT 24 May 30 02:36:43 PM PDT 24 71119908 ps
T865 /workspace/coverage/default/6.pwrmgr_glitch.971362999 May 30 02:37:01 PM PDT 24 May 30 02:37:05 PM PDT 24 34616294 ps
T866 /workspace/coverage/default/37.pwrmgr_reset_invalid.2633398403 May 30 02:38:19 PM PDT 24 May 30 02:38:24 PM PDT 24 162908767 ps
T867 /workspace/coverage/default/8.pwrmgr_aborted_low_power.2864131916 May 30 02:37:01 PM PDT 24 May 30 02:37:05 PM PDT 24 41609689 ps
T868 /workspace/coverage/default/17.pwrmgr_aborted_low_power.1395759022 May 30 02:37:25 PM PDT 24 May 30 02:37:31 PM PDT 24 82316572 ps
T869 /workspace/coverage/default/39.pwrmgr_smoke.3074370205 May 30 02:38:26 PM PDT 24 May 30 02:38:35 PM PDT 24 32169422 ps
T870 /workspace/coverage/default/25.pwrmgr_stress_all.3748430952 May 30 02:37:39 PM PDT 24 May 30 02:37:49 PM PDT 24 2504792538 ps
T871 /workspace/coverage/default/20.pwrmgr_glitch.2235006791 May 30 02:37:27 PM PDT 24 May 30 02:37:33 PM PDT 24 73335115 ps
T872 /workspace/coverage/default/30.pwrmgr_stress_all.3207955316 May 30 02:38:05 PM PDT 24 May 30 02:38:10 PM PDT 24 677688547 ps
T873 /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.3227474674 May 30 02:37:38 PM PDT 24 May 30 02:37:46 PM PDT 24 65700657 ps
T874 /workspace/coverage/default/5.pwrmgr_stress_all.1583058806 May 30 02:36:45 PM PDT 24 May 30 02:36:51 PM PDT 24 566553438 ps
T875 /workspace/coverage/default/42.pwrmgr_global_esc.2399737699 May 30 02:38:30 PM PDT 24 May 30 02:38:37 PM PDT 24 44808062 ps
T876 /workspace/coverage/default/2.pwrmgr_reset_invalid.2841734417 May 30 02:36:40 PM PDT 24 May 30 02:36:45 PM PDT 24 114130091 ps
T877 /workspace/coverage/default/23.pwrmgr_reset.1995117532 May 30 02:37:44 PM PDT 24 May 30 02:37:51 PM PDT 24 132930667 ps
T878 /workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.139943551 May 30 02:37:34 PM PDT 24 May 30 02:37:44 PM PDT 24 802971917 ps
T879 /workspace/coverage/default/21.pwrmgr_aborted_low_power.2760571727 May 30 02:37:21 PM PDT 24 May 30 02:37:27 PM PDT 24 147043232 ps
T880 /workspace/coverage/default/0.pwrmgr_reset_invalid.2532703310 May 30 02:36:30 PM PDT 24 May 30 02:36:34 PM PDT 24 181820135 ps
T881 /workspace/coverage/default/42.pwrmgr_stress_all.1619430316 May 30 02:38:32 PM PDT 24 May 30 02:38:42 PM PDT 24 1835204692 ps
T882 /workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2078549283 May 30 02:36:48 PM PDT 24 May 30 02:36:53 PM PDT 24 1207748609 ps
T883 /workspace/coverage/default/15.pwrmgr_reset_invalid.1484234535 May 30 02:37:13 PM PDT 24 May 30 02:37:16 PM PDT 24 127656205 ps
T884 /workspace/coverage/default/44.pwrmgr_smoke.3418589779 May 30 02:38:33 PM PDT 24 May 30 02:38:40 PM PDT 24 30782469 ps
T885 /workspace/coverage/default/30.pwrmgr_wakeup_reset.1335888137 May 30 02:38:08 PM PDT 24 May 30 02:38:11 PM PDT 24 260226605 ps
T886 /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2823823208 May 30 02:36:55 PM PDT 24 May 30 02:36:57 PM PDT 24 54351709 ps
T887 /workspace/coverage/default/15.pwrmgr_escalation_timeout.1654501670 May 30 02:37:17 PM PDT 24 May 30 02:37:23 PM PDT 24 635563923 ps
T888 /workspace/coverage/default/14.pwrmgr_glitch.1152042428 May 30 02:37:28 PM PDT 24 May 30 02:37:35 PM PDT 24 119461047 ps
T889 /workspace/coverage/default/46.pwrmgr_lowpower_invalid.3625216745 May 30 02:38:37 PM PDT 24 May 30 02:38:43 PM PDT 24 86849280 ps
T890 /workspace/coverage/default/9.pwrmgr_escalation_timeout.2993345931 May 30 02:37:15 PM PDT 24 May 30 02:37:21 PM PDT 24 317923497 ps
T891 /workspace/coverage/default/14.pwrmgr_wakeup_reset.848096409 May 30 02:37:11 PM PDT 24 May 30 02:37:15 PM PDT 24 150652168 ps
T892 /workspace/coverage/default/46.pwrmgr_escalation_timeout.1141308741 May 30 02:38:45 PM PDT 24 May 30 02:38:48 PM PDT 24 624019582 ps
T893 /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.3707874338 May 30 02:38:54 PM PDT 24 May 30 02:38:57 PM PDT 24 66208676 ps
T894 /workspace/coverage/default/6.pwrmgr_escalation_timeout.99657650 May 30 02:36:43 PM PDT 24 May 30 02:36:48 PM PDT 24 359165144 ps
T895 /workspace/coverage/default/13.pwrmgr_reset_invalid.3586184733 May 30 02:37:16 PM PDT 24 May 30 02:37:21 PM PDT 24 98367355 ps
T896 /workspace/coverage/default/17.pwrmgr_global_esc.2705948681 May 30 02:37:31 PM PDT 24 May 30 02:37:40 PM PDT 24 28055683 ps
T897 /workspace/coverage/default/39.pwrmgr_glitch.678255203 May 30 02:38:25 PM PDT 24 May 30 02:38:33 PM PDT 24 36434135 ps
T898 /workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2447316963 May 30 02:37:12 PM PDT 24 May 30 02:37:17 PM PDT 24 823450952 ps
T899 /workspace/coverage/default/23.pwrmgr_stress_all.2403516541 May 30 02:37:35 PM PDT 24 May 30 02:37:49 PM PDT 24 2882451686 ps
T900 /workspace/coverage/default/36.pwrmgr_reset.4195175933 May 30 02:38:18 PM PDT 24 May 30 02:38:21 PM PDT 24 82478403 ps
T901 /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2567036100 May 30 02:38:27 PM PDT 24 May 30 02:38:37 PM PDT 24 1011620767 ps
T902 /workspace/coverage/default/31.pwrmgr_stress_all_with_rand_reset.1566171650 May 30 02:38:13 PM PDT 24 May 30 02:38:22 PM PDT 24 5092247032 ps
T903 /workspace/coverage/default/1.pwrmgr_escalation_timeout.3563906628 May 30 02:36:27 PM PDT 24 May 30 02:36:31 PM PDT 24 546352597 ps
T904 /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.362881420 May 30 02:38:24 PM PDT 24 May 30 02:38:33 PM PDT 24 890117802 ps
T905 /workspace/coverage/default/8.pwrmgr_smoke.3259688348 May 30 02:37:01 PM PDT 24 May 30 02:37:05 PM PDT 24 54220897 ps
T906 /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.502128336 May 30 02:36:37 PM PDT 24 May 30 02:36:41 PM PDT 24 75975904 ps
T907 /workspace/coverage/default/6.pwrmgr_lowpower_invalid.331350133 May 30 02:37:01 PM PDT 24 May 30 02:37:05 PM PDT 24 112595581 ps
T908 /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2501508730 May 30 02:36:35 PM PDT 24 May 30 02:36:40 PM PDT 24 1635455618 ps
T909 /workspace/coverage/default/26.pwrmgr_lowpower_invalid.1302683176 May 30 02:37:54 PM PDT 24 May 30 02:37:59 PM PDT 24 77404309 ps
T910 /workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.3319201197 May 30 02:37:26 PM PDT 24 May 30 02:37:32 PM PDT 24 345132994 ps
T911 /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.2138994031 May 30 02:38:19 PM PDT 24 May 30 02:38:22 PM PDT 24 29031625 ps
T912 /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.1839776782 May 30 02:38:04 PM PDT 24 May 30 02:38:07 PM PDT 24 57863986 ps
T913 /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.919471467 May 30 02:37:30 PM PDT 24 May 30 02:37:38 PM PDT 24 80295603 ps
T914 /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.854785548 May 30 02:37:29 PM PDT 24 May 30 02:37:37 PM PDT 24 97675806 ps
T915 /workspace/coverage/default/7.pwrmgr_smoke.780489516 May 30 02:36:55 PM PDT 24 May 30 02:36:57 PM PDT 24 59984453 ps
T916 /workspace/coverage/default/34.pwrmgr_stress_all_with_rand_reset.1568154185 May 30 02:38:17 PM PDT 24 May 30 02:38:36 PM PDT 24 4916903463 ps
T917 /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1049961153 May 30 02:36:59 PM PDT 24 May 30 02:37:05 PM PDT 24 802014183 ps
T918 /workspace/coverage/default/16.pwrmgr_escalation_timeout.2896825430 May 30 02:37:28 PM PDT 24 May 30 02:37:36 PM PDT 24 320472675 ps
T919 /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1579330544 May 30 02:36:42 PM PDT 24 May 30 02:36:48 PM PDT 24 206175447 ps
T920 /workspace/coverage/default/45.pwrmgr_global_esc.2937806235 May 30 02:38:56 PM PDT 24 May 30 02:39:00 PM PDT 24 50191485 ps
T921 /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.673802357 May 30 02:38:17 PM PDT 24 May 30 02:38:21 PM PDT 24 81337502 ps
T922 /workspace/coverage/default/40.pwrmgr_wakeup.3648959889 May 30 02:38:24 PM PDT 24 May 30 02:38:31 PM PDT 24 367755478 ps
T923 /workspace/coverage/default/43.pwrmgr_wakeup_reset.4056328632 May 30 02:38:25 PM PDT 24 May 30 02:38:33 PM PDT 24 349009741 ps
T924 /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.5357345 May 30 02:37:12 PM PDT 24 May 30 02:37:16 PM PDT 24 807320618 ps
T925 /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1686102656 May 30 02:36:52 PM PDT 24 May 30 02:36:54 PM PDT 24 129061463 ps
T926 /workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3612545633 May 30 02:38:05 PM PDT 24 May 30 02:38:10 PM PDT 24 968382669 ps
T927 /workspace/coverage/default/7.pwrmgr_global_esc.726772791 May 30 02:36:58 PM PDT 24 May 30 02:37:01 PM PDT 24 45479061 ps
T928 /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.3847319123 May 30 02:36:44 PM PDT 24 May 30 02:36:48 PM PDT 24 74867378 ps
T929 /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.1670185097 May 30 02:38:03 PM PDT 24 May 30 02:38:07 PM PDT 24 67710081 ps
T930 /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.2732463592 May 30 02:37:12 PM PDT 24 May 30 02:37:15 PM PDT 24 37255156 ps
T931 /workspace/coverage/default/32.pwrmgr_global_esc.3257042215 May 30 02:38:14 PM PDT 24 May 30 02:38:16 PM PDT 24 59217176 ps
T932 /workspace/coverage/default/36.pwrmgr_escalation_timeout.268862710 May 30 02:38:19 PM PDT 24 May 30 02:38:24 PM PDT 24 159633984 ps
T933 /workspace/coverage/default/27.pwrmgr_global_esc.3403892465 May 30 02:37:44 PM PDT 24 May 30 02:37:51 PM PDT 24 85052076 ps
T934 /workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3993085016 May 30 02:38:21 PM PDT 24 May 30 02:38:28 PM PDT 24 1042275547 ps
T935 /workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2222432390 May 30 02:37:10 PM PDT 24 May 30 02:37:15 PM PDT 24 822543594 ps
T936 /workspace/coverage/default/2.pwrmgr_lowpower_invalid.445477756 May 30 02:36:37 PM PDT 24 May 30 02:36:40 PM PDT 24 77566465 ps
T937 /workspace/coverage/default/6.pwrmgr_stress_all.722375374 May 30 02:37:00 PM PDT 24 May 30 02:37:07 PM PDT 24 968400057 ps
T938 /workspace/coverage/default/7.pwrmgr_stress_all.1311104576 May 30 02:36:58 PM PDT 24 May 30 02:37:03 PM PDT 24 2373370894 ps
T939 /workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.2083897244 May 30 02:37:42 PM PDT 24 May 30 02:37:49 PM PDT 24 94664771 ps
T940 /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3209557131 May 30 02:38:38 PM PDT 24 May 30 02:38:43 PM PDT 24 28599499 ps
T941 /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.754504714 May 30 02:37:25 PM PDT 24 May 30 02:37:32 PM PDT 24 64520795 ps
T942 /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.4248449426 May 30 02:37:32 PM PDT 24 May 30 02:37:41 PM PDT 24 66341547 ps
T943 /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.1810753286 May 30 02:37:14 PM PDT 24 May 30 02:37:19 PM PDT 24 75243874 ps
T944 /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.659894340 May 30 02:38:22 PM PDT 24 May 30 02:38:28 PM PDT 24 52677374 ps
T945 /workspace/coverage/default/15.pwrmgr_global_esc.1556668843 May 30 02:37:17 PM PDT 24 May 30 02:37:23 PM PDT 24 48748784 ps
T946 /workspace/coverage/default/30.pwrmgr_stress_all_with_rand_reset.414758418 May 30 02:38:04 PM PDT 24 May 30 02:38:16 PM PDT 24 4425995246 ps
T947 /workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2376500737 May 30 02:37:27 PM PDT 24 May 30 02:37:36 PM PDT 24 965428420 ps
T948 /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2650511184 May 30 02:38:55 PM PDT 24 May 30 02:38:58 PM PDT 24 29800616 ps
T949 /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.3122400075 May 30 02:37:42 PM PDT 24 May 30 02:37:49 PM PDT 24 28737699 ps
T950 /workspace/coverage/default/29.pwrmgr_stress_all_with_rand_reset.1001625798 May 30 02:38:02 PM PDT 24 May 30 02:38:17 PM PDT 24 3730602628 ps
T951 /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.85177555 May 30 02:37:17 PM PDT 24 May 30 02:37:23 PM PDT 24 68731194 ps
T952 /workspace/coverage/default/33.pwrmgr_aborted_low_power.1533797684 May 30 02:38:16 PM PDT 24 May 30 02:38:19 PM PDT 24 26089158 ps
T953 /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.3818536413 May 30 02:38:18 PM PDT 24 May 30 02:38:21 PM PDT 24 89510519 ps
T954 /workspace/coverage/default/43.pwrmgr_smoke.4180564121 May 30 02:38:26 PM PDT 24 May 30 02:38:34 PM PDT 24 40348541 ps
T955 /workspace/coverage/default/14.pwrmgr_aborted_low_power.3509379962 May 30 02:37:18 PM PDT 24 May 30 02:37:24 PM PDT 24 47867515 ps
T956 /workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.253455463 May 30 02:38:27 PM PDT 24 May 30 02:38:36 PM PDT 24 174435261 ps
T957 /workspace/coverage/default/15.pwrmgr_lowpower_invalid.635064967 May 30 02:37:19 PM PDT 24 May 30 02:37:26 PM PDT 24 81637857 ps
T958 /workspace/coverage/default/48.pwrmgr_aborted_low_power.918765159 May 30 02:38:34 PM PDT 24 May 30 02:38:41 PM PDT 24 70612401 ps
T959 /workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4264534520 May 30 02:38:25 PM PDT 24 May 30 02:38:34 PM PDT 24 971471181 ps
T960 /workspace/coverage/default/30.pwrmgr_aborted_low_power.582055789 May 30 02:38:02 PM PDT 24 May 30 02:38:05 PM PDT 24 35576198 ps
T961 /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.1488586643 May 30 02:37:14 PM PDT 24 May 30 02:37:19 PM PDT 24 36539133 ps
T962 /workspace/coverage/default/12.pwrmgr_reset.3091517888 May 30 02:37:17 PM PDT 24 May 30 02:37:23 PM PDT 24 52087759 ps
T963 /workspace/coverage/default/23.pwrmgr_glitch.1862058184 May 30 02:37:34 PM PDT 24 May 30 02:37:42 PM PDT 24 37737412 ps
T964 /workspace/coverage/default/35.pwrmgr_glitch.2432960451 May 30 02:38:18 PM PDT 24 May 30 02:38:22 PM PDT 24 75666142 ps
T965 /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.81471917 May 30 02:38:31 PM PDT 24 May 30 02:38:39 PM PDT 24 29058096 ps
T966 /workspace/coverage/default/14.pwrmgr_smoke.3147294241 May 30 02:37:16 PM PDT 24 May 30 02:37:21 PM PDT 24 28086568 ps
T967 /workspace/coverage/default/19.pwrmgr_wakeup.2000947121 May 30 02:37:29 PM PDT 24 May 30 02:37:37 PM PDT 24 134380243 ps
T968 /workspace/coverage/default/19.pwrmgr_stress_all_with_rand_reset.866384063 May 30 02:37:29 PM PDT 24 May 30 02:37:56 PM PDT 24 16300519215 ps
T969 /workspace/coverage/default/49.pwrmgr_reset.1220800086 May 30 02:38:46 PM PDT 24 May 30 02:38:50 PM PDT 24 68840911 ps
T970 /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1446879098 May 30 02:36:56 PM PDT 24 May 30 02:36:59 PM PDT 24 998397972 ps
T971 /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3893933664 May 30 02:38:22 PM PDT 24 May 30 02:38:31 PM PDT 24 841239772 ps
T972 /workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2175262512 May 30 02:37:13 PM PDT 24 May 30 02:37:19 PM PDT 24 825979739 ps
T973 /workspace/coverage/default/9.pwrmgr_reset_invalid.2572218686 May 30 02:37:10 PM PDT 24 May 30 02:37:13 PM PDT 24 433031347 ps
T974 /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.1665372550 May 30 02:37:19 PM PDT 24 May 30 02:37:26 PM PDT 24 28075294 ps
T975 /workspace/coverage/default/3.pwrmgr_wakeup_reset.169837260 May 30 02:36:29 PM PDT 24 May 30 02:36:33 PM PDT 24 191163226 ps
T976 /workspace/coverage/default/17.pwrmgr_wakeup_reset.2517107183 May 30 02:37:23 PM PDT 24 May 30 02:37:29 PM PDT 24 311904738 ps
T977 /workspace/coverage/default/15.pwrmgr_stress_all_with_rand_reset.3492480041 May 30 02:37:15 PM PDT 24 May 30 02:37:37 PM PDT 24 25222261154 ps
T978 /workspace/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4111820459 May 30 02:36:36 PM PDT 24 May 30 02:36:42 PM PDT 24 667968543 ps
T979 /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.2613466391 May 30 02:37:14 PM PDT 24 May 30 02:37:19 PM PDT 24 214996794 ps
T980 /workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.2150889696 May 30 02:38:19 PM PDT 24 May 30 02:38:24 PM PDT 24 128104102 ps
T981 /workspace/coverage/default/39.pwrmgr_global_esc.4161235678 May 30 02:38:21 PM PDT 24 May 30 02:38:27 PM PDT 24 53679375 ps
T982 /workspace/coverage/default/21.pwrmgr_wakeup.1220093844 May 30 02:37:27 PM PDT 24 May 30 02:37:34 PM PDT 24 103320912 ps
T983 /workspace/coverage/default/2.pwrmgr_wakeup.1271787016 May 30 02:36:41 PM PDT 24 May 30 02:36:46 PM PDT 24 380193811 ps
T984 /workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.3640790233 May 30 02:36:57 PM PDT 24 May 30 02:36:59 PM PDT 24 107254844 ps
T85 /workspace/coverage/default/43.pwrmgr_stress_all_with_rand_reset.1689647047 May 30 02:38:34 PM PDT 24 May 30 02:38:49 PM PDT 24 3591892969 ps
T985 /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4192169528 May 30 02:38:24 PM PDT 24 May 30 02:38:34 PM PDT 24 936010412 ps
T986 /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1817472275 May 30 02:36:45 PM PDT 24 May 30 02:36:49 PM PDT 24 29469734 ps
T987 /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.3745085477 May 30 02:36:29 PM PDT 24 May 30 02:36:33 PM PDT 24 94161480 ps
T988 /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.2822233044 May 30 02:37:35 PM PDT 24 May 30 02:37:43 PM PDT 24 37163287 ps
T989 /workspace/coverage/default/22.pwrmgr_stress_all.3304164793 May 30 02:37:42 PM PDT 24 May 30 02:37:50 PM PDT 24 1318426494 ps
T990 /workspace/coverage/default/45.pwrmgr_wakeup.3934380037 May 30 02:38:58 PM PDT 24 May 30 02:39:03 PM PDT 24 540661122 ps
T991 /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.3822128241 May 30 02:38:05 PM PDT 24 May 30 02:38:08 PM PDT 24 41722312 ps
T992 /workspace/coverage/default/37.pwrmgr_wakeup.655066164 May 30 02:38:20 PM PDT 24 May 30 02:38:25 PM PDT 24 208704355 ps
T993 /workspace/coverage/default/24.pwrmgr_reset_invalid.1730778553 May 30 02:37:39 PM PDT 24 May 30 02:37:47 PM PDT 24 114199101 ps
T994 /workspace/coverage/default/16.pwrmgr_stress_all.2545055745 May 30 02:37:28 PM PDT 24 May 30 02:37:40 PM PDT 24 2981384596 ps
T995 /workspace/coverage/default/18.pwrmgr_wakeup.1231794414 May 30 02:37:21 PM PDT 24 May 30 02:37:27 PM PDT 24 177888336 ps
T996 /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3368591873 May 30 02:37:12 PM PDT 24 May 30 02:37:17 PM PDT 24 1541712216 ps
T997 /workspace/coverage/default/35.pwrmgr_reset.2311452470 May 30 02:38:19 PM PDT 24 May 30 02:38:24 PM PDT 24 86891826 ps
T998 /workspace/coverage/default/46.pwrmgr_stress_all_with_rand_reset.2592767683 May 30 02:39:01 PM PDT 24 May 30 02:39:15 PM PDT 24 7841862674 ps
T999 /workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2423884765 May 30 02:37:13 PM PDT 24 May 30 02:37:21 PM PDT 24 850398265 ps
T1000 /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.256403249 May 30 02:37:13 PM PDT 24 May 30 02:37:17 PM PDT 24 93567501 ps
T1001 /workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3112873407 May 30 02:36:31 PM PDT 24 May 30 02:36:36 PM PDT 24 1211145887 ps
T1002 /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.1158261728 May 30 02:37:10 PM PDT 24 May 30 02:37:12 PM PDT 24 173494845 ps
T1003 /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.3715333639 May 30 02:37:12 PM PDT 24 May 30 02:37:16 PM PDT 24 278388000 ps
T1004 /workspace/coverage/default/22.pwrmgr_stress_all_with_rand_reset.3125954741 May 30 02:37:38 PM PDT 24 May 30 02:38:13 PM PDT 24 17056836779 ps
T68 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2273326826 May 30 03:14:05 PM PDT 24 May 30 03:14:08 PM PDT 24 56330511 ps
T62 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1994239401 May 30 03:13:33 PM PDT 24 May 30 03:13:36 PM PDT 24 110170561 ps
T49 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3769689828 May 30 03:14:00 PM PDT 24 May 30 03:14:04 PM PDT 24 275524773 ps
T50 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1082601663 May 30 03:13:32 PM PDT 24 May 30 03:13:35 PM PDT 24 61595298 ps
T63 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2135189420 May 30 03:13:20 PM PDT 24 May 30 03:13:22 PM PDT 24 62944664 ps
T53 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2581854 May 30 03:13:24 PM PDT 24 May 30 03:13:26 PM PDT 24 188750283 ps
T69 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.640973898 May 30 03:13:43 PM PDT 24 May 30 03:13:45 PM PDT 24 48932572 ps
T112 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.2153443815 May 30 03:14:03 PM PDT 24 May 30 03:14:05 PM PDT 24 39087217 ps
T70 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.440102587 May 30 03:14:16 PM PDT 24 May 30 03:14:19 PM PDT 24 47546555 ps
T74 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3301500195 May 30 03:13:45 PM PDT 24 May 30 03:13:48 PM PDT 24 61820838 ps
T55 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.2356241933 May 30 03:13:46 PM PDT 24 May 30 03:13:49 PM PDT 24 404092696 ps
T71 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.2117409374 May 30 03:13:56 PM PDT 24 May 30 03:13:58 PM PDT 24 91105661 ps
T75 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.869247893 May 30 03:13:58 PM PDT 24 May 30 03:14:00 PM PDT 24 94465067 ps
T67 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.767843250 May 30 03:13:56 PM PDT 24 May 30 03:13:58 PM PDT 24 70669635 ps
T61 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3001652145 May 30 03:13:58 PM PDT 24 May 30 03:14:00 PM PDT 24 24012313 ps
T113 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.111026883 May 30 03:13:33 PM PDT 24 May 30 03:13:36 PM PDT 24 19459915 ps
T56 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3701660296 May 30 03:13:24 PM PDT 24 May 30 03:13:26 PM PDT 24 112569109 ps
T64 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.7602067 May 30 03:13:57 PM PDT 24 May 30 03:14:01 PM PDT 24 528228452 ps
T166 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.586239589 May 30 03:14:05 PM PDT 24 May 30 03:14:07 PM PDT 24 44377235 ps
T167 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.4199897229 May 30 03:14:16 PM PDT 24 May 30 03:14:18 PM PDT 24 22047242 ps
T114 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2804303319 May 30 03:13:46 PM PDT 24 May 30 03:13:49 PM PDT 24 60347091 ps
T72 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2344547109 May 30 03:14:05 PM PDT 24 May 30 03:14:07 PM PDT 24 55991324 ps
T1005 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.519579205 May 30 03:13:23 PM PDT 24 May 30 03:13:27 PM PDT 24 292063263 ps
T168 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.2956494477 May 30 03:14:08 PM PDT 24 May 30 03:14:11 PM PDT 24 46370018 ps
T65 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.3889580085 May 30 03:14:05 PM PDT 24 May 30 03:14:09 PM PDT 24 377541116 ps
T115 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1805067017 May 30 03:13:58 PM PDT 24 May 30 03:14:00 PM PDT 24 38969220 ps
T169 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1590182713 May 30 03:14:07 PM PDT 24 May 30 03:14:10 PM PDT 24 41279366 ps
T100 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.4230905958 May 30 03:13:22 PM PDT 24 May 30 03:13:24 PM PDT 24 155579767 ps
T116 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.4063985610 May 30 03:13:33 PM PDT 24 May 30 03:13:36 PM PDT 24 265210267 ps
T101 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1640202745 May 30 03:14:06 PM PDT 24 May 30 03:14:08 PM PDT 24 111277730 ps
T66 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.1615080963 May 30 03:13:34 PM PDT 24 May 30 03:13:38 PM PDT 24 212524172 ps
T117 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1180947156 May 30 03:13:33 PM PDT 24 May 30 03:13:35 PM PDT 24 67401431 ps
T1006 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.419525855 May 30 03:13:33 PM PDT 24 May 30 03:13:36 PM PDT 24 150399254 ps
T1007 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2099843148 May 30 03:13:45 PM PDT 24 May 30 03:13:48 PM PDT 24 17327870 ps
T1008 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.3298843320 May 30 03:13:43 PM PDT 24 May 30 03:13:47 PM PDT 24 112740037 ps
T171 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3993580658 May 30 03:14:05 PM PDT 24 May 30 03:14:07 PM PDT 24 17555989 ps
T118 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3628989681 May 30 03:13:41 PM PDT 24 May 30 03:13:43 PM PDT 24 41262415 ps
T170 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3208642171 May 30 03:13:34 PM PDT 24 May 30 03:13:37 PM PDT 24 57608879 ps
T1009 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.1554567410 May 30 03:14:06 PM PDT 24 May 30 03:14:08 PM PDT 24 18020299 ps
T1010 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1976686360 May 30 03:13:21 PM PDT 24 May 30 03:13:23 PM PDT 24 63990048 ps
T1011 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1986088072 May 30 03:13:32 PM PDT 24 May 30 03:13:36 PM PDT 24 50290962 ps
T1012 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.1478831951 May 30 03:14:06 PM PDT 24 May 30 03:14:09 PM PDT 24 91477401 ps
T1013 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.1646299480 May 30 03:14:04 PM PDT 24 May 30 03:14:06 PM PDT 24 66775203 ps
T102 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.3096155793 May 30 03:14:06 PM PDT 24 May 30 03:14:08 PM PDT 24 18465880 ps
T1014 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2187201060 May 30 03:14:04 PM PDT 24 May 30 03:14:08 PM PDT 24 155828120 ps
T1015 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3509226491 May 30 03:13:23 PM PDT 24 May 30 03:13:27 PM PDT 24 766063347 ps
T1016 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1858962260 May 30 03:13:32 PM PDT 24 May 30 03:13:33 PM PDT 24 20935290 ps
T1017 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2489788338 May 30 03:13:43 PM PDT 24 May 30 03:13:46 PM PDT 24 52686448 ps
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