Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34288

1

T2

50

T5

18

T8

4

auto[1]

32642

1

T2

50

T5

20

T8

2

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34450

1

T2

46

T5

16

T8

2

auto[1]

32480

1

T2

54

T5

22

T8

4

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32635

1

T2

46

T5

26

T8

2

auto[1]

34295

1

T2

54

T5

12

T8

4

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38084

1

T2

50

T5

19

T8

3

auto[1]

28846

1

T2

50

T5

19

T8

3

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32721

1

T2

52

T5

24

T8

2

auto[1]

34209

1

T2

48

T5

14

T8

4

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34429

1

T2

54

T5

14

T8

2

auto[1]

32501

1

T2

46

T5

24

T8

4

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1207

1

T2

2

T25

3

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

897

1

T2

2

T25

3

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1194

1

T2

3

T25

1

T37

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

917

1

T2

3

T25

1

T37

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1180

1

T2

1

T5

1

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

886

1

T2

1

T5

1

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1857

1

T9

1

T25

1

T37

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1572

1

T9

1

T25

1

T37

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1172

1

T2

1

T5

1

T25

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

874

1

T2

1

T5

1

T25

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1209

1

T2

2

T9

1

T25

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

901

1

T2

2

T9

1

T25

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1150

1

T2

1

T5

1

T37

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

857

1

T2

1

T5

1

T37

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1208

1

T2

2

T25

1

T37

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

900

1

T2

2

T25

1

T37

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1186

1

T2

1

T37

1

T14

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

930

1

T2

1

T37

1

T38

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1171

1

T2

2

T5

2

T25

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

889

1

T2

2

T5

2

T25

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1214

1

T2

1

T9

1

T25

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

910

1

T2

1

T9

1

T25

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1239

1

T2

4

T25

1

T37

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

942

1

T2

4

T25

1

T37

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1118

1

T2

3

T5

1

T25

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

864

1

T2

3

T5

1

T25

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1138

1

T5

1

T9

1

T25

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

873

1

T5

1

T9

1

T25

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1120

1

T2

1

T5

1

T9

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

848

1

T2

1

T5

1

T9

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1061

1

T2

1

T5

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

804

1

T2

1

T5

1

T8

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1152

1

T2

2

T5

1

T25

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

861

1

T2

2

T5

1

T25

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1200

1

T2

2

T25

2

T37

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

882

1

T2

2

T25

2

T37

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1158

1

T2

3

T25

2

T37

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

879

1

T2

3

T25

2

T37

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1168

1

T37

4

T38

2

T64

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

883

1

T37

4

T38

2

T64

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1168

1

T5

3

T9

1

T25

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

859

1

T5

3

T9

1

T25

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1171

1

T5

1

T25

2

T37

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

894

1

T5

1

T25

2

T37

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1178

1

T2

2

T25

1

T38

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

861

1

T2

2

T25

1

T38

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1242

1

T2

2

T25

3

T37

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

913

1

T2

2

T25

3

T37

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1163

1

T2

3

T5

1

T37

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

887

1

T2

3

T5

1

T37

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1160

1

T2

1

T37

1

T15

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

872

1

T2

1

T37

1

T47

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1134

1

T5

1

T25

2

T37

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

851

1

T5

1

T25

2

T37

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1126

1

T2

2

T5

1

T25

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

862

1

T2

2

T5

1

T25

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1112

1

T2

2

T5

1

T25

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

817

1

T2

2

T5

1

T25

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1136

1

T2

2

T8

1

T25

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

847

1

T2

2

T8

1

T25

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1212

1

T5

1

T25

2

T14

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

930

1

T5

1

T25

2

T38

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1180

1

T2

4

T25

2

T38

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

884

1

T2

4

T25

2

T38

1