Summary for Variable main_power_reset_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for main_power_reset_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
41296 |
1 |
|
|
T2 |
75 |
|
T3 |
8 |
|
T4 |
1 |
| auto[1] |
7314 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T5 |
5 |
Summary for Variable sleep_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sleep_cp
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19880 |
1 |
|
|
T2 |
36 |
|
T3 |
9 |
|
T4 |
1 |
| auto[1] |
28730 |
1 |
|
|
T2 |
50 |
|
T5 |
19 |
|
T8 |
3 |
Summary for Cross reset_cross
Samples crossed: main_power_reset_cp sleep_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
3 |
0 |
3 |
100.00 |
|
| Automatically Generated Cross Bins |
3 |
0 |
3 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for reset_cross
Bins
| main_power_reset_cp | sleep_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
12566 |
1 |
|
|
T2 |
25 |
|
T3 |
8 |
|
T4 |
1 |
| auto[0] |
auto[1] |
28730 |
1 |
|
|
T2 |
50 |
|
T5 |
19 |
|
T8 |
3 |
| auto[1] |
auto[0] |
7314 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T5 |
5 |
User Defined Cross Bins for reset_cross
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| illegal |
0 |
Illegal |