Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33317 1 T3 2 T4 1 T5 15
auto[1] 32043 1 T5 14 T7 58 T8 12


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33165 1 T3 2 T4 1 T5 14
auto[1] 32195 1 T5 15 T7 38 T8 18


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31922 1 T5 15 T7 68 T8 16
auto[1] 33438 1 T3 2 T4 1 T5 14


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 37295 1 T3 1 T4 1 T5 23
auto[1] 28065 1 T3 1 T5 6 T7 50


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31805 1 T4 1 T5 17 T7 54
auto[1] 33555 1 T3 2 T5 12 T7 46


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33581 1 T3 2 T4 1 T5 16
auto[1] 31779 1 T5 13 T7 46 T8 22


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1092 1 T5 1 T7 2 T10 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 797 1 T7 2 T25 3 T54 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1097 1 T4 1 T7 1 T9 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 811 1 T7 1 T9 1 T54 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1178 1 T5 1 T7 4 T46 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 878 1 T7 4 T54 2 T15 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1832 1 T3 1 T7 3 T46 3
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1532 1 T3 1 T7 3 T46 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1179 1 T7 1 T8 2 T10 3
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 888 1 T7 1 T8 2 T10 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1138 1 T5 1 T7 1 T8 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 865 1 T7 1 T8 1 T9 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1118 1 T5 1 T9 2 T10 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 816 1 T5 1 T9 2 T25 3
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1151 1 T45 1 T47 1 T25 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 863 1 T45 1 T47 1 T25 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1170 1 T7 2 T8 1 T25 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 884 1 T7 2 T8 1 T25 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1089 1 T5 1 T7 3 T46 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 813 1 T5 1 T7 3 T46 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1140 1 T5 1 T8 1 T46 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 841 1 T8 1 T25 2 T15 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1235 1 T5 2 T10 1 T46 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 945 1 T5 1 T53 1 T30 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1160 1 T5 1 T25 1 T15 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 866 1 T25 1 T15 1 T43 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1111 1 T5 1 T7 2 T8 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 840 1 T5 1 T7 2 T8 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1189 1 T5 1 T7 2 T10 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 888 1 T7 2 T10 1 T46 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1091 1 T8 1 T9 1 T46 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 820 1 T8 1 T9 1 T25 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1120 1 T5 1 T7 3 T10 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 835 1 T7 3 T46 2 T25 4
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1170 1 T7 2 T10 4 T46 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 884 1 T7 2 T10 1 T53 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1132 1 T5 1 T7 4 T9 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 842 1 T7 4 T9 1 T53 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1153 1 T5 2 T10 1 T25 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 861 1 T25 1 T54 2 T15 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1151 1 T5 1 T7 4 T8 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 860 1 T7 4 T8 1 T53 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1134 1 T5 3 T7 1 T9 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 871 1 T5 1 T7 1 T9 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1131 1 T7 5 T8 1 T9 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 868 1 T7 5 T8 1 T9 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1089 1 T10 1 T45 1 T46 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 829 1 T10 1 T45 1 T15 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1171 1 T5 2 T8 1 T10 3
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 837 1 T5 1 T8 1 T10 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1180 1 T10 1 T46 3 T16 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 878 1 T25 2 T42 1 T43 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1186 1 T5 1 T7 2 T9 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 858 1 T7 2 T9 1 T25 4
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1211 1 T7 1 T10 3 T46 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 929 1 T7 1 T10 1 T46 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1107 1 T5 1 T7 4 T10 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 834 1 T7 4 T46 1 T25 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1137 1 T7 1 T8 1 T9 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 836 1 T7 1 T8 1 T9 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1082 1 T7 1 T8 1 T9 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 824 1 T7 1 T8 1 T9 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1171 1 T7 1 T8 1 T46 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 872 1 T7 1 T8 1 T25 1

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