Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33088

1

T1

18

T5

18

T7

14

auto[1]

31552

1

T1

8

T5

18

T7

8

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33381

1

T1

18

T5

14

T7

10

auto[1]

31259

1

T1

8

T5

22

T7

12

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31676

1

T1

8

T5

20

T7

16

auto[1]

32964

1

T1

18

T5

16

T7

6

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36097

1

T1

13

T5

18

T7

11

auto[1]

28543

1

T1

13

T5

18

T7

11

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31645

1

T1

12

T5

20

T7

12

auto[1]

32995

1

T1

14

T5

16

T7

10

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32845

1

T1

10

T5

22

T7

12

auto[1]

31795

1

T1

16

T5

14

T7

10

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1121

1

T7

1

T29

5

T30

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

909

1

T7

1

T29

5

T30

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1150

1

T46

1

T47

1

T29

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

897

1

T29

1

T30

4

T43

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1043

1

T7

1

T47

1

T29

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

826

1

T7

1

T47

1

T29

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1819

1

T1

2

T5

1

T45

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1608

1

T1

2

T5

1

T45

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1074

1

T1

1

T5

2

T7

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

831

1

T1

1

T5

2

T7

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1115

1

T1

1

T44

1

T29

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

872

1

T1

1

T29

7

T30

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1154

1

T47

2

T29

4

T30

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

914

1

T47

2

T29

4

T30

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1083

1

T1

2

T7

1

T47

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

867

1

T1

2

T7

1

T47

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1069

1

T5

2

T29

5

T30

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

865

1

T5

2

T29

5

T30

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1102

1

T1

1

T5

1

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

850

1

T1

1

T5

1

T7

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1094

1

T5

1

T7

1

T29

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

870

1

T5

1

T7

1

T29

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1073

1

T1

1

T5

1

T8

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

840

1

T1

1

T5

1

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1137

1

T12

1

T29

3

T30

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

905

1

T29

3

T30

1

T43

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1112

1

T1

1

T5

1

T7

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

860

1

T1

1

T5

1

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1132

1

T46

1

T29

3

T79

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

864

1

T46

1

T29

3

T79

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1141

1

T29

5

T79

1

T49

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

891

1

T29

5

T79

1

T49

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1146

1

T1

1

T5

1

T29

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

911

1

T1

1

T5

1

T29

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1099

1

T29

3

T79

1

T30

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

857

1

T29

3

T79

1

T30

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1106

1

T5

1

T46

1

T29

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

852

1

T5

1

T46

1

T29

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1093

1

T29

1

T43

1

T27

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

873

1

T29

1

T43

1

T27

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1123

1

T1

1

T5

2

T29

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

882

1

T1

1

T5

2

T29

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1166

1

T46

1

T29

7

T79

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

934

1

T46

1

T29

7

T79

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1156

1

T1

1

T7

1

T47

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

886

1

T1

1

T7

1

T47

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1124

1

T29

1

T79

1

T30

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

890

1

T29

1

T79

1

T30

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1050

1

T7

1

T29

9

T79

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

837

1

T7

1

T29

9

T79

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1075

1

T5

1

T44

1

T29

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

824

1

T5

1

T29

6

T79

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1154

1

T7

1

T29

2

T30

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

926

1

T7

1

T29

2

T30

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1070

1

T5

2

T44

1

T46

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

836

1

T5

2

T44

1

T29

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1062

1

T7

1

T29

1

T43

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

842

1

T7

1

T29

1

T43

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1103

1

T8

1

T47

1

T29

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

865

1

T8

1

T47

1

T29

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1097

1

T5

1

T29

2

T30

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

838

1

T5

1

T29

2

T30

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1054

1

T1

1

T5

1

T44

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

821

1

T1

1

T5

1

T44

1