Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32101

1

T1

14

T2

56

T4

12

auto[1]

30720

1

T1

10

T2

44

T4

12

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32037

1

T1

4

T2

44

T4

12

auto[1]

30784

1

T1

20

T2

56

T4

12

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30975

1

T1

16

T2

40

T4

8

auto[1]

31846

1

T1

8

T2

60

T4

16

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35285

1

T1

12

T2

50

T4

12

auto[1]

27536

1

T1

12

T2

50

T4

12

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31028

1

T1

16

T2

54

T4

6

auto[1]

31793

1

T1

8

T2

46

T4

18

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32280

1

T1

10

T2

54

T4

18

auto[1]

30541

1

T1

14

T2

46

T4

6

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1055

1

T2

2

T25

2

T13

16

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

833

1

T2

2

T25

2

T13

9

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1033

1

T2

4

T6

4

T13

23

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

792

1

T2

4

T6

4

T13

16

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1092

1

T13

21

T37

3

T38

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

863

1

T13

18

T37

3

T38

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1747

1

T2

2

T4

1

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1525

1

T2

2

T4

1

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1088

1

T2

2

T6

1

T25

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

850

1

T2

2

T6

1

T25

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1055

1

T2

1

T4

1

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

820

1

T2

1

T4

1

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1092

1

T2

2

T6

2

T13

26

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

834

1

T2

2

T6

2

T13

21

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1074

1

T1

1

T6

2

T25

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

833

1

T1

1

T6

2

T25

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1142

1

T1

2

T2

3

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

895

1

T1

2

T2

3

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1118

1

T1

1

T2

2

T4

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

881

1

T1

1

T2

2

T4

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1072

1

T1

1

T2

1

T4

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

834

1

T1

1

T2

1

T4

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1063

1

T2

2

T4

1

T6

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

823

1

T2

2

T4

1

T6

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1113

1

T1

1

T4

1

T25

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

876

1

T1

1

T4

1

T25

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1095

1

T1

1

T2

2

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

810

1

T1

1

T2

2

T6

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1089

1

T2

2

T6

1

T25

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

855

1

T2

2

T6

1

T25

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1044

1

T2

3

T6

2

T25

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

805

1

T2

3

T6

2

T25

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1097

1

T1

1

T2

3

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

861

1

T1

1

T2

3

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1143

1

T6

1

T13

16

T37

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

906

1

T6

1

T13

13

T37

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1049

1

T4

2

T6

5

T25

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

806

1

T4

2

T6

5

T25

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1016

1

T2

3

T4

2

T25

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

783

1

T2

3

T4

2

T25

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1117

1

T2

1

T6

1

T25

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

848

1

T2

1

T6

1

T25

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1074

1

T2

1

T6

1

T25

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

839

1

T2

1

T6

1

T25

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1111

1

T6

2

T25

2

T13

23

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

831

1

T6

2

T25

2

T13

15

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1108

1

T2

1

T6

1

T25

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

862

1

T2

1

T6

1

T25

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1137

1

T2

1

T6

1

T25

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

883

1

T2

1

T6

1

T25

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1129

1

T2

2

T6

2

T25

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

862

1

T2

2

T6

2

T25

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1085

1

T2

1

T6

1

T13

17

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

862

1

T2

1

T6

1

T13

17

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1061

1

T2

1

T4

1

T6

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

832

1

T2

1

T4

1

T6

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1041

1

T1

2

T6

3

T25

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

830

1

T1

2

T6

3

T25

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1032

1

T2

3

T6

1

T13

16

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

773

1

T2

3

T6

1

T13

12

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1031

1

T1

1

T2

2

T6

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

803

1

T1

1

T2

2

T6

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1082

1

T1

1

T2

3

T4

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

826

1

T1

1

T2

3

T4

1