Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30193

1

T1

100

T2

18

T4

1

auto[1]

29412

1

T1

90

T2

21

T4

2

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30551

1

T1

109

T2

27

T4

1

auto[1]

29054

1

T1

81

T2

12

T4

2

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29288

1

T1

100

T2

16

T4

1

auto[1]

30317

1

T1

90

T2

23

T4

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33170

1

T1

109

T2

23

T4

3

auto[1]

26435

1

T1

81

T2

16

T6

259

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29418

1

T1

73

T2

26

T4

2

auto[1]

30187

1

T1

117

T2

13

T4

1

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30136

1

T1

103

T2

16

T4

1

auto[1]

29469

1

T1

87

T2

23

T4

2

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

965

1

T1

2

T2

2

T6

13

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

786

1

T1

2

T2

2

T6

9

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

965

1

T1

4

T6

11

T9

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

783

1

T1

3

T6

5

T9

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

987

1

T1

4

T2

2

T6

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

770

1

T1

3

T2

1

T6

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1624

1

T1

4

T2

1

T6

20

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1402

1

T1

3

T2

1

T6

17

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

998

1

T1

1

T2

1

T6

15

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

795

1

T1

1

T2

1

T6

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1034

1

T1

4

T2

1

T6

15

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

825

1

T1

4

T2

1

T6

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

976

1

T1

5

T6

13

T9

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

776

1

T1

2

T6

7

T9

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

996

1

T1

4

T2

1

T6

12

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

774

1

T1

3

T2

1

T6

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1046

1

T1

3

T6

12

T24

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

836

1

T1

1

T6

6

T24

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1010

1

T1

2

T2

1

T6

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

795

1

T1

1

T6

8

T9

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1056

1

T1

6

T6

16

T9

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

839

1

T1

6

T6

12

T9

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

964

1

T1

1

T6

13

T9

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

760

1

T1

1

T6

6

T9

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1052

1

T1

4

T2

1

T6

12

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

835

1

T1

4

T6

8

T9

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1037

1

T1

2

T2

1

T6

15

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

826

1

T1

2

T6

9

T9

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1027

1

T1

4

T6

21

T9

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

832

1

T1

2

T6

15

T9

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1008

1

T1

7

T4

1

T6

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

814

1

T1

5

T6

3

T9

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1029

1

T1

5

T2

1

T6

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

826

1

T1

5

T2

1

T6

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1044

1

T1

4

T2

1

T6

14

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

833

1

T1

3

T2

1

T6

11

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1022

1

T1

8

T6

20

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

829

1

T1

7

T6

15

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1025

1

T1

6

T6

14

T51

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

795

1

T1

4

T6

8

T51

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1041

1

T1

4

T4

1

T6

9

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

830

1

T1

2

T6

7

T9

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1087

1

T1

2

T2

3

T6

17

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

877

1

T2

3

T6

9

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1054

1

T1

2

T6

17

T9

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

848

1

T1

2

T6

7

T9

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1098

1

T1

3

T2

1

T6

11

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

857

1

T1

3

T2

1

T6

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1005

1

T1

1

T6

15

T9

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

816

1

T1

1

T6

11

T9

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1022

1

T1

1

T2

2

T4

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

791

1

T6

8

T9

3

T24

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

959

1

T1

2

T6

6

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

757

1

T1

2

T6

5

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1026

1

T1

5

T6

13

T9

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

769

1

T1

3

T6

6

T9

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1028

1

T1

2

T2

1

T6

10

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

821

1

T1

1

T2

1

T6

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

993

1

T1

1

T2

1

T6

17

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

787

1

T1

1

T6

11

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1036

1

T1

4

T2

1

T6

10

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

811

1

T1

2

T2

1

T6

9

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

956

1

T1

2

T2

1

T6

14

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

740

1

T1

2

T2

1

T6

6