Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31625

1

T1

20

T3

35

T7

9

auto[1]

30047

1

T1

14

T3

33

T7

8

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31404

1

T1

20

T3

28

T7

12

auto[1]

30268

1

T1

14

T3

40

T7

5

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30127

1

T1

14

T3

38

T7

7

auto[1]

31545

1

T1

20

T3

30

T7

10

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34283

1

T1

17

T3

39

T7

17

auto[1]

27389

1

T1

17

T3

29

T8

19

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30473

1

T1

22

T3

29

T7

9

auto[1]

31199

1

T1

12

T3

39

T7

8

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31612

1

T1

18

T3

35

T7

10

auto[1]

30060

1

T1

16

T3

33

T7

7

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1087

1

T1

2

T3

1

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

866

1

T1

2

T3

1

T16

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1083

1

T3

1

T7

2

T8

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

895

1

T8

1

T38

1

T20

26

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1005

1

T177

1

T20

35

T41

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

782

1

T177

1

T20

24

T138

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1706

1

T1

2

T3

3

T7

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1511

1

T1

2

T3

3

T8

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1054

1

T3

3

T7

1

T16

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

835

1

T3

2

T16

1

T82

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1051

1

T1

2

T8

1

T16

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

824

1

T1

2

T8

1

T16

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1028

1

T3

1

T16

3

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

812

1

T3

1

T16

2

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1051

1

T1

1

T61

1

T38

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

843

1

T1

1

T38

1

T39

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1062

1

T1

1

T3

2

T7

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

839

1

T1

1

T3

2

T16

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1087

1

T1

1

T3

1

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

869

1

T1

1

T3

1

T16

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1030

1

T3

1

T61

1

T38

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

821

1

T3

1

T61

1

T38

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1034

1

T3

2

T8

2

T16

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

822

1

T3

2

T8

2

T16

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1099

1

T3

1

T16

4

T82

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

890

1

T3

1

T16

3

T82

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1068

1

T1

1

T8

1

T16

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

817

1

T1

1

T8

1

T16

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1040

1

T3

2

T7

1

T16

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

823

1

T3

1

T16

1

T38

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1048

1

T3

1

T16

5

T82

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

843

1

T3

1

T16

3

T82

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1066

1

T1

2

T16

1

T82

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

837

1

T1

2

T16

1

T82

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1065

1

T16

5

T83

1

T38

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

837

1

T16

4

T83

1

T38

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1019

1

T16

3

T82

1

T61

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

825

1

T16

3

T82

1

T61

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1016

1

T3

2

T7

2

T8

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

821

1

T3

2

T8

2

T16

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1064

1

T1

1

T3

2

T7

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

859

1

T1

1

T3

1

T61

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1050

1

T3

2

T7

1

T8

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

849

1

T3

1

T8

1

T16

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1003

1

T3

1

T16

3

T61

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

782

1

T3

1

T16

3

T61

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1044

1

T7

3

T16

3

T82

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

834

1

T16

3

T82

1

T84

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1110

1

T3

1

T8

1

T16

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

858

1

T8

1

T16

4

T38

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1019

1

T46

1

T39

3

T40

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

802

1

T46

1

T39

3

T40

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1052

1

T3

3

T7

1

T8

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

846

1

T3

2

T8

2

T16

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1077

1

T1

1

T3

3

T8

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

863

1

T1

1

T3

1

T8

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1020

1

T3

1

T8

1

T16

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

805

1

T3

1

T8

1

T16

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1016

1

T1

1

T3

2

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

790

1

T1

1

T3

2

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1045

1

T1

1

T3

3

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

863

1

T1

1

T3

2

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1084

1

T1

1

T16

3

T46

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

826

1

T1

1

T16

3

T84

1