Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31357

1

T8

6

T10

22

T14

5

auto[1]

29838

1

T8

6

T10

15

T14

1

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31046

1

T8

8

T10

15

T14

4

auto[1]

30149

1

T8

4

T10

22

T14

2

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30230

1

T8

4

T10

20

T14

2

auto[1]

30965

1

T8

8

T10

17

T14

4

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34143

1

T8

6

T10

28

T14

4

auto[1]

27052

1

T8

6

T10

9

T14

2

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29968

1

T8

8

T10

20

T14

1

auto[1]

31227

1

T8

4

T10

17

T14

5

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31041

1

T8

8

T10

24

T14

3

auto[1]

30154

1

T8

4

T10

13

T14

3

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1010

1

T8

1

T13

4

T23

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

785

1

T8

1

T13

4

T23

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1031

1

T10

1

T13

4

T23

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

806

1

T13

3

T23

1

T24

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1038

1

T8

1

T10

2

T13

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

828

1

T8

1

T13

3

T23

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1707

1

T8

1

T10

1

T14

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1509

1

T8

1

T10

1

T13

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1041

1

T10

1

T13

1

T23

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

837

1

T10

1

T23

1

T24

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1022

1

T10

1

T13

4

T40

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

817

1

T13

4

T40

1

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1049

1

T13

3

T23

1

T24

16

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

807

1

T13

2

T23

1

T24

14

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1060

1

T14

1

T13

3

T23

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

852

1

T14

2

T13

1

T23

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1072

1

T10

2

T14

1

T13

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

853

1

T10

1

T13

3

T23

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1012

1

T10

1

T12

1

T13

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

782

1

T12

1

T13

5

T23

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1058

1

T10

2

T13

7

T23

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

835

1

T13

6

T23

1

T24

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1079

1

T10

2

T15

1

T16

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

841

1

T24

13

T58

1

T25

17

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1102

1

T13

6

T16

1

T24

14

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

873

1

T13

5

T24

12

T58

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1063

1

T10

3

T13

3

T16

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

807

1

T10

1

T13

3

T24

10

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1091

1

T10

1

T13

2

T23

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

880

1

T10

1

T13

2

T23

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1002

1

T13

6

T23

1

T16

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

808

1

T13

4

T23

1

T24

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

994

1

T10

3

T13

2

T16

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

790

1

T10

2

T13

2

T24

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1053

1

T13

4

T40

1

T16

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

829

1

T13

2

T40

1

T24

13

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1033

1

T10

1

T12

1

T13

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

802

1

T12

1

T13

2

T24

11

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1049

1

T13

5

T23

1

T24

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

815

1

T13

5

T23

1

T24

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1107

1

T13

1

T23

2

T45

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

864

1

T13

1

T23

2

T24

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1016

1

T8

1

T13

3

T15

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

806

1

T8

1

T13

2

T24

12

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1063

1

T13

3

T16

2

T24

10

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

833

1

T13

2

T24

7

T81

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1000

1

T10

1

T13

3

T46

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

793

1

T13

3

T46

1

T24

12

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1055

1

T13

4

T24

12

T25

20

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

850

1

T13

3

T24

8

T25

18

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1047

1

T8

1

T10

1

T13

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

816

1

T8

1

T23

1

T80

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1055

1

T10

1

T14

1

T13

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

872

1

T10

1

T13

1

T24

12

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

969

1

T10

1

T13

2

T23

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

766

1

T10

1

T13

2

T23

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1065

1

T10

1

T13

4

T23

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

835

1

T13

4

T23

1

T24

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1094

1

T8

1

T10

1

T13

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

834

1

T8

1

T13

2

T24

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1040

1

T12

1

T13

4

T23

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

813

1

T12

1

T13

4

T23

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1066

1

T10

1

T13

5

T40

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

814

1

T13

4

T40

1

T24

11