Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02


Total test records in report: 1116
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T1016 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1520366644 Jun 10 07:44:08 PM PDT 24 Jun 10 07:44:12 PM PDT 24 30916468 ps
T1017 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.3801337393 Jun 10 07:43:38 PM PDT 24 Jun 10 07:43:42 PM PDT 24 18344426 ps
T176 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2801222349 Jun 10 07:43:49 PM PDT 24 Jun 10 07:43:53 PM PDT 24 747128598 ps
T116 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.869244687 Jun 10 07:43:49 PM PDT 24 Jun 10 07:43:53 PM PDT 24 23542318 ps
T1018 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1660131039 Jun 10 07:43:38 PM PDT 24 Jun 10 07:43:42 PM PDT 24 91165222 ps
T1019 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1055848347 Jun 10 07:43:48 PM PDT 24 Jun 10 07:43:51 PM PDT 24 59367508 ps
T1020 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.1870727071 Jun 10 07:44:01 PM PDT 24 Jun 10 07:44:05 PM PDT 24 17052496 ps
T1021 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2338474757 Jun 10 07:43:49 PM PDT 24 Jun 10 07:43:53 PM PDT 24 20809253 ps
T1022 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.3233387311 Jun 10 07:43:49 PM PDT 24 Jun 10 07:43:54 PM PDT 24 238320999 ps
T1023 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.582437466 Jun 10 07:43:39 PM PDT 24 Jun 10 07:43:43 PM PDT 24 24183208 ps
T1024 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2205911577 Jun 10 07:43:45 PM PDT 24 Jun 10 07:43:48 PM PDT 24 30996280 ps
T1025 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.221896536 Jun 10 07:44:03 PM PDT 24 Jun 10 07:44:07 PM PDT 24 20630957 ps
T1026 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1630950661 Jun 10 07:43:39 PM PDT 24 Jun 10 07:43:43 PM PDT 24 32722677 ps
T1027 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1090137912 Jun 10 07:43:36 PM PDT 24 Jun 10 07:43:40 PM PDT 24 33413014 ps
T117 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.3699402859 Jun 10 07:43:49 PM PDT 24 Jun 10 07:43:52 PM PDT 24 82876735 ps
T124 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2552297797 Jun 10 07:44:01 PM PDT 24 Jun 10 07:44:05 PM PDT 24 21725388 ps
T1028 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3146443481 Jun 10 07:44:07 PM PDT 24 Jun 10 07:44:11 PM PDT 24 18310212 ps
T1029 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.537554007 Jun 10 07:43:57 PM PDT 24 Jun 10 07:44:00 PM PDT 24 44911739 ps
T1030 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.1871465696 Jun 10 07:44:02 PM PDT 24 Jun 10 07:44:06 PM PDT 24 37166273 ps
T177 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1936729133 Jun 10 07:43:43 PM PDT 24 Jun 10 07:43:48 PM PDT 24 446776579 ps
T1031 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.4288371309 Jun 10 07:43:37 PM PDT 24 Jun 10 07:43:41 PM PDT 24 63241878 ps
T1032 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.327030040 Jun 10 07:43:48 PM PDT 24 Jun 10 07:43:52 PM PDT 24 503639065 ps
T1033 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2384963808 Jun 10 07:43:51 PM PDT 24 Jun 10 07:43:56 PM PDT 24 95094354 ps
T1034 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.200526284 Jun 10 07:43:39 PM PDT 24 Jun 10 07:43:46 PM PDT 24 410499530 ps
T1035 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2725526481 Jun 10 07:43:50 PM PDT 24 Jun 10 07:43:54 PM PDT 24 24476824 ps
T1036 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.2120944883 Jun 10 07:43:57 PM PDT 24 Jun 10 07:44:00 PM PDT 24 191553687 ps
T1037 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.4185261681 Jun 10 07:43:58 PM PDT 24 Jun 10 07:44:02 PM PDT 24 136980285 ps
T1038 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3217747523 Jun 10 07:44:01 PM PDT 24 Jun 10 07:44:07 PM PDT 24 113194926 ps
T1039 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.177640103 Jun 10 07:43:40 PM PDT 24 Jun 10 07:43:44 PM PDT 24 107007771 ps
T1040 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1282516410 Jun 10 07:43:36 PM PDT 24 Jun 10 07:43:39 PM PDT 24 33286423 ps
T118 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3262466202 Jun 10 07:43:59 PM PDT 24 Jun 10 07:44:02 PM PDT 24 22042907 ps
T1041 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3039380775 Jun 10 07:43:52 PM PDT 24 Jun 10 07:43:56 PM PDT 24 47470520 ps
T1042 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3741482997 Jun 10 07:43:36 PM PDT 24 Jun 10 07:43:41 PM PDT 24 111743955 ps
T1043 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.716312391 Jun 10 07:43:56 PM PDT 24 Jun 10 07:44:00 PM PDT 24 114597709 ps
T1044 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3255789942 Jun 10 07:43:59 PM PDT 24 Jun 10 07:44:02 PM PDT 24 18528024 ps
T1045 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.4220808790 Jun 10 07:44:00 PM PDT 24 Jun 10 07:44:04 PM PDT 24 22845019 ps
T1046 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1745672217 Jun 10 07:43:59 PM PDT 24 Jun 10 07:44:03 PM PDT 24 45086912 ps
T1047 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2550794834 Jun 10 07:43:58 PM PDT 24 Jun 10 07:44:00 PM PDT 24 112550437 ps
T1048 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2762111162 Jun 10 07:43:51 PM PDT 24 Jun 10 07:43:56 PM PDT 24 57153780 ps
T1049 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1774570574 Jun 10 07:43:57 PM PDT 24 Jun 10 07:44:00 PM PDT 24 25192172 ps
T1050 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.45385807 Jun 10 07:43:59 PM PDT 24 Jun 10 07:44:02 PM PDT 24 46802705 ps
T1051 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2066781635 Jun 10 07:43:41 PM PDT 24 Jun 10 07:43:46 PM PDT 24 42651513 ps
T119 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.545568467 Jun 10 07:43:40 PM PDT 24 Jun 10 07:43:45 PM PDT 24 67908545 ps
T1052 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2017778588 Jun 10 07:43:38 PM PDT 24 Jun 10 07:43:42 PM PDT 24 67074488 ps
T1053 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2528566938 Jun 10 07:43:58 PM PDT 24 Jun 10 07:44:01 PM PDT 24 137528749 ps
T1054 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2654641372 Jun 10 07:43:59 PM PDT 24 Jun 10 07:44:02 PM PDT 24 102741163 ps
T120 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.215275961 Jun 10 07:43:38 PM PDT 24 Jun 10 07:43:43 PM PDT 24 64788354 ps
T1055 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.2215537489 Jun 10 07:44:00 PM PDT 24 Jun 10 07:44:03 PM PDT 24 22821581 ps
T1056 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.2523796344 Jun 10 07:43:46 PM PDT 24 Jun 10 07:43:49 PM PDT 24 37494685 ps
T1057 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.370214052 Jun 10 07:43:59 PM PDT 24 Jun 10 07:44:02 PM PDT 24 26715175 ps
T1058 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2101829403 Jun 10 07:43:37 PM PDT 24 Jun 10 07:43:41 PM PDT 24 27609450 ps
T1059 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2589002455 Jun 10 07:43:51 PM PDT 24 Jun 10 07:43:56 PM PDT 24 45707516 ps
T1060 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1406755448 Jun 10 07:44:03 PM PDT 24 Jun 10 07:44:07 PM PDT 24 126648820 ps
T1061 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1952898147 Jun 10 07:43:42 PM PDT 24 Jun 10 07:43:46 PM PDT 24 34886081 ps
T1062 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1717527691 Jun 10 07:44:01 PM PDT 24 Jun 10 07:44:05 PM PDT 24 46431138 ps
T1063 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3449637208 Jun 10 07:43:48 PM PDT 24 Jun 10 07:43:50 PM PDT 24 50560958 ps
T121 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2769934508 Jun 10 07:43:42 PM PDT 24 Jun 10 07:43:46 PM PDT 24 167417992 ps
T1064 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3260240388 Jun 10 07:43:58 PM PDT 24 Jun 10 07:44:01 PM PDT 24 248559314 ps
T1065 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2768700977 Jun 10 07:44:00 PM PDT 24 Jun 10 07:44:04 PM PDT 24 54205679 ps
T1066 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3816851296 Jun 10 07:43:47 PM PDT 24 Jun 10 07:43:51 PM PDT 24 98184741 ps
T1067 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2801850208 Jun 10 07:44:08 PM PDT 24 Jun 10 07:44:12 PM PDT 24 81322216 ps
T1068 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2908859535 Jun 10 07:43:50 PM PDT 24 Jun 10 07:43:56 PM PDT 24 127944304 ps
T1069 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1713835671 Jun 10 07:43:52 PM PDT 24 Jun 10 07:43:57 PM PDT 24 43978970 ps
T1070 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.528734569 Jun 10 07:43:48 PM PDT 24 Jun 10 07:43:51 PM PDT 24 109002940 ps
T1071 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.3670386892 Jun 10 07:43:47 PM PDT 24 Jun 10 07:43:49 PM PDT 24 65183246 ps
T1072 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1988313495 Jun 10 07:43:35 PM PDT 24 Jun 10 07:43:38 PM PDT 24 61579677 ps
T1073 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.2325476446 Jun 10 07:44:00 PM PDT 24 Jun 10 07:44:03 PM PDT 24 40195206 ps
T1074 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3766030194 Jun 10 07:43:37 PM PDT 24 Jun 10 07:43:41 PM PDT 24 19075770 ps
T1075 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.944419114 Jun 10 07:43:49 PM PDT 24 Jun 10 07:43:53 PM PDT 24 36559454 ps
T1076 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3645323891 Jun 10 07:43:40 PM PDT 24 Jun 10 07:43:46 PM PDT 24 98834538 ps
T1077 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.589334798 Jun 10 07:43:35 PM PDT 24 Jun 10 07:43:39 PM PDT 24 214343755 ps
T1078 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.4023964758 Jun 10 07:43:53 PM PDT 24 Jun 10 07:43:58 PM PDT 24 353190798 ps
T1079 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.87758873 Jun 10 07:43:37 PM PDT 24 Jun 10 07:43:41 PM PDT 24 19369331 ps
T71 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1425518046 Jun 10 07:43:37 PM PDT 24 Jun 10 07:43:42 PM PDT 24 209399648 ps
T1080 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3841440231 Jun 10 07:43:47 PM PDT 24 Jun 10 07:43:50 PM PDT 24 28743507 ps
T122 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.461875980 Jun 10 07:43:50 PM PDT 24 Jun 10 07:43:55 PM PDT 24 73606172 ps
T1081 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.670453569 Jun 10 07:43:53 PM PDT 24 Jun 10 07:43:57 PM PDT 24 18027169 ps
T1082 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3658612086 Jun 10 07:43:50 PM PDT 24 Jun 10 07:43:54 PM PDT 24 24795123 ps
T1083 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.989351231 Jun 10 07:44:00 PM PDT 24 Jun 10 07:44:03 PM PDT 24 16656754 ps
T125 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1824371651 Jun 10 07:43:37 PM PDT 24 Jun 10 07:43:42 PM PDT 24 575261978 ps
T1084 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3286690656 Jun 10 07:43:58 PM PDT 24 Jun 10 07:44:00 PM PDT 24 117044875 ps
T1085 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.1048635298 Jun 10 07:44:00 PM PDT 24 Jun 10 07:44:03 PM PDT 24 17921652 ps
T1086 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.4099104001 Jun 10 07:43:51 PM PDT 24 Jun 10 07:43:55 PM PDT 24 21876134 ps
T123 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.35878609 Jun 10 07:43:35 PM PDT 24 Jun 10 07:43:39 PM PDT 24 21015716 ps
T1087 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1967413383 Jun 10 07:43:48 PM PDT 24 Jun 10 07:43:51 PM PDT 24 24521010 ps
T1088 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.20185655 Jun 10 07:43:53 PM PDT 24 Jun 10 07:43:57 PM PDT 24 25817423 ps
T126 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3353605128 Jun 10 07:43:35 PM PDT 24 Jun 10 07:43:38 PM PDT 24 37422253 ps
T1089 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.4170018452 Jun 10 07:43:48 PM PDT 24 Jun 10 07:43:52 PM PDT 24 59677925 ps
T1090 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4264441391 Jun 10 07:44:09 PM PDT 24 Jun 10 07:44:13 PM PDT 24 20132630 ps
T1091 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.2665537977 Jun 10 07:43:49 PM PDT 24 Jun 10 07:43:52 PM PDT 24 47698970 ps
T1092 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1295113344 Jun 10 07:43:59 PM PDT 24 Jun 10 07:44:01 PM PDT 24 50262125 ps
T1093 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.3523794164 Jun 10 07:43:49 PM PDT 24 Jun 10 07:43:54 PM PDT 24 231267674 ps
T1094 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3001987981 Jun 10 07:43:40 PM PDT 24 Jun 10 07:43:45 PM PDT 24 30180846 ps
T1095 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1335380653 Jun 10 07:44:02 PM PDT 24 Jun 10 07:44:06 PM PDT 24 143392221 ps
T1096 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3219751703 Jun 10 07:43:59 PM PDT 24 Jun 10 07:44:03 PM PDT 24 16576439 ps
T1097 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.671619310 Jun 10 07:43:38 PM PDT 24 Jun 10 07:43:44 PM PDT 24 94022085 ps
T1098 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.4282369591 Jun 10 07:44:03 PM PDT 24 Jun 10 07:44:07 PM PDT 24 55635683 ps
T1099 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1336082171 Jun 10 07:44:04 PM PDT 24 Jun 10 07:44:08 PM PDT 24 28622913 ps
T1100 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.40642950 Jun 10 07:43:49 PM PDT 24 Jun 10 07:43:54 PM PDT 24 209867557 ps
T72 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2685812490 Jun 10 07:43:48 PM PDT 24 Jun 10 07:43:51 PM PDT 24 267849470 ps
T1101 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1721555334 Jun 10 07:43:59 PM PDT 24 Jun 10 07:44:02 PM PDT 24 19794007 ps
T1102 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3516173634 Jun 10 07:44:00 PM PDT 24 Jun 10 07:44:03 PM PDT 24 51256428 ps
T1103 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3156240288 Jun 10 07:43:57 PM PDT 24 Jun 10 07:44:00 PM PDT 24 79038721 ps
T1104 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.579896487 Jun 10 07:44:09 PM PDT 24 Jun 10 07:44:13 PM PDT 24 19182048 ps
T1105 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2690486832 Jun 10 07:43:52 PM PDT 24 Jun 10 07:43:58 PM PDT 24 664100603 ps
T1106 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2825220650 Jun 10 07:43:48 PM PDT 24 Jun 10 07:43:52 PM PDT 24 31907866 ps
T1107 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2922496479 Jun 10 07:43:50 PM PDT 24 Jun 10 07:43:56 PM PDT 24 42687687 ps
T1108 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3985480120 Jun 10 07:43:39 PM PDT 24 Jun 10 07:43:43 PM PDT 24 51496661 ps
T1109 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2829752390 Jun 10 07:44:01 PM PDT 24 Jun 10 07:44:05 PM PDT 24 75413100 ps
T1110 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2224686127 Jun 10 07:44:00 PM PDT 24 Jun 10 07:44:04 PM PDT 24 279358566 ps
T1111 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2232494121 Jun 10 07:43:48 PM PDT 24 Jun 10 07:43:51 PM PDT 24 48096351 ps
T1112 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3491745238 Jun 10 07:43:39 PM PDT 24 Jun 10 07:43:43 PM PDT 24 242927542 ps
T1113 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.520315126 Jun 10 07:44:00 PM PDT 24 Jun 10 07:44:03 PM PDT 24 33225123 ps
T1114 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2829072526 Jun 10 07:43:49 PM PDT 24 Jun 10 07:43:54 PM PDT 24 451429846 ps
T1115 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1715273629 Jun 10 07:43:53 PM PDT 24 Jun 10 07:43:57 PM PDT 24 95288891 ps
T1116 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2520854284 Jun 10 07:43:59 PM PDT 24 Jun 10 07:44:02 PM PDT 24 29632842 ps

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.3301486926
Short name T10
Test name
Test status
Simulation time 130113084 ps
CPU time 0.98 seconds
Started Jun 10 07:44:40 PM PDT 24
Finished Jun 10 07:44:47 PM PDT 24
Peak memory 199560 kb
Host smart-295ce5da-ea28-4ecc-98f0-167df29bedf4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301486926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_c
m_ctrl_config_regwen.3301486926
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.1441381486
Short name T3
Test name
Test status
Simulation time 53590871 ps
CPU time 0.82 seconds
Started Jun 10 07:44:52 PM PDT 24
Finished Jun 10 07:44:59 PM PDT 24
Peak memory 198696 kb
Host smart-edbb66b1-300f-4168-b0fd-b39e38ab0c71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441381486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.1441381486
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all_with_rand_reset.697490766
Short name T24
Test name
Test status
Simulation time 6096996519 ps
CPU time 20.33 seconds
Started Jun 10 07:45:24 PM PDT 24
Finished Jun 10 07:45:45 PM PDT 24
Peak memory 200880 kb
Host smart-4acf1c7f-478a-40ba-9d11-fa53edf2af6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697490766 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all_with_rand_reset.697490766
Directory /workspace/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.2597195694
Short name T7
Test name
Test status
Simulation time 118617059 ps
CPU time 0.81 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 208932 kb
Host smart-68ec19f2-b785-4174-9b76-99c3d3fe0082
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597195694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.2597195694
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.1808501552
Short name T20
Test name
Test status
Simulation time 667964259 ps
CPU time 1.98 seconds
Started Jun 10 07:44:41 PM PDT 24
Finished Jun 10 07:44:48 PM PDT 24
Peak memory 217508 kb
Host smart-15d44da5-a53a-4377-a69c-00a61ad71c4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808501552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.1808501552
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.3641685050
Short name T46
Test name
Test status
Simulation time 44669578 ps
CPU time 0.73 seconds
Started Jun 10 07:45:38 PM PDT 24
Finished Jun 10 07:45:41 PM PDT 24
Peak memory 200776 kb
Host smart-31b0f664-63f6-44fa-9d15-84c7476c926b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641685050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.3641685050
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1954045437
Short name T49
Test name
Test status
Simulation time 324149215 ps
CPU time 1.06 seconds
Started Jun 10 07:43:47 PM PDT 24
Finished Jun 10 07:43:50 PM PDT 24
Peak memory 195048 kb
Host smart-e6135d94-1af4-4c29-adb3-2fbd28af3547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954045437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.1954045437
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.398086658
Short name T82
Test name
Test status
Simulation time 2095029954 ps
CPU time 2.21 seconds
Started Jun 10 07:44:41 PM PDT 24
Finished Jun 10 07:44:48 PM PDT 24
Peak memory 200644 kb
Host smart-db4fd7b7-7f90-4e80-a4b1-91f6702a5750
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398086658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.398086658
Directory /workspace/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all_with_rand_reset.4196662623
Short name T51
Test name
Test status
Simulation time 6163949516 ps
CPU time 22.73 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:47:12 PM PDT 24
Peak memory 200872 kb
Host smart-74158ed4-aef4-4e72-af99-852249e9bd75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196662623 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all_with_rand_reset.4196662623
Directory /workspace/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.585909967
Short name T23
Test name
Test status
Simulation time 310261265 ps
CPU time 1.51 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:06 PM PDT 24
Peak memory 200316 kb
Host smart-736be600-2aa2-41e1-a8ff-1659d273cf1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585909967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wa
keup_race.585909967
Directory /workspace/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3240366119
Short name T180
Test name
Test status
Simulation time 83166025 ps
CPU time 0.62 seconds
Started Jun 10 07:44:09 PM PDT 24
Finished Jun 10 07:44:12 PM PDT 24
Peak memory 194936 kb
Host smart-fcf49d96-dd88-446b-886e-f24d3e9e51ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240366119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3240366119
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3781724776
Short name T37
Test name
Test status
Simulation time 818883538 ps
CPU time 3.22 seconds
Started Jun 10 07:46:09 PM PDT 24
Finished Jun 10 07:46:18 PM PDT 24
Peak memory 200604 kb
Host smart-1bf7c45c-8e53-458a-b83f-fe1808e98885
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781724776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3781724776
Directory /workspace/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1146055244
Short name T115
Test name
Test status
Simulation time 20447328 ps
CPU time 0.63 seconds
Started Jun 10 07:43:50 PM PDT 24
Finished Jun 10 07:43:54 PM PDT 24
Peak memory 194984 kb
Host smart-4d3b3e4e-8f68-4361-9abe-0a5fb579dcdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146055244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.1146055244
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.4177930554
Short name T1014
Test name
Test status
Simulation time 48996914 ps
CPU time 2.41 seconds
Started Jun 10 07:43:58 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 196372 kb
Host smart-0d81231a-9708-410e-8937-9c7c60756752
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177930554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.4177930554
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.495755220
Short name T85
Test name
Test status
Simulation time 600830191 ps
CPU time 0.97 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:28 PM PDT 24
Peak memory 197748 kb
Host smart-9f453bc5-78c6-4657-be25-c3b3b1817e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495755220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.495755220
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all.2940673879
Short name T13
Test name
Test status
Simulation time 1557372192 ps
CPU time 5.19 seconds
Started Jun 10 07:45:50 PM PDT 24
Finished Jun 10 07:45:58 PM PDT 24
Peak memory 200704 kb
Host smart-03af21bb-be02-4c52-b59e-13e3eab5f551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940673879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.2940673879
Directory /workspace/22.pwrmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.270566969
Short name T178
Test name
Test status
Simulation time 313166999 ps
CPU time 1.64 seconds
Started Jun 10 07:43:58 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 195092 kb
Host smart-48aab2b5-8c11-4b9e-abd1-743e1c2f17ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270566969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err
.270566969
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.1900461067
Short name T189
Test name
Test status
Simulation time 93962065 ps
CPU time 0.79 seconds
Started Jun 10 07:45:43 PM PDT 24
Finished Jun 10 07:45:47 PM PDT 24
Peak memory 198936 kb
Host smart-c4eb53bc-999e-48fb-b254-6596422003cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900461067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1900461067
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.2863874809
Short name T28
Test name
Test status
Simulation time 71702509 ps
CPU time 0.69 seconds
Started Jun 10 07:46:08 PM PDT 24
Finished Jun 10 07:46:14 PM PDT 24
Peak memory 198656 kb
Host smart-e43df0e9-04d2-4988-9e2f-d28230a536cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863874809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.2863874809
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all_with_rand_reset.87719893
Short name T148
Test name
Test status
Simulation time 8710964995 ps
CPU time 10.81 seconds
Started Jun 10 07:45:42 PM PDT 24
Finished Jun 10 07:45:57 PM PDT 24
Peak memory 200832 kb
Host smart-4e2d5b13-99bf-4f84-a727-4528cb58763d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87719893 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all_with_rand_reset.87719893
Directory /workspace/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1282516410
Short name T1040
Test name
Test status
Simulation time 33286423 ps
CPU time 0.58 seconds
Started Jun 10 07:43:36 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 194928 kb
Host smart-52d54771-81a6-43e6-a759-144454c8ac02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282516410 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.1282516410
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1936729133
Short name T177
Test name
Test status
Simulation time 446776579 ps
CPU time 1.52 seconds
Started Jun 10 07:43:43 PM PDT 24
Finished Jun 10 07:43:48 PM PDT 24
Peak memory 195204 kb
Host smart-1e8fc0cd-f046-475a-be9e-18b002798906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936729133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.1936729133
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.1544744539
Short name T186
Test name
Test status
Simulation time 90175695 ps
CPU time 0.67 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 198216 kb
Host smart-b48072f8-054e-47bc-b648-8b6828c48ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544744539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.1544744539
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.1257980837
Short name T188
Test name
Test status
Simulation time 87937055 ps
CPU time 0.68 seconds
Started Jun 10 07:47:01 PM PDT 24
Finished Jun 10 07:47:10 PM PDT 24
Peak memory 198724 kb
Host smart-83c8787b-1c79-4ffc-8b0e-281553595867
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257980837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.1257980837
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.1753623744
Short name T50
Test name
Test status
Simulation time 183330613 ps
CPU time 1.06 seconds
Started Jun 10 07:43:35 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 195008 kb
Host smart-55a60d9e-1eaf-4cfb-a723-65801d51ca38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753623744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.1753623744
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.3598606186
Short name T254
Test name
Test status
Simulation time 112539843 ps
CPU time 0.59 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 197688 kb
Host smart-e3eb9cf0-2f41-4225-94fd-609fec098559
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598606186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3598606186
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2713243088
Short name T1004
Test name
Test status
Simulation time 78090598 ps
CPU time 1 seconds
Started Jun 10 07:43:36 PM PDT 24
Finished Jun 10 07:43:40 PM PDT 24
Peak memory 194892 kb
Host smart-42561d42-1e5f-41e5-9080-f0b727b34b34
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713243088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.2
713243088
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3741482997
Short name T1042
Test name
Test status
Simulation time 111743955 ps
CPU time 2 seconds
Started Jun 10 07:43:36 PM PDT 24
Finished Jun 10 07:43:41 PM PDT 24
Peak memory 195020 kb
Host smart-c39c1b7a-2cce-4094-8804-79a08b0a1fb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741482997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.3
741482997
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3985480120
Short name T1108
Test name
Test status
Simulation time 51496661 ps
CPU time 0.66 seconds
Started Jun 10 07:43:39 PM PDT 24
Finished Jun 10 07:43:43 PM PDT 24
Peak memory 197548 kb
Host smart-dc336fba-28ca-4f0f-8013-a4340921ffb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985480120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.3
985480120
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1988313495
Short name T1072
Test name
Test status
Simulation time 61579677 ps
CPU time 1.01 seconds
Started Jun 10 07:43:35 PM PDT 24
Finished Jun 10 07:43:38 PM PDT 24
Peak memory 195020 kb
Host smart-fbc5825c-0564-4982-b3a7-6559a78d9e58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988313495 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.1988313495
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.35878609
Short name T123
Test name
Test status
Simulation time 21015716 ps
CPU time 0.65 seconds
Started Jun 10 07:43:35 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 194984 kb
Host smart-79b975a3-5616-46f2-b588-d35ada3b6a8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35878609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.35878609
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.87758873
Short name T1079
Test name
Test status
Simulation time 19369331 ps
CPU time 0.63 seconds
Started Jun 10 07:43:37 PM PDT 24
Finished Jun 10 07:43:41 PM PDT 24
Peak memory 194924 kb
Host smart-07449d65-d0b5-44ec-b9b4-6356158cf19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87758873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.87758873
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2767803261
Short name T132
Test name
Test status
Simulation time 123827449 ps
CPU time 0.91 seconds
Started Jun 10 07:43:38 PM PDT 24
Finished Jun 10 07:43:42 PM PDT 24
Peak memory 194892 kb
Host smart-f0413cc5-f847-45e6-bd64-79b57010aa04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767803261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.2767803261
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.671619310
Short name T1097
Test name
Test status
Simulation time 94022085 ps
CPU time 2.29 seconds
Started Jun 10 07:43:38 PM PDT 24
Finished Jun 10 07:43:44 PM PDT 24
Peak memory 195220 kb
Host smart-a2f8f495-8294-4ebd-ab63-0201128de478
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671619310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.671619310
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3353605128
Short name T126
Test name
Test status
Simulation time 37422253 ps
CPU time 0.83 seconds
Started Jun 10 07:43:35 PM PDT 24
Finished Jun 10 07:43:38 PM PDT 24
Peak memory 194892 kb
Host smart-7b7d8db6-a057-44d4-81d6-6e0bbb561e68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353605128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.3
353605128
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.992450800
Short name T1015
Test name
Test status
Simulation time 483633512 ps
CPU time 3.58 seconds
Started Jun 10 07:43:42 PM PDT 24
Finished Jun 10 07:43:49 PM PDT 24
Peak memory 195092 kb
Host smart-a2adebc2-d60e-48c9-b925-e3ee24c0d839
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992450800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.992450800
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2101829403
Short name T1058
Test name
Test status
Simulation time 27609450 ps
CPU time 0.64 seconds
Started Jun 10 07:43:37 PM PDT 24
Finished Jun 10 07:43:41 PM PDT 24
Peak memory 197468 kb
Host smart-a9eb78fb-ef97-4b9a-a798-e1f340728ab7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101829403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.2
101829403
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.4288371309
Short name T1031
Test name
Test status
Simulation time 63241878 ps
CPU time 1.06 seconds
Started Jun 10 07:43:37 PM PDT 24
Finished Jun 10 07:43:41 PM PDT 24
Peak memory 195960 kb
Host smart-e6458d8d-33f2-43d3-a92f-f3b2fdc220dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288371309 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.4288371309
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2017778588
Short name T1052
Test name
Test status
Simulation time 67074488 ps
CPU time 0.61 seconds
Started Jun 10 07:43:38 PM PDT 24
Finished Jun 10 07:43:42 PM PDT 24
Peak memory 195020 kb
Host smart-6c19eed8-b948-4150-9497-f7e8af2c75d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017778588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.2017778588
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.968408128
Short name T128
Test name
Test status
Simulation time 34100418 ps
CPU time 0.86 seconds
Started Jun 10 07:43:38 PM PDT 24
Finished Jun 10 07:43:42 PM PDT 24
Peak memory 199820 kb
Host smart-7d2df47f-003d-4ce7-bb99-912c3f06705d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968408128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sam
e_csr_outstanding.968408128
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.3001987981
Short name T1094
Test name
Test status
Simulation time 30180846 ps
CPU time 1.45 seconds
Started Jun 10 07:43:40 PM PDT 24
Finished Jun 10 07:43:45 PM PDT 24
Peak memory 195312 kb
Host smart-63314a2f-851d-4699-9cdd-32265a836643
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001987981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.3001987981
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1425518046
Short name T71
Test name
Test status
Simulation time 209399648 ps
CPU time 1.11 seconds
Started Jun 10 07:43:37 PM PDT 24
Finished Jun 10 07:43:42 PM PDT 24
Peak memory 200000 kb
Host smart-ab9dd4a4-7fec-44bf-b879-9d58835a44ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425518046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.1425518046
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.3670386892
Short name T1071
Test name
Test status
Simulation time 65183246 ps
CPU time 0.82 seconds
Started Jun 10 07:43:47 PM PDT 24
Finished Jun 10 07:43:49 PM PDT 24
Peak memory 195032 kb
Host smart-1867b41e-538f-4dad-935c-ab38d17ce032
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670386892 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.3670386892
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.2665537977
Short name T1091
Test name
Test status
Simulation time 47698970 ps
CPU time 0.61 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:52 PM PDT 24
Peak memory 194936 kb
Host smart-86804657-9bcc-439c-829c-dbaaceb22d58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665537977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.2665537977
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3841440231
Short name T1080
Test name
Test status
Simulation time 28743507 ps
CPU time 0.71 seconds
Started Jun 10 07:43:47 PM PDT 24
Finished Jun 10 07:43:50 PM PDT 24
Peak memory 194916 kb
Host smart-5a108957-9a67-41b7-b41c-4c54df780b6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841440231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.3841440231
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3816851296
Short name T1066
Test name
Test status
Simulation time 98184741 ps
CPU time 2.18 seconds
Started Jun 10 07:43:47 PM PDT 24
Finished Jun 10 07:43:51 PM PDT 24
Peak memory 196288 kb
Host smart-7fcdf35a-c08d-457b-b072-3c7a08c8ffd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816851296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.3816851296
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.900527536
Short name T64
Test name
Test status
Simulation time 233439670 ps
CPU time 1.81 seconds
Started Jun 10 07:43:46 PM PDT 24
Finished Jun 10 07:43:50 PM PDT 24
Peak memory 200368 kb
Host smart-450b92b1-3790-4098-95fd-9f4de425760e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900527536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err
.900527536
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2762111162
Short name T1048
Test name
Test status
Simulation time 57153780 ps
CPU time 0.98 seconds
Started Jun 10 07:43:51 PM PDT 24
Finished Jun 10 07:43:56 PM PDT 24
Peak memory 195076 kb
Host smart-d47dc678-070f-43a4-9596-54b0bc2d6602
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762111162 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.2762111162
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3715076849
Short name T998
Test name
Test status
Simulation time 85518436 ps
CPU time 0.65 seconds
Started Jun 10 07:43:50 PM PDT 24
Finished Jun 10 07:43:55 PM PDT 24
Peak memory 197220 kb
Host smart-d9bdf113-371f-4be6-ab6d-594b95991053
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715076849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3715076849
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.3910548264
Short name T179
Test name
Test status
Simulation time 27465482 ps
CPU time 0.65 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:52 PM PDT 24
Peak memory 195008 kb
Host smart-9b689059-8e73-49d4-b282-6bf249a90db2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910548264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.3910548264
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1967413383
Short name T1087
Test name
Test status
Simulation time 24521010 ps
CPU time 0.73 seconds
Started Jun 10 07:43:48 PM PDT 24
Finished Jun 10 07:43:51 PM PDT 24
Peak memory 197220 kb
Host smart-3c463583-55b8-44a5-8a99-22337136ea18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967413383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.1967413383
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.928594171
Short name T54
Test name
Test status
Simulation time 157831533 ps
CPU time 2.19 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:55 PM PDT 24
Peak memory 197084 kb
Host smart-2e351813-1850-4de3-a943-d2ee3c3af24a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928594171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.928594171
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3484609166
Short name T996
Test name
Test status
Simulation time 39407234 ps
CPU time 0.77 seconds
Started Jun 10 07:43:48 PM PDT 24
Finished Jun 10 07:43:51 PM PDT 24
Peak memory 195032 kb
Host smart-630c3b4d-f7fa-4c1e-b190-cf8da030cd8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484609166 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.3484609166
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2384963808
Short name T1033
Test name
Test status
Simulation time 95094354 ps
CPU time 0.66 seconds
Started Jun 10 07:43:51 PM PDT 24
Finished Jun 10 07:43:56 PM PDT 24
Peak memory 197340 kb
Host smart-c263a541-7af0-4f04-9d99-aa85215b6c35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384963808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2384963808
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1357879731
Short name T69
Test name
Test status
Simulation time 18785669 ps
CPU time 0.59 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:52 PM PDT 24
Peak memory 194916 kb
Host smart-4da7ee81-4c9c-4300-a8f7-afb9ab228246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357879731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.1357879731
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3658612086
Short name T1082
Test name
Test status
Simulation time 24795123 ps
CPU time 0.78 seconds
Started Jun 10 07:43:50 PM PDT 24
Finished Jun 10 07:43:54 PM PDT 24
Peak memory 198288 kb
Host smart-3d958f20-3a3b-4fa5-aadd-62ad66e69f14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658612086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.3658612086
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.214827086
Short name T75
Test name
Test status
Simulation time 42109738 ps
CPU time 1.84 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:53 PM PDT 24
Peak memory 200424 kb
Host smart-550daca6-e735-47d1-83b2-df56c511c9af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214827086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.214827086
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3481713040
Short name T56
Test name
Test status
Simulation time 425997311 ps
CPU time 1.05 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:53 PM PDT 24
Peak memory 195116 kb
Host smart-a3493182-f65e-407a-ba2a-8962378ae598
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481713040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.3481713040
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1219328798
Short name T1005
Test name
Test status
Simulation time 49204935 ps
CPU time 0.74 seconds
Started Jun 10 07:43:52 PM PDT 24
Finished Jun 10 07:43:57 PM PDT 24
Peak memory 195080 kb
Host smart-928dfd5d-5d1b-441d-80fd-c9b3f8659656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219328798 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.1219328798
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.73826958
Short name T60
Test name
Test status
Simulation time 53195277 ps
CPU time 0.63 seconds
Started Jun 10 07:43:52 PM PDT 24
Finished Jun 10 07:43:56 PM PDT 24
Peak memory 195084 kb
Host smart-bc44efc9-5658-4435-a56c-c4c591fa4de0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73826958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.73826958
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2589002455
Short name T1059
Test name
Test status
Simulation time 45707516 ps
CPU time 0.64 seconds
Started Jun 10 07:43:51 PM PDT 24
Finished Jun 10 07:43:56 PM PDT 24
Peak memory 195004 kb
Host smart-925081c2-55f1-4446-8d11-d659c683ec70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589002455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.2589002455
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1715273629
Short name T1115
Test name
Test status
Simulation time 95288891 ps
CPU time 0.85 seconds
Started Jun 10 07:43:53 PM PDT 24
Finished Jun 10 07:43:57 PM PDT 24
Peak memory 194912 kb
Host smart-ceab6c0d-e8d1-47d8-ba06-6b1137503757
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715273629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.1715273629
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2318449958
Short name T70
Test name
Test status
Simulation time 84294832 ps
CPU time 1.4 seconds
Started Jun 10 07:43:51 PM PDT 24
Finished Jun 10 07:43:56 PM PDT 24
Peak memory 196196 kb
Host smart-b46b35af-f4e5-47ca-b5a5-a6f3844e29fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318449958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.2318449958
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3327362966
Short name T55
Test name
Test status
Simulation time 195688333 ps
CPU time 1.49 seconds
Started Jun 10 07:43:53 PM PDT 24
Finished Jun 10 07:43:58 PM PDT 24
Peak memory 195064 kb
Host smart-f67e39aa-4357-44ed-9bb0-2a39a7c3357d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327362966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.3327362966
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2654641372
Short name T1054
Test name
Test status
Simulation time 102741163 ps
CPU time 0.85 seconds
Started Jun 10 07:43:59 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 195052 kb
Host smart-d8c3fa3a-26df-489f-98ee-b76d17cc28f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654641372 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.2654641372
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3262466202
Short name T118
Test name
Test status
Simulation time 22042907 ps
CPU time 0.62 seconds
Started Jun 10 07:43:59 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 195084 kb
Host smart-b27e036c-2462-4cb1-8228-e65056266d90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262466202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.3262466202
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.670453569
Short name T1081
Test name
Test status
Simulation time 18027169 ps
CPU time 0.64 seconds
Started Jun 10 07:43:53 PM PDT 24
Finished Jun 10 07:43:57 PM PDT 24
Peak memory 194936 kb
Host smart-2083adc6-b930-4c0c-bef0-7fe91b46ea00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670453569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.670453569
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2550794834
Short name T1047
Test name
Test status
Simulation time 112550437 ps
CPU time 0.68 seconds
Started Jun 10 07:43:58 PM PDT 24
Finished Jun 10 07:44:00 PM PDT 24
Peak memory 197156 kb
Host smart-7ed87416-0e86-4621-b7b7-859aad741410
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550794834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.2550794834
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.40642950
Short name T1100
Test name
Test status
Simulation time 209867557 ps
CPU time 2.31 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:54 PM PDT 24
Peak memory 197408 kb
Host smart-b161d284-c6da-4d11-9f66-19512233aace
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40642950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.40642950
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.4023964758
Short name T1078
Test name
Test status
Simulation time 353190798 ps
CPU time 1.46 seconds
Started Jun 10 07:43:53 PM PDT 24
Finished Jun 10 07:43:58 PM PDT 24
Peak memory 199884 kb
Host smart-cdc186af-5ddc-4a24-92d0-555e43b31ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023964758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.4023964758
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3156240288
Short name T1103
Test name
Test status
Simulation time 79038721 ps
CPU time 0.74 seconds
Started Jun 10 07:43:57 PM PDT 24
Finished Jun 10 07:44:00 PM PDT 24
Peak memory 195080 kb
Host smart-c1c6ae5d-2d18-462b-a947-b6a777e890d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156240288 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.3156240288
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3260240388
Short name T1064
Test name
Test status
Simulation time 248559314 ps
CPU time 0.66 seconds
Started Jun 10 07:43:58 PM PDT 24
Finished Jun 10 07:44:01 PM PDT 24
Peak memory 197168 kb
Host smart-1084dc45-11b4-4b49-a3b3-214e760e7ff6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260240388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.3260240388
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.4282369591
Short name T1098
Test name
Test status
Simulation time 55635683 ps
CPU time 0.63 seconds
Started Jun 10 07:44:03 PM PDT 24
Finished Jun 10 07:44:07 PM PDT 24
Peak memory 194932 kb
Host smart-aed83043-4e36-4cca-a923-f4a73d8b99f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282369591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.4282369591
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.3174145359
Short name T133
Test name
Test status
Simulation time 126010136 ps
CPU time 0.95 seconds
Started Jun 10 07:43:59 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 199756 kb
Host smart-c6b37557-88ab-4d78-97b1-cc6672a889cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174145359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.3174145359
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.4185261681
Short name T1037
Test name
Test status
Simulation time 136980285 ps
CPU time 2.6 seconds
Started Jun 10 07:43:58 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 197312 kb
Host smart-503b4a78-6ff3-4fdf-b7ee-56a3c6a00d4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185261681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.4185261681
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2224686127
Short name T1110
Test name
Test status
Simulation time 279358566 ps
CPU time 1.59 seconds
Started Jun 10 07:44:00 PM PDT 24
Finished Jun 10 07:44:04 PM PDT 24
Peak memory 200104 kb
Host smart-f2056261-9850-4eeb-8eff-0ceecd1af0a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224686127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.2224686127
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2768700977
Short name T1065
Test name
Test status
Simulation time 54205679 ps
CPU time 0.91 seconds
Started Jun 10 07:44:00 PM PDT 24
Finished Jun 10 07:44:04 PM PDT 24
Peak memory 200368 kb
Host smart-dbf9e638-3f3b-4e68-9942-9a7c85d05cb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768700977 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.2768700977
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.2215537489
Short name T1055
Test name
Test status
Simulation time 22821581 ps
CPU time 0.74 seconds
Started Jun 10 07:44:00 PM PDT 24
Finished Jun 10 07:44:03 PM PDT 24
Peak memory 197184 kb
Host smart-d4a57fed-2488-4581-b284-8ca67d1306a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215537489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.2215537489
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.4063254573
Short name T997
Test name
Test status
Simulation time 20794901 ps
CPU time 0.61 seconds
Started Jun 10 07:43:57 PM PDT 24
Finished Jun 10 07:44:00 PM PDT 24
Peak memory 194916 kb
Host smart-bb0374a3-3b78-4c64-8897-dfa3431d73a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063254573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.4063254573
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.370214052
Short name T1057
Test name
Test status
Simulation time 26715175 ps
CPU time 0.8 seconds
Started Jun 10 07:43:59 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 197176 kb
Host smart-00ecc85e-8154-4b12-937a-ea55080995f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370214052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sa
me_csr_outstanding.370214052
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3217747523
Short name T1038
Test name
Test status
Simulation time 113194926 ps
CPU time 2.3 seconds
Started Jun 10 07:44:01 PM PDT 24
Finished Jun 10 07:44:07 PM PDT 24
Peak memory 196148 kb
Host smart-b4a501e7-22e5-4bf2-9373-911e36ef7d16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217747523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.3217747523
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3353370540
Short name T1000
Test name
Test status
Simulation time 179441115 ps
CPU time 1.7 seconds
Started Jun 10 07:44:00 PM PDT 24
Finished Jun 10 07:44:05 PM PDT 24
Peak memory 200060 kb
Host smart-2c5beaf6-cd9d-4e1d-b9e4-82d371c2f7de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353370540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.3353370540
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.537554007
Short name T1029
Test name
Test status
Simulation time 44911739 ps
CPU time 0.82 seconds
Started Jun 10 07:43:57 PM PDT 24
Finished Jun 10 07:44:00 PM PDT 24
Peak memory 195016 kb
Host smart-a736ee7e-30c8-4784-8c90-db3b18b6c742
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537554007 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.537554007
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1774570574
Short name T1049
Test name
Test status
Simulation time 25192172 ps
CPU time 0.66 seconds
Started Jun 10 07:43:57 PM PDT 24
Finished Jun 10 07:44:00 PM PDT 24
Peak memory 197136 kb
Host smart-6dab5ff3-1777-48ea-ae8e-85c372712bbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774570574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1774570574
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1295113344
Short name T1092
Test name
Test status
Simulation time 50262125 ps
CPU time 0.62 seconds
Started Jun 10 07:43:59 PM PDT 24
Finished Jun 10 07:44:01 PM PDT 24
Peak memory 194904 kb
Host smart-1e8f97e4-b8bf-4062-a68a-53aa20dca70b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295113344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.1295113344
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3516173634
Short name T1102
Test name
Test status
Simulation time 51256428 ps
CPU time 0.79 seconds
Started Jun 10 07:44:00 PM PDT 24
Finished Jun 10 07:44:03 PM PDT 24
Peak memory 194904 kb
Host smart-94e552ed-ebfd-42ad-92f8-c5f6a806623c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516173634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.3516173634
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.716312391
Short name T1043
Test name
Test status
Simulation time 114597709 ps
CPU time 1.14 seconds
Started Jun 10 07:43:56 PM PDT 24
Finished Jun 10 07:44:00 PM PDT 24
Peak memory 195136 kb
Host smart-b7e996f8-3f8e-42b9-8a83-8c24a3c39f3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716312391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err
.716312391
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1008513181
Short name T1008
Test name
Test status
Simulation time 59551044 ps
CPU time 0.71 seconds
Started Jun 10 07:44:00 PM PDT 24
Finished Jun 10 07:44:03 PM PDT 24
Peak memory 195028 kb
Host smart-6efe5bee-f79d-4676-b185-96d5ec4bfab3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008513181 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.1008513181
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2552297797
Short name T124
Test name
Test status
Simulation time 21725388 ps
CPU time 0.66 seconds
Started Jun 10 07:44:01 PM PDT 24
Finished Jun 10 07:44:05 PM PDT 24
Peak memory 194984 kb
Host smart-47ac9681-f0d5-4581-b83c-28ac100575b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552297797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.2552297797
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3219751703
Short name T1096
Test name
Test status
Simulation time 16576439 ps
CPU time 0.65 seconds
Started Jun 10 07:43:59 PM PDT 24
Finished Jun 10 07:44:03 PM PDT 24
Peak memory 194916 kb
Host smart-b7db89da-2178-4ce2-a649-92be2d2cf73c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219751703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.3219751703
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2520854284
Short name T1116
Test name
Test status
Simulation time 29632842 ps
CPU time 0.92 seconds
Started Jun 10 07:43:59 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 198208 kb
Host smart-04365d4b-8eee-44aa-9682-37d66d3d6f61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520854284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.2520854284
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.2120944883
Short name T1036
Test name
Test status
Simulation time 191553687 ps
CPU time 1.76 seconds
Started Jun 10 07:43:57 PM PDT 24
Finished Jun 10 07:44:00 PM PDT 24
Peak memory 196180 kb
Host smart-6a28bbb0-a15a-4e8b-b350-f88ef9b6742d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120944883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.2120944883
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.342830162
Short name T1012
Test name
Test status
Simulation time 297385075 ps
CPU time 1.49 seconds
Started Jun 10 07:43:58 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 200324 kb
Host smart-66c05ce4-7d17-4bfc-97bf-ca0fed996601
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342830162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err
.342830162
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1717527691
Short name T1062
Test name
Test status
Simulation time 46431138 ps
CPU time 0.83 seconds
Started Jun 10 07:44:01 PM PDT 24
Finished Jun 10 07:44:05 PM PDT 24
Peak memory 195044 kb
Host smart-f9222c66-91e5-4a9e-8b9b-662f7411cfdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717527691 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.1717527691
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.4025094902
Short name T127
Test name
Test status
Simulation time 19652151 ps
CPU time 0.66 seconds
Started Jun 10 07:43:58 PM PDT 24
Finished Jun 10 07:44:00 PM PDT 24
Peak memory 194984 kb
Host smart-57983686-e218-4611-a041-a513ba716672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025094902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.4025094902
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.1048635298
Short name T1085
Test name
Test status
Simulation time 17921652 ps
CPU time 0.62 seconds
Started Jun 10 07:44:00 PM PDT 24
Finished Jun 10 07:44:03 PM PDT 24
Peak memory 194896 kb
Host smart-49cba8b7-68f0-4ac7-b16a-67fbd319713a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048635298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.1048635298
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1335380653
Short name T1095
Test name
Test status
Simulation time 143392221 ps
CPU time 0.76 seconds
Started Jun 10 07:44:02 PM PDT 24
Finished Jun 10 07:44:06 PM PDT 24
Peak memory 194892 kb
Host smart-c80db2d2-e589-44df-8371-b393fb9c8bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335380653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.1335380653
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1164908113
Short name T1011
Test name
Test status
Simulation time 379566257 ps
CPU time 1.86 seconds
Started Jun 10 07:43:57 PM PDT 24
Finished Jun 10 07:44:01 PM PDT 24
Peak memory 196084 kb
Host smart-9d440d52-70e5-469b-ad67-2e16f32158de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164908113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.1164908113
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2769934508
Short name T121
Test name
Test status
Simulation time 167417992 ps
CPU time 1.02 seconds
Started Jun 10 07:43:42 PM PDT 24
Finished Jun 10 07:43:46 PM PDT 24
Peak memory 195008 kb
Host smart-7816aa11-d26d-440c-bd49-4460ab82efda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769934508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.2
769934508
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.200526284
Short name T1034
Test name
Test status
Simulation time 410499530 ps
CPU time 3.26 seconds
Started Jun 10 07:43:39 PM PDT 24
Finished Jun 10 07:43:46 PM PDT 24
Peak memory 195016 kb
Host smart-a89aebbc-6361-44c0-942f-b132f67a4fb5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200526284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.200526284
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1630950661
Short name T1026
Test name
Test status
Simulation time 32722677 ps
CPU time 0.77 seconds
Started Jun 10 07:43:39 PM PDT 24
Finished Jun 10 07:43:43 PM PDT 24
Peak memory 197492 kb
Host smart-f51e024b-6943-4615-92f4-087e9b03cf9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630950661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1
630950661
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1660131039
Short name T1018
Test name
Test status
Simulation time 91165222 ps
CPU time 1.22 seconds
Started Jun 10 07:43:38 PM PDT 24
Finished Jun 10 07:43:42 PM PDT 24
Peak memory 196596 kb
Host smart-6dbc5764-1df4-47b5-b1e9-dc40cf6d969d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660131039 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.1660131039
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.3801337393
Short name T1017
Test name
Test status
Simulation time 18344426 ps
CPU time 0.64 seconds
Started Jun 10 07:43:38 PM PDT 24
Finished Jun 10 07:43:42 PM PDT 24
Peak memory 194984 kb
Host smart-5996fe9b-b854-47ca-aa73-08875de3e816
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801337393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.3801337393
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1090137912
Short name T1027
Test name
Test status
Simulation time 33413014 ps
CPU time 0.59 seconds
Started Jun 10 07:43:36 PM PDT 24
Finished Jun 10 07:43:40 PM PDT 24
Peak memory 194932 kb
Host smart-0591ef53-f44d-440d-8911-1fc055408378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090137912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.1090137912
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2066781635
Short name T1051
Test name
Test status
Simulation time 42651513 ps
CPU time 0.93 seconds
Started Jun 10 07:43:41 PM PDT 24
Finished Jun 10 07:43:46 PM PDT 24
Peak memory 198256 kb
Host smart-530a1c7f-09ab-4a11-82a6-cd4ed1d0f42a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066781635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.2066781635
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3645323891
Short name T1076
Test name
Test status
Simulation time 98834538 ps
CPU time 2.19 seconds
Started Jun 10 07:43:40 PM PDT 24
Finished Jun 10 07:43:46 PM PDT 24
Peak memory 200440 kb
Host smart-7e04f9f0-468b-41d2-add4-7e2b7e53925b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645323891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.3645323891
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.177640103
Short name T1039
Test name
Test status
Simulation time 107007771 ps
CPU time 1.21 seconds
Started Jun 10 07:43:40 PM PDT 24
Finished Jun 10 07:43:44 PM PDT 24
Peak memory 200020 kb
Host smart-3435516f-30b7-41e5-99c2-ef537a355596
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177640103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.
177640103
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3286690656
Short name T1084
Test name
Test status
Simulation time 117044875 ps
CPU time 0.62 seconds
Started Jun 10 07:43:58 PM PDT 24
Finished Jun 10 07:44:00 PM PDT 24
Peak memory 194892 kb
Host smart-2947f43f-492c-4be6-be9d-1380ee02ea98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286690656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.3286690656
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.45385807
Short name T1050
Test name
Test status
Simulation time 46802705 ps
CPU time 0.61 seconds
Started Jun 10 07:43:59 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 194924 kb
Host smart-578a1f62-6f14-4c77-b59e-f8c4ba3f19c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45385807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.45385807
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.1870727071
Short name T1020
Test name
Test status
Simulation time 17052496 ps
CPU time 0.66 seconds
Started Jun 10 07:44:01 PM PDT 24
Finished Jun 10 07:44:05 PM PDT 24
Peak memory 194912 kb
Host smart-f6a183d1-f4d1-4ec0-91d3-da3b9305a530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870727071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.1870727071
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1336082171
Short name T1099
Test name
Test status
Simulation time 28622913 ps
CPU time 0.6 seconds
Started Jun 10 07:44:04 PM PDT 24
Finished Jun 10 07:44:08 PM PDT 24
Peak memory 195012 kb
Host smart-71623a12-ff21-4c96-a503-d85b8cfc561c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336082171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.1336082171
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.221896536
Short name T1025
Test name
Test status
Simulation time 20630957 ps
CPU time 0.62 seconds
Started Jun 10 07:44:03 PM PDT 24
Finished Jun 10 07:44:07 PM PDT 24
Peak memory 195008 kb
Host smart-43cf7141-c70a-4c16-86b3-fc31e04ec2a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221896536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.221896536
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.579896487
Short name T1104
Test name
Test status
Simulation time 19182048 ps
CPU time 0.63 seconds
Started Jun 10 07:44:09 PM PDT 24
Finished Jun 10 07:44:13 PM PDT 24
Peak memory 194936 kb
Host smart-598c5c00-fb32-4fc9-bda6-8d1c14d48f4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579896487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.579896487
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1745672217
Short name T1046
Test name
Test status
Simulation time 45086912 ps
CPU time 0.61 seconds
Started Jun 10 07:43:59 PM PDT 24
Finished Jun 10 07:44:03 PM PDT 24
Peak memory 194920 kb
Host smart-f37da39c-f6a0-46f5-8f40-cd63e1afe92a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745672217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1745672217
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.3886177144
Short name T1007
Test name
Test status
Simulation time 31745359 ps
CPU time 0.61 seconds
Started Jun 10 07:44:02 PM PDT 24
Finished Jun 10 07:44:06 PM PDT 24
Peak memory 194836 kb
Host smart-f0479340-89b7-4632-bc77-30b263db17c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886177144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.3886177144
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.995502687
Short name T999
Test name
Test status
Simulation time 17780965 ps
CPU time 0.66 seconds
Started Jun 10 07:44:09 PM PDT 24
Finished Jun 10 07:44:13 PM PDT 24
Peak memory 194928 kb
Host smart-bc973238-181c-49c1-aa1c-857cc57e6296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995502687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.995502687
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.2303560749
Short name T68
Test name
Test status
Simulation time 26903628 ps
CPU time 0.61 seconds
Started Jun 10 07:43:58 PM PDT 24
Finished Jun 10 07:44:01 PM PDT 24
Peak memory 195032 kb
Host smart-875452c2-d593-4663-95e9-43269138ad60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303560749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.2303560749
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.215275961
Short name T120
Test name
Test status
Simulation time 64788354 ps
CPU time 0.78 seconds
Started Jun 10 07:43:38 PM PDT 24
Finished Jun 10 07:43:43 PM PDT 24
Peak memory 197516 kb
Host smart-84d33c08-e2ae-44bc-82ba-3316930e638d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215275961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.215275961
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1824371651
Short name T125
Test name
Test status
Simulation time 575261978 ps
CPU time 2.91 seconds
Started Jun 10 07:43:37 PM PDT 24
Finished Jun 10 07:43:42 PM PDT 24
Peak memory 200156 kb
Host smart-3b0c9c42-b659-4e52-87b9-9ce7a64340e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824371651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.1
824371651
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.545568467
Short name T119
Test name
Test status
Simulation time 67908545 ps
CPU time 0.67 seconds
Started Jun 10 07:43:40 PM PDT 24
Finished Jun 10 07:43:45 PM PDT 24
Peak memory 194956 kb
Host smart-50480ab5-7940-42f7-bf5b-5bdda7d22154
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545568467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.545568467
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1704415492
Short name T182
Test name
Test status
Simulation time 52577923 ps
CPU time 0.87 seconds
Started Jun 10 07:43:42 PM PDT 24
Finished Jun 10 07:43:46 PM PDT 24
Peak memory 194920 kb
Host smart-8cf33484-8c48-4b61-9f4c-71ba6418c5ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704415492 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.1704415492
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3766030194
Short name T1074
Test name
Test status
Simulation time 19075770 ps
CPU time 0.65 seconds
Started Jun 10 07:43:37 PM PDT 24
Finished Jun 10 07:43:41 PM PDT 24
Peak memory 195064 kb
Host smart-9edebf08-a93b-432a-b8ee-c5be49d556db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766030194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.3766030194
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.582437466
Short name T1023
Test name
Test status
Simulation time 24183208 ps
CPU time 0.7 seconds
Started Jun 10 07:43:39 PM PDT 24
Finished Jun 10 07:43:43 PM PDT 24
Peak memory 194876 kb
Host smart-4cb7df00-9aff-46ba-a826-86d7eb3a73f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582437466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.582437466
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1224703560
Short name T131
Test name
Test status
Simulation time 132797022 ps
CPU time 0.82 seconds
Started Jun 10 07:43:42 PM PDT 24
Finished Jun 10 07:43:46 PM PDT 24
Peak memory 198392 kb
Host smart-b5d88518-ed78-488a-af87-c2e76e986af5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224703560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.1224703560
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.589334798
Short name T1077
Test name
Test status
Simulation time 214343755 ps
CPU time 1.26 seconds
Started Jun 10 07:43:35 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 196100 kb
Host smart-318a5c14-570c-40ad-9ee0-8c0df874ba8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589334798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.589334798
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3491745238
Short name T1112
Test name
Test status
Simulation time 242927542 ps
CPU time 1.13 seconds
Started Jun 10 07:43:39 PM PDT 24
Finished Jun 10 07:43:43 PM PDT 24
Peak memory 195048 kb
Host smart-2f41605d-bf76-449a-a553-337c856cef5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491745238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.3491745238
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.1871465696
Short name T1030
Test name
Test status
Simulation time 37166273 ps
CPU time 0.61 seconds
Started Jun 10 07:44:02 PM PDT 24
Finished Jun 10 07:44:06 PM PDT 24
Peak memory 194848 kb
Host smart-e1323040-40ac-4d56-b0e9-a95c7f666168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871465696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.1871465696
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2801850208
Short name T1067
Test name
Test status
Simulation time 81322216 ps
CPU time 0.67 seconds
Started Jun 10 07:44:08 PM PDT 24
Finished Jun 10 07:44:12 PM PDT 24
Peak memory 194936 kb
Host smart-b2d0b93d-b2fb-41f9-94bc-4c947cffe0f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801850208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.2801850208
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1721555334
Short name T1101
Test name
Test status
Simulation time 19794007 ps
CPU time 0.65 seconds
Started Jun 10 07:43:59 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 194920 kb
Host smart-f5ef3073-ce15-4316-b7f2-432131e81114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721555334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.1721555334
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4264441391
Short name T1090
Test name
Test status
Simulation time 20132630 ps
CPU time 0.63 seconds
Started Jun 10 07:44:09 PM PDT 24
Finished Jun 10 07:44:13 PM PDT 24
Peak memory 194932 kb
Host smart-490c7407-6a4d-425b-b693-2ada94b9146c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264441391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.4264441391
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2829752390
Short name T1109
Test name
Test status
Simulation time 75413100 ps
CPU time 0.59 seconds
Started Jun 10 07:44:01 PM PDT 24
Finished Jun 10 07:44:05 PM PDT 24
Peak memory 194904 kb
Host smart-c3bade1c-008c-4520-8eb6-ebde5aa25277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829752390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2829752390
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1520366644
Short name T1016
Test name
Test status
Simulation time 30916468 ps
CPU time 0.7 seconds
Started Jun 10 07:44:08 PM PDT 24
Finished Jun 10 07:44:12 PM PDT 24
Peak memory 194936 kb
Host smart-f78f3175-646b-419b-b1c1-ae3c0e200667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520366644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.1520366644
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3255789942
Short name T1044
Test name
Test status
Simulation time 18528024 ps
CPU time 0.68 seconds
Started Jun 10 07:43:59 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 194936 kb
Host smart-f2616abd-09c1-46c1-938b-2b7adfa0dc64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255789942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3255789942
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1433902234
Short name T1003
Test name
Test status
Simulation time 19905412 ps
CPU time 0.63 seconds
Started Jun 10 07:44:02 PM PDT 24
Finished Jun 10 07:44:06 PM PDT 24
Peak memory 194924 kb
Host smart-9330ae0a-d9d1-4fc3-aa83-c2fe2d73d232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433902234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.1433902234
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.4220808790
Short name T1045
Test name
Test status
Simulation time 22845019 ps
CPU time 0.69 seconds
Started Jun 10 07:44:00 PM PDT 24
Finished Jun 10 07:44:04 PM PDT 24
Peak memory 194912 kb
Host smart-d6d30c0d-d5db-4d87-92bc-0d726f522443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220808790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.4220808790
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3146443481
Short name T1028
Test name
Test status
Simulation time 18310212 ps
CPU time 0.65 seconds
Started Jun 10 07:44:07 PM PDT 24
Finished Jun 10 07:44:11 PM PDT 24
Peak memory 194936 kb
Host smart-3ee6857e-aff9-4501-a74c-a92955e970ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146443481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.3146443481
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.461875980
Short name T122
Test name
Test status
Simulation time 73606172 ps
CPU time 0.79 seconds
Started Jun 10 07:43:50 PM PDT 24
Finished Jun 10 07:43:55 PM PDT 24
Peak memory 194880 kb
Host smart-5ef357c2-f6fc-452a-8a84-4947b6083e99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461875980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.461875980
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2829072526
Short name T1114
Test name
Test status
Simulation time 451429846 ps
CPU time 1.95 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:54 PM PDT 24
Peak memory 195116 kb
Host smart-57d1c6c3-9f46-48f2-b43e-2195913245a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829072526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.2
829072526
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.869244687
Short name T116
Test name
Test status
Simulation time 23542318 ps
CPU time 0.65 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:53 PM PDT 24
Peak memory 197404 kb
Host smart-2517a95e-12e2-48d2-bc22-e9514c3ca97d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869244687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.869244687
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3396069803
Short name T1009
Test name
Test status
Simulation time 46508235 ps
CPU time 0.86 seconds
Started Jun 10 07:43:47 PM PDT 24
Finished Jun 10 07:43:50 PM PDT 24
Peak memory 195028 kb
Host smart-2297231e-3a16-4fed-a7b6-3b53515fc02b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396069803 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.3396069803
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.1416355404
Short name T114
Test name
Test status
Simulation time 28408239 ps
CPU time 0.67 seconds
Started Jun 10 07:43:47 PM PDT 24
Finished Jun 10 07:43:49 PM PDT 24
Peak memory 195032 kb
Host smart-b3b4d36d-738f-423c-86c2-7977c890c3c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416355404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.1416355404
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1952898147
Short name T1061
Test name
Test status
Simulation time 34886081 ps
CPU time 0.6 seconds
Started Jun 10 07:43:42 PM PDT 24
Finished Jun 10 07:43:46 PM PDT 24
Peak memory 194924 kb
Host smart-691739eb-a8fe-4fac-980e-72b4906178ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952898147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1952898147
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.885802157
Short name T1013
Test name
Test status
Simulation time 28867784 ps
CPU time 0.71 seconds
Started Jun 10 07:43:47 PM PDT 24
Finished Jun 10 07:43:50 PM PDT 24
Peak memory 197104 kb
Host smart-90f8752b-0eac-466b-910a-3791ae17a33a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885802157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sam
e_csr_outstanding.885802157
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.512969761
Short name T63
Test name
Test status
Simulation time 92232443 ps
CPU time 1.26 seconds
Started Jun 10 07:43:37 PM PDT 24
Finished Jun 10 07:43:41 PM PDT 24
Peak memory 196180 kb
Host smart-ab9aa05a-cdf2-40ef-b8b8-5b3f140c40f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512969761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.512969761
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1817708060
Short name T1006
Test name
Test status
Simulation time 57309377 ps
CPU time 0.65 seconds
Started Jun 10 07:44:02 PM PDT 24
Finished Jun 10 07:44:06 PM PDT 24
Peak memory 194932 kb
Host smart-f50f3456-9615-42ef-a5cb-0b05002f0382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817708060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.1817708060
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.520315126
Short name T1113
Test name
Test status
Simulation time 33225123 ps
CPU time 0.62 seconds
Started Jun 10 07:44:00 PM PDT 24
Finished Jun 10 07:44:03 PM PDT 24
Peak memory 195004 kb
Host smart-abe38ea7-69e8-46e3-9fe6-43765e22fcc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520315126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.520315126
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.2777525960
Short name T1002
Test name
Test status
Simulation time 18752154 ps
CPU time 0.61 seconds
Started Jun 10 07:44:00 PM PDT 24
Finished Jun 10 07:44:04 PM PDT 24
Peak memory 194940 kb
Host smart-03642c87-8025-49f6-88aa-f74416b254ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777525960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.2777525960
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.1752938571
Short name T1001
Test name
Test status
Simulation time 151211548 ps
CPU time 0.57 seconds
Started Jun 10 07:44:01 PM PDT 24
Finished Jun 10 07:44:05 PM PDT 24
Peak memory 195004 kb
Host smart-99436baf-5f88-4ee1-b52f-0ecb1d8b30c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752938571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.1752938571
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.2933602400
Short name T67
Test name
Test status
Simulation time 19517315 ps
CPU time 0.65 seconds
Started Jun 10 07:43:59 PM PDT 24
Finished Jun 10 07:44:02 PM PDT 24
Peak memory 194920 kb
Host smart-3fd5eacb-8b6a-4de0-972f-976fca3d814e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933602400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.2933602400
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.2325476446
Short name T1073
Test name
Test status
Simulation time 40195206 ps
CPU time 0.62 seconds
Started Jun 10 07:44:00 PM PDT 24
Finished Jun 10 07:44:03 PM PDT 24
Peak memory 194920 kb
Host smart-9af767f7-4d78-46c2-bf8c-10ca19184479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325476446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.2325476446
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.989351231
Short name T1083
Test name
Test status
Simulation time 16656754 ps
CPU time 0.62 seconds
Started Jun 10 07:44:00 PM PDT 24
Finished Jun 10 07:44:03 PM PDT 24
Peak memory 194932 kb
Host smart-9be06bb8-f385-4d09-8aa5-5bf10ece03b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989351231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.989351231
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.1406755448
Short name T1060
Test name
Test status
Simulation time 126648820 ps
CPU time 0.61 seconds
Started Jun 10 07:44:03 PM PDT 24
Finished Jun 10 07:44:07 PM PDT 24
Peak memory 194928 kb
Host smart-7072d539-9e04-42fa-a4a8-def6fa4df6a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406755448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.1406755448
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2528566938
Short name T1053
Test name
Test status
Simulation time 137528749 ps
CPU time 0.58 seconds
Started Jun 10 07:43:58 PM PDT 24
Finished Jun 10 07:44:01 PM PDT 24
Peak memory 194852 kb
Host smart-108026a2-a260-48a5-9f42-9af6a3324f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528566938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.2528566938
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1713835671
Short name T1069
Test name
Test status
Simulation time 43978970 ps
CPU time 0.81 seconds
Started Jun 10 07:43:52 PM PDT 24
Finished Jun 10 07:43:57 PM PDT 24
Peak memory 195136 kb
Host smart-c14c1a9b-fa6c-4b2f-a01e-78d6eb19d931
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713835671 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.1713835671
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3997055776
Short name T129
Test name
Test status
Simulation time 19382566 ps
CPU time 0.65 seconds
Started Jun 10 07:43:46 PM PDT 24
Finished Jun 10 07:43:49 PM PDT 24
Peak memory 195024 kb
Host smart-c40edf38-79db-43f6-9299-8b4a9b21fce5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997055776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.3997055776
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.4099104001
Short name T1086
Test name
Test status
Simulation time 21876134 ps
CPU time 0.61 seconds
Started Jun 10 07:43:51 PM PDT 24
Finished Jun 10 07:43:55 PM PDT 24
Peak memory 194872 kb
Host smart-4e402d06-5e1d-49e9-aa72-c459c7cb0b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099104001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.4099104001
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2988406394
Short name T130
Test name
Test status
Simulation time 127990294 ps
CPU time 0.88 seconds
Started Jun 10 07:43:48 PM PDT 24
Finished Jun 10 07:43:51 PM PDT 24
Peak memory 198196 kb
Host smart-f1bfadcd-e364-4835-a91a-0200255086de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988406394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2988406394
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2908859535
Short name T1068
Test name
Test status
Simulation time 127944304 ps
CPU time 2.48 seconds
Started Jun 10 07:43:50 PM PDT 24
Finished Jun 10 07:43:56 PM PDT 24
Peak memory 197052 kb
Host smart-b95c6e69-acc1-4192-bcc3-190eb2c4049c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908859535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.2908859535
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.906167641
Short name T78
Test name
Test status
Simulation time 231078284 ps
CPU time 1.06 seconds
Started Jun 10 07:43:47 PM PDT 24
Finished Jun 10 07:43:50 PM PDT 24
Peak memory 200096 kb
Host smart-98bd4da9-a8ba-43d7-a0fa-7f53b536fb49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906167641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.
906167641
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.4218147564
Short name T57
Test name
Test status
Simulation time 38178028 ps
CPU time 0.95 seconds
Started Jun 10 07:43:50 PM PDT 24
Finished Jun 10 07:43:54 PM PDT 24
Peak memory 195036 kb
Host smart-161536aa-3d3c-4695-abb3-2b715584d101
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218147564 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.4218147564
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.2523796344
Short name T1056
Test name
Test status
Simulation time 37494685 ps
CPU time 0.61 seconds
Started Jun 10 07:43:46 PM PDT 24
Finished Jun 10 07:43:49 PM PDT 24
Peak memory 197168 kb
Host smart-668d8192-e165-4d04-8022-080ea537383e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523796344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.2523796344
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.2713558670
Short name T181
Test name
Test status
Simulation time 41855715 ps
CPU time 0.6 seconds
Started Jun 10 07:43:45 PM PDT 24
Finished Jun 10 07:43:48 PM PDT 24
Peak memory 194900 kb
Host smart-497059ee-ef1f-461b-8ef7-5220e055755a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713558670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.2713558670
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2922496479
Short name T1107
Test name
Test status
Simulation time 42687687 ps
CPU time 0.9 seconds
Started Jun 10 07:43:50 PM PDT 24
Finished Jun 10 07:43:56 PM PDT 24
Peak memory 198296 kb
Host smart-e326e16b-2ad0-4695-a7ec-61e2cdde9183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922496479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.2922496479
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.3224574612
Short name T1010
Test name
Test status
Simulation time 597388183 ps
CPU time 1.99 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:54 PM PDT 24
Peak memory 195276 kb
Host smart-64c6d540-bfcf-42d2-9889-b68a02a94577
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224574612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.3224574612
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2801222349
Short name T176
Test name
Test status
Simulation time 747128598 ps
CPU time 1.51 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:53 PM PDT 24
Peak memory 200280 kb
Host smart-9dfcde4a-ba60-4ad4-9ce6-05c3595cfc1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801222349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.2801222349
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1055848347
Short name T1019
Test name
Test status
Simulation time 59367508 ps
CPU time 1.03 seconds
Started Jun 10 07:43:48 PM PDT 24
Finished Jun 10 07:43:51 PM PDT 24
Peak memory 196072 kb
Host smart-a5bfccad-2b9a-4752-99c6-a1386544dd90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055848347 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.1055848347
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.3699402859
Short name T117
Test name
Test status
Simulation time 82876735 ps
CPU time 0.67 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:52 PM PDT 24
Peak memory 197280 kb
Host smart-2760234b-ed7a-4ba1-87bd-7d2a0660f2af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699402859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.3699402859
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2205911577
Short name T1024
Test name
Test status
Simulation time 30996280 ps
CPU time 0.62 seconds
Started Jun 10 07:43:45 PM PDT 24
Finished Jun 10 07:43:48 PM PDT 24
Peak memory 194924 kb
Host smart-928b18e6-100d-46ce-9d57-c7e4a636b51f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205911577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.2205911577
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2338474757
Short name T1021
Test name
Test status
Simulation time 20809253 ps
CPU time 0.7 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:53 PM PDT 24
Peak memory 197132 kb
Host smart-0607ee23-03f1-4db6-acd2-cce33ce0cc5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338474757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.2338474757
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.3233387311
Short name T1022
Test name
Test status
Simulation time 238320999 ps
CPU time 1.45 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:54 PM PDT 24
Peak memory 196076 kb
Host smart-23d0b243-6475-4aaa-b8e6-6f65921e812e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233387311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.3233387311
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2685812490
Short name T72
Test name
Test status
Simulation time 267849470 ps
CPU time 1.64 seconds
Started Jun 10 07:43:48 PM PDT 24
Finished Jun 10 07:43:51 PM PDT 24
Peak memory 200392 kb
Host smart-37f118e7-f7ad-49b0-b6a2-e4d54d8f0e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685812490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.2685812490
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2232494121
Short name T1111
Test name
Test status
Simulation time 48096351 ps
CPU time 1.05 seconds
Started Jun 10 07:43:48 PM PDT 24
Finished Jun 10 07:43:51 PM PDT 24
Peak memory 195972 kb
Host smart-84e2212f-ef01-4e34-9e6e-fb4965510e4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232494121 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.2232494121
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.4170018452
Short name T1089
Test name
Test status
Simulation time 59677925 ps
CPU time 0.65 seconds
Started Jun 10 07:43:48 PM PDT 24
Finished Jun 10 07:43:52 PM PDT 24
Peak memory 197148 kb
Host smart-83961e92-427c-43fe-b91c-79abaf9eb4ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170018452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.4170018452
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3449637208
Short name T1063
Test name
Test status
Simulation time 50560958 ps
CPU time 0.59 seconds
Started Jun 10 07:43:48 PM PDT 24
Finished Jun 10 07:43:50 PM PDT 24
Peak memory 194900 kb
Host smart-261867fb-ff09-4c79-a700-ba4c8ea4ecb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449637208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.3449637208
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.944419114
Short name T1075
Test name
Test status
Simulation time 36559454 ps
CPU time 0.83 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:53 PM PDT 24
Peak memory 198152 kb
Host smart-951cc770-5ac7-4752-8f68-d5311a469c17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944419114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sam
e_csr_outstanding.944419114
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.3523794164
Short name T1093
Test name
Test status
Simulation time 231267674 ps
CPU time 2.2 seconds
Started Jun 10 07:43:49 PM PDT 24
Finished Jun 10 07:43:54 PM PDT 24
Peak memory 200488 kb
Host smart-dd90769d-8678-41f6-9897-02146356561a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523794164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.3523794164
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.327030040
Short name T1032
Test name
Test status
Simulation time 503639065 ps
CPU time 1.58 seconds
Started Jun 10 07:43:48 PM PDT 24
Finished Jun 10 07:43:52 PM PDT 24
Peak memory 200344 kb
Host smart-817755e6-e229-463e-9fce-566edc99db0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327030040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.
327030040
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3039380775
Short name T1041
Test name
Test status
Simulation time 47470520 ps
CPU time 0.73 seconds
Started Jun 10 07:43:52 PM PDT 24
Finished Jun 10 07:43:56 PM PDT 24
Peak memory 200340 kb
Host smart-0122c89f-509f-49b1-a957-268b0f0a5aad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039380775 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.3039380775
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2825220650
Short name T1106
Test name
Test status
Simulation time 31907866 ps
CPU time 0.71 seconds
Started Jun 10 07:43:48 PM PDT 24
Finished Jun 10 07:43:52 PM PDT 24
Peak memory 195036 kb
Host smart-6cdb1772-0389-40db-97ec-93d8ab838708
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825220650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.2825220650
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2725526481
Short name T1035
Test name
Test status
Simulation time 24476824 ps
CPU time 0.63 seconds
Started Jun 10 07:43:50 PM PDT 24
Finished Jun 10 07:43:54 PM PDT 24
Peak memory 194900 kb
Host smart-da04863e-6b5e-4856-a2ca-88d83768699f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725526481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.2725526481
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.20185655
Short name T1088
Test name
Test status
Simulation time 25817423 ps
CPU time 0.71 seconds
Started Jun 10 07:43:53 PM PDT 24
Finished Jun 10 07:43:57 PM PDT 24
Peak memory 197156 kb
Host smart-df01f844-fb9c-49d4-ae09-be203aec6ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20185655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_same
_csr_outstanding.20185655
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2690486832
Short name T1105
Test name
Test status
Simulation time 664100603 ps
CPU time 1.85 seconds
Started Jun 10 07:43:52 PM PDT 24
Finished Jun 10 07:43:58 PM PDT 24
Peak memory 197120 kb
Host smart-c359395d-4ac8-4e5f-909a-8eaded504da5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690486832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.2690486832
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.528734569
Short name T1070
Test name
Test status
Simulation time 109002940 ps
CPU time 1.17 seconds
Started Jun 10 07:43:48 PM PDT 24
Finished Jun 10 07:43:51 PM PDT 24
Peak memory 195064 kb
Host smart-396a0cf8-8ef6-4867-93c7-64dd281995d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528734569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.
528734569
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.3804418055
Short name T649
Test name
Test status
Simulation time 31428157 ps
CPU time 0.71 seconds
Started Jun 10 07:44:40 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 198636 kb
Host smart-9bc6b763-73f1-49de-bddf-6f20a883a3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804418055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3804418055
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.1552113871
Short name T912
Test name
Test status
Simulation time 87018985 ps
CPU time 0.73 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 198080 kb
Host smart-27c6d467-6298-478e-9381-cf555c52fa32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552113871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.1552113871
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2439286500
Short name T237
Test name
Test status
Simulation time 28706599 ps
CPU time 0.64 seconds
Started Jun 10 07:44:43 PM PDT 24
Finished Jun 10 07:44:50 PM PDT 24
Peak memory 197548 kb
Host smart-5ff99e18-4424-40c9-9307-fbcfef74a42b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439286500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.2439286500
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.4114441210
Short name T661
Test name
Test status
Simulation time 159860635 ps
CPU time 0.95 seconds
Started Jun 10 07:44:38 PM PDT 24
Finished Jun 10 07:44:43 PM PDT 24
Peak memory 197636 kb
Host smart-1046d183-500a-45c9-a20d-066f15d7064f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114441210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.4114441210
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.1184060434
Short name T850
Test name
Test status
Simulation time 81246103 ps
CPU time 0.63 seconds
Started Jun 10 07:44:37 PM PDT 24
Finished Jun 10 07:44:42 PM PDT 24
Peak memory 197920 kb
Host smart-b71a9b67-d5e4-4c4e-8f1e-71ea7d5c5e12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184060434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.1184060434
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.4008693551
Short name T198
Test name
Test status
Simulation time 68832465 ps
CPU time 0.65 seconds
Started Jun 10 07:44:40 PM PDT 24
Finished Jun 10 07:44:46 PM PDT 24
Peak memory 200708 kb
Host smart-7134c18c-5e1c-42d2-bc54-0b0cd27013ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008693551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.4008693551
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.1443596254
Short name T446
Test name
Test status
Simulation time 107734504 ps
CPU time 0.72 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 198060 kb
Host smart-4fcd820a-9c2c-4f49-87b1-a71bfee2fd88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443596254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wa
keup_race.1443596254
Directory /workspace/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.1679264174
Short name T607
Test name
Test status
Simulation time 160222326 ps
CPU time 0.79 seconds
Started Jun 10 07:44:41 PM PDT 24
Finished Jun 10 07:44:47 PM PDT 24
Peak memory 199396 kb
Host smart-4af6ffe3-49ba-4a0d-a368-f021de93a7a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679264174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.1679264174
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.226601664
Short name T406
Test name
Test status
Simulation time 149714215 ps
CPU time 0.85 seconds
Started Jun 10 07:44:44 PM PDT 24
Finished Jun 10 07:44:51 PM PDT 24
Peak memory 207492 kb
Host smart-232433b9-0fce-4906-b723-dbf1fc49f722
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226601664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.226601664
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.2424988635
Short name T59
Test name
Test status
Simulation time 102967672 ps
CPU time 0.78 seconds
Started Jun 10 07:44:44 PM PDT 24
Finished Jun 10 07:44:51 PM PDT 24
Peak memory 197244 kb
Host smart-f2429bcd-5757-488d-bcb1-4736159a1181
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424988635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_c
m_ctrl_config_regwen.2424988635
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2918275230
Short name T952
Test name
Test status
Simulation time 854547643 ps
CPU time 3.45 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:47 PM PDT 24
Peak memory 200504 kb
Host smart-30754f2e-5686-45d0-bded-79b1f90dcaec
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918275230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2918275230
Directory /workspace/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.569972957
Short name T342
Test name
Test status
Simulation time 1300640160 ps
CPU time 2.29 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:46 PM PDT 24
Peak memory 200440 kb
Host smart-bd1969b8-4d42-40ce-8749-54ad906ca6f8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569972957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.569972957
Directory /workspace/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3522574760
Short name T273
Test name
Test status
Simulation time 189976248 ps
CPU time 0.91 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 198992 kb
Host smart-0587c2b0-a40d-408c-b95e-ca07447110a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522574760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3522574760
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.1300024208
Short name T826
Test name
Test status
Simulation time 28457351 ps
CPU time 0.67 seconds
Started Jun 10 07:44:40 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 198820 kb
Host smart-4d9c6bce-b017-4399-b1a5-09303baa4855
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300024208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.1300024208
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all.1599462858
Short name T867
Test name
Test status
Simulation time 3664925727 ps
CPU time 3.08 seconds
Started Jun 10 07:44:43 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 200712 kb
Host smart-656814c6-7b6e-431a-8d28-2453973ca0a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599462858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.1599462858
Directory /workspace/0.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all_with_rand_reset.2741743911
Short name T73
Test name
Test status
Simulation time 33619201940 ps
CPU time 18.77 seconds
Started Jun 10 07:44:37 PM PDT 24
Finished Jun 10 07:45:00 PM PDT 24
Peak memory 200816 kb
Host smart-bf228549-5c4e-443e-ab50-985911e79526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741743911 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all_with_rand_reset.2741743911
Directory /workspace/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup.2803013392
Short name T313
Test name
Test status
Simulation time 66892638 ps
CPU time 0.74 seconds
Started Jun 10 07:44:44 PM PDT 24
Finished Jun 10 07:44:51 PM PDT 24
Peak memory 196964 kb
Host smart-d1c88be7-9498-4bbc-80df-c8ec3b86554f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803013392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.2803013392
Directory /workspace/0.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.1300908454
Short name T743
Test name
Test status
Simulation time 190654245 ps
CPU time 1.01 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:44 PM PDT 24
Peak memory 199272 kb
Host smart-7071a241-88db-4bd8-b665-923da79dd2d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300908454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.1300908454
Directory /workspace/0.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.4054060056
Short name T884
Test name
Test status
Simulation time 299427591 ps
CPU time 0.82 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 199660 kb
Host smart-d22a185e-2b71-404a-9c3b-b5d6f73611a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054060056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.4054060056
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.2716528532
Short name T796
Test name
Test status
Simulation time 142209608 ps
CPU time 0.7 seconds
Started Jun 10 07:44:43 PM PDT 24
Finished Jun 10 07:44:49 PM PDT 24
Peak memory 198196 kb
Host smart-874ff717-9fd4-413a-92f9-736bee2aea2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716528532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.2716528532
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.455092709
Short name T261
Test name
Test status
Simulation time 31005577 ps
CPU time 0.6 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 197648 kb
Host smart-b86f82bd-5237-460e-b084-2643be72cd7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455092709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_m
alfunc.455092709
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.467006568
Short name T958
Test name
Test status
Simulation time 206448168 ps
CPU time 1.03 seconds
Started Jun 10 07:44:43 PM PDT 24
Finished Jun 10 07:44:50 PM PDT 24
Peak memory 197572 kb
Host smart-4267cba4-b5cd-47d0-9d2a-9671cf3a9935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467006568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.467006568
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.3940546521
Short name T900
Test name
Test status
Simulation time 40737972 ps
CPU time 0.66 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:51 PM PDT 24
Peak memory 196900 kb
Host smart-d1f39924-38e6-417f-beae-eae6c5cdd69b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940546521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.3940546521
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.1127629278
Short name T524
Test name
Test status
Simulation time 105703547 ps
CPU time 0.63 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:51 PM PDT 24
Peak memory 197692 kb
Host smart-b4b6a289-4c82-4d54-99ca-4788a803f9dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127629278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.1127629278
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.1088715494
Short name T572
Test name
Test status
Simulation time 79034979 ps
CPU time 0.69 seconds
Started Jun 10 07:44:43 PM PDT 24
Finished Jun 10 07:44:50 PM PDT 24
Peak memory 200828 kb
Host smart-1a3a76c5-2298-45ff-b556-039215f73c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088715494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.1088715494
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.2657796243
Short name T885
Test name
Test status
Simulation time 54278587 ps
CPU time 0.62 seconds
Started Jun 10 07:44:35 PM PDT 24
Finished Jun 10 07:44:40 PM PDT 24
Peak memory 197796 kb
Host smart-9d022fea-cd4b-4d23-9fcb-2f8a917c6d4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657796243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wa
keup_race.2657796243
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.4246189143
Short name T485
Test name
Test status
Simulation time 172095795 ps
CPU time 0.95 seconds
Started Jun 10 07:44:42 PM PDT 24
Finished Jun 10 07:44:48 PM PDT 24
Peak memory 199576 kb
Host smart-224b8a32-ca78-4512-9787-ecd96b19dd57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246189143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.4246189143
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.1869004920
Short name T871
Test name
Test status
Simulation time 161814071 ps
CPU time 0.81 seconds
Started Jun 10 07:44:41 PM PDT 24
Finished Jun 10 07:44:47 PM PDT 24
Peak memory 208916 kb
Host smart-38eaf1d5-0221-4126-a0e1-c8c15018b3d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869004920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.1869004920
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.3985672234
Short name T22
Test name
Test status
Simulation time 660781898 ps
CPU time 2.19 seconds
Started Jun 10 07:44:42 PM PDT 24
Finished Jun 10 07:44:50 PM PDT 24
Peak memory 217524 kb
Host smart-f6770493-9e5d-4e09-b0e1-d5a53cb47575
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985672234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.3985672234
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3632145999
Short name T245
Test name
Test status
Simulation time 184705337 ps
CPU time 0.76 seconds
Started Jun 10 07:44:42 PM PDT 24
Finished Jun 10 07:44:49 PM PDT 24
Peak memory 198144 kb
Host smart-92e534dd-b800-4b56-ad53-eb13b279c0e3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632145999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_c
m_ctrl_config_regwen.3632145999
Directory /workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3360000994
Short name T705
Test name
Test status
Simulation time 881889275 ps
CPU time 3.02 seconds
Started Jun 10 07:44:42 PM PDT 24
Finished Jun 10 07:44:50 PM PDT 24
Peak memory 200580 kb
Host smart-63d9f2cb-f7fd-4d6a-8f1c-4ed234df4bd1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360000994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3360000994
Directory /workspace/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1898823760
Short name T144
Test name
Test status
Simulation time 1090380063 ps
CPU time 2.54 seconds
Started Jun 10 07:44:41 PM PDT 24
Finished Jun 10 07:44:49 PM PDT 24
Peak memory 200612 kb
Host smart-03db6dd3-d227-4328-a6e9-14d177e17665
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898823760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1898823760
Directory /workspace/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.247707614
Short name T499
Test name
Test status
Simulation time 67887179 ps
CPU time 0.95 seconds
Started Jun 10 07:44:43 PM PDT 24
Finished Jun 10 07:44:50 PM PDT 24
Peak memory 198700 kb
Host smart-0ca6131d-807f-42b6-be0a-25258aa48f06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247707614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.247707614
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.1655539168
Short name T571
Test name
Test status
Simulation time 56194371 ps
CPU time 0.62 seconds
Started Jun 10 07:44:40 PM PDT 24
Finished Jun 10 07:44:46 PM PDT 24
Peak memory 197732 kb
Host smart-6b933e46-3905-482f-9485-8544a478231c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655539168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.1655539168
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all.3679049626
Short name T972
Test name
Test status
Simulation time 1186142961 ps
CPU time 4.6 seconds
Started Jun 10 07:44:43 PM PDT 24
Finished Jun 10 07:44:54 PM PDT 24
Peak memory 200656 kb
Host smart-39cfddd2-5357-4f0e-ab05-5b65431c46e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679049626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.3679049626
Directory /workspace/1.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all_with_rand_reset.4015806634
Short name T312
Test name
Test status
Simulation time 10215603614 ps
CPU time 29.44 seconds
Started Jun 10 07:44:43 PM PDT 24
Finished Jun 10 07:45:18 PM PDT 24
Peak memory 200776 kb
Host smart-f247081b-10a4-498b-8f6d-a6d362eb519e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015806634 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all_with_rand_reset.4015806634
Directory /workspace/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup.1253139953
Short name T622
Test name
Test status
Simulation time 68229727 ps
CPU time 0.67 seconds
Started Jun 10 07:44:40 PM PDT 24
Finished Jun 10 07:44:46 PM PDT 24
Peak memory 198292 kb
Host smart-7b70f011-0e88-4efa-851e-311225110f3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253139953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.1253139953
Directory /workspace/1.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup_reset.2322972836
Short name T852
Test name
Test status
Simulation time 212211282 ps
CPU time 1.16 seconds
Started Jun 10 07:44:42 PM PDT 24
Finished Jun 10 07:44:49 PM PDT 24
Peak memory 199516 kb
Host smart-8a154dd7-acc9-467a-b402-b428c783d2e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322972836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.2322972836
Directory /workspace/1.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.1620449636
Short name T647
Test name
Test status
Simulation time 68610062 ps
CPU time 0.77 seconds
Started Jun 10 07:45:07 PM PDT 24
Finished Jun 10 07:45:12 PM PDT 24
Peak memory 198636 kb
Host smart-9672e599-bd29-494d-b6ca-fc16923e646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620449636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.1620449636
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.1033752169
Short name T854
Test name
Test status
Simulation time 57871492 ps
CPU time 0.71 seconds
Started Jun 10 07:45:05 PM PDT 24
Finished Jun 10 07:45:10 PM PDT 24
Peak memory 198716 kb
Host smart-c819713d-be72-4104-894f-000ced969150
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033752169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.1033752169
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1101339038
Short name T171
Test name
Test status
Simulation time 30452042 ps
CPU time 0.63 seconds
Started Jun 10 07:45:10 PM PDT 24
Finished Jun 10 07:45:15 PM PDT 24
Peak memory 197500 kb
Host smart-6bd7966a-76b3-47c9-a761-a065184666ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101339038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.1101339038
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.140451066
Short name T807
Test name
Test status
Simulation time 337636933 ps
CPU time 0.95 seconds
Started Jun 10 07:45:03 PM PDT 24
Finished Jun 10 07:45:07 PM PDT 24
Peak memory 197700 kb
Host smart-0723e00c-ab96-44bd-9d09-7871675ad6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140451066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.140451066
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.664539270
Short name T655
Test name
Test status
Simulation time 61141297 ps
CPU time 0.66 seconds
Started Jun 10 07:45:05 PM PDT 24
Finished Jun 10 07:45:10 PM PDT 24
Peak memory 197620 kb
Host smart-647df5d5-e9f8-427a-89dd-10168c36f9ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664539270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.664539270
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.3731099704
Short name T385
Test name
Test status
Simulation time 46739404 ps
CPU time 0.67 seconds
Started Jun 10 07:45:05 PM PDT 24
Finished Jun 10 07:45:10 PM PDT 24
Peak memory 197940 kb
Host smart-e311e14e-7655-4da3-8818-ae8649b680a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731099704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.3731099704
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.1057837464
Short name T917
Test name
Test status
Simulation time 41900924 ps
CPU time 0.72 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:11 PM PDT 24
Peak memory 200800 kb
Host smart-b4a93806-63ef-4b1f-87bb-8872f01dbc01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057837464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.1057837464
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.288962587
Short name T882
Test name
Test status
Simulation time 300276409 ps
CPU time 1.07 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:11 PM PDT 24
Peak memory 199220 kb
Host smart-3819b602-000d-4711-9ebb-57b8be4522e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288962587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wa
keup_race.288962587
Directory /workspace/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.3526137609
Short name T817
Test name
Test status
Simulation time 73030619 ps
CPU time 0.93 seconds
Started Jun 10 07:45:08 PM PDT 24
Finished Jun 10 07:45:13 PM PDT 24
Peak memory 199476 kb
Host smart-2bed1817-0934-41ef-9594-bb6bf67346e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526137609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.3526137609
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.2098811952
Short name T523
Test name
Test status
Simulation time 100844223 ps
CPU time 0.93 seconds
Started Jun 10 07:45:04 PM PDT 24
Finished Jun 10 07:45:09 PM PDT 24
Peak memory 208968 kb
Host smart-f116f774-88ee-4d20-b4f2-4b7b45e349f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098811952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.2098811952
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.592346253
Short name T840
Test name
Test status
Simulation time 169683211 ps
CPU time 0.78 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:11 PM PDT 24
Peak memory 198164 kb
Host smart-a19ca926-20f5-4eb5-8cf5-eaa6c2ea145e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592346253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_c
m_ctrl_config_regwen.592346253
Directory /workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3875522204
Short name T404
Test name
Test status
Simulation time 1008133483 ps
CPU time 2.14 seconds
Started Jun 10 07:45:09 PM PDT 24
Finished Jun 10 07:45:16 PM PDT 24
Peak memory 200496 kb
Host smart-6754bd06-2aea-44ee-8bd1-17069f02894a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875522204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3875522204
Directory /workspace/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1836474057
Short name T908
Test name
Test status
Simulation time 1058458296 ps
CPU time 2.06 seconds
Started Jun 10 07:45:02 PM PDT 24
Finished Jun 10 07:45:08 PM PDT 24
Peak memory 200628 kb
Host smart-b6046a11-dcaa-4212-aaec-ffa04702a76d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836474057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1836474057
Directory /workspace/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2278031080
Short name T440
Test name
Test status
Simulation time 192519987 ps
CPU time 0.87 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:11 PM PDT 24
Peak memory 199220 kb
Host smart-068ab5ca-d50e-4cf8-93d6-7a034da86e7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278031080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2278031080
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.2537579431
Short name T953
Test name
Test status
Simulation time 42655530 ps
CPU time 0.64 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:11 PM PDT 24
Peak memory 198036 kb
Host smart-209dea06-deb5-4cd0-92d9-842f77b3de59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537579431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2537579431
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all.572021674
Short name T308
Test name
Test status
Simulation time 1381066691 ps
CPU time 6.22 seconds
Started Jun 10 07:45:09 PM PDT 24
Finished Jun 10 07:45:20 PM PDT 24
Peak memory 200608 kb
Host smart-5f0469bd-ddef-43ca-9b05-5dbba4e1c2ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572021674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.572021674
Directory /workspace/10.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup.4240230318
Short name T476
Test name
Test status
Simulation time 69393494 ps
CPU time 0.65 seconds
Started Jun 10 07:45:11 PM PDT 24
Finished Jun 10 07:45:15 PM PDT 24
Peak memory 197824 kb
Host smart-2266dbbc-15b3-461b-84de-24206684aa94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240230318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.4240230318
Directory /workspace/10.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup_reset.28946872
Short name T763
Test name
Test status
Simulation time 329358565 ps
CPU time 1.62 seconds
Started Jun 10 07:45:07 PM PDT 24
Finished Jun 10 07:45:13 PM PDT 24
Peak memory 200612 kb
Host smart-63520463-8a21-4aa0-afca-1214658b84d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28946872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.28946872
Directory /workspace/10.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.3710791156
Short name T570
Test name
Test status
Simulation time 256688541 ps
CPU time 0.69 seconds
Started Jun 10 07:45:14 PM PDT 24
Finished Jun 10 07:45:19 PM PDT 24
Peak memory 198196 kb
Host smart-60b09d77-fad3-4b53-99ae-f9e1c79ee52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710791156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.3710791156
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.658395528
Short name T967
Test name
Test status
Simulation time 64637056 ps
CPU time 0.74 seconds
Started Jun 10 07:45:14 PM PDT 24
Finished Jun 10 07:45:19 PM PDT 24
Peak memory 198616 kb
Host smart-a8509fe5-7164-4fb5-adfa-17e3aa9ccc10
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658395528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disa
ble_rom_integrity_check.658395528
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.1122324719
Short name T928
Test name
Test status
Simulation time 39115379 ps
CPU time 0.57 seconds
Started Jun 10 07:45:14 PM PDT 24
Finished Jun 10 07:45:18 PM PDT 24
Peak memory 197552 kb
Host smart-ed97458c-7121-4f25-badb-19864af6e144
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122324719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.1122324719
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.1691647562
Short name T941
Test name
Test status
Simulation time 626673719 ps
CPU time 0.94 seconds
Started Jun 10 07:45:15 PM PDT 24
Finished Jun 10 07:45:20 PM PDT 24
Peak memory 197636 kb
Host smart-7a0ddfa3-74df-4980-966c-f61b1597ad63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691647562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.1691647562
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.2238238417
Short name T19
Test name
Test status
Simulation time 46538607 ps
CPU time 0.66 seconds
Started Jun 10 07:45:17 PM PDT 24
Finished Jun 10 07:45:21 PM PDT 24
Peak memory 197644 kb
Host smart-2961b971-ac7e-4f7e-a1f5-be190d55448a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238238417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.2238238417
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.3692170327
Short name T690
Test name
Test status
Simulation time 53803378 ps
CPU time 0.64 seconds
Started Jun 10 07:45:12 PM PDT 24
Finished Jun 10 07:45:17 PM PDT 24
Peak memory 197648 kb
Host smart-553be4ce-ecd7-41d7-b1fa-a7c96a597d0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692170327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.3692170327
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.1110236830
Short name T319
Test name
Test status
Simulation time 78362336 ps
CPU time 0.72 seconds
Started Jun 10 07:45:12 PM PDT 24
Finished Jun 10 07:45:16 PM PDT 24
Peak memory 200804 kb
Host smart-fd3e61f9-c23d-4c01-a69c-bda6c8a1c373
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110236830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.1110236830
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_wakeup_race.2608345554
Short name T157
Test name
Test status
Simulation time 145324064 ps
CPU time 0.79 seconds
Started Jun 10 07:45:13 PM PDT 24
Finished Jun 10 07:45:18 PM PDT 24
Peak memory 197904 kb
Host smart-17b2d66d-973b-48d2-afcb-237575a1b5ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608345554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_w
akeup_race.2608345554
Directory /workspace/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.3253201654
Short name T538
Test name
Test status
Simulation time 76751506 ps
CPU time 0.99 seconds
Started Jun 10 07:45:12 PM PDT 24
Finished Jun 10 07:45:17 PM PDT 24
Peak memory 199412 kb
Host smart-0e683c07-891b-45da-87d1-1d7e25c4ce8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253201654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.3253201654
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.2175775299
Short name T41
Test name
Test status
Simulation time 97060601 ps
CPU time 0.94 seconds
Started Jun 10 07:45:13 PM PDT 24
Finished Jun 10 07:45:18 PM PDT 24
Peak memory 208968 kb
Host smart-c0299b0f-91df-49b4-8cd2-df994ddc1026
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175775299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.2175775299
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.560091660
Short name T477
Test name
Test status
Simulation time 295716421 ps
CPU time 1.29 seconds
Started Jun 10 07:45:14 PM PDT 24
Finished Jun 10 07:45:20 PM PDT 24
Peak memory 199624 kb
Host smart-0560ddfc-6cb1-4fdc-8928-8df88f5ef7b6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560091660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_c
m_ctrl_config_regwen.560091660
Directory /workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.171458749
Short name T568
Test name
Test status
Simulation time 1015278527 ps
CPU time 2.32 seconds
Started Jun 10 07:45:14 PM PDT 24
Finished Jun 10 07:45:20 PM PDT 24
Peak memory 200648 kb
Host smart-6a0beb6f-555e-4a32-a71e-6e369e1ad0bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171458749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.171458749
Directory /workspace/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1980001414
Short name T808
Test name
Test status
Simulation time 1280974688 ps
CPU time 2.25 seconds
Started Jun 10 07:45:12 PM PDT 24
Finished Jun 10 07:45:18 PM PDT 24
Peak memory 200644 kb
Host smart-88ffff43-378e-4b9c-8746-0b73e4b36ccb
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980001414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1980001414
Directory /workspace/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.567036859
Short name T426
Test name
Test status
Simulation time 154238108 ps
CPU time 0.91 seconds
Started Jun 10 07:45:13 PM PDT 24
Finished Jun 10 07:45:18 PM PDT 24
Peak memory 198840 kb
Host smart-7750cac5-aac9-407e-b8e0-4949f75d18ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567036859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_
mubi.567036859
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.3714378462
Short name T290
Test name
Test status
Simulation time 54247367 ps
CPU time 0.61 seconds
Started Jun 10 07:45:11 PM PDT 24
Finished Jun 10 07:45:16 PM PDT 24
Peak memory 198032 kb
Host smart-0c539ae7-625d-48f2-891b-4140a68d09fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714378462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.3714378462
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all.3030413510
Short name T583
Test name
Test status
Simulation time 1558530236 ps
CPU time 5.55 seconds
Started Jun 10 07:45:12 PM PDT 24
Finished Jun 10 07:45:21 PM PDT 24
Peak memory 200720 kb
Host smart-0f9ea958-5ad1-40d1-964c-60fcbe9e7e98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030413510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.3030413510
Directory /workspace/11.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all_with_rand_reset.285954427
Short name T97
Test name
Test status
Simulation time 14449756793 ps
CPU time 22.96 seconds
Started Jun 10 07:45:14 PM PDT 24
Finished Jun 10 07:45:41 PM PDT 24
Peak memory 200780 kb
Host smart-9e2998ce-bf52-4f08-85f4-408eb9237772
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285954427 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all_with_rand_reset.285954427
Directory /workspace/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup.1315370483
Short name T737
Test name
Test status
Simulation time 286868827 ps
CPU time 0.94 seconds
Started Jun 10 07:45:15 PM PDT 24
Finished Jun 10 07:45:20 PM PDT 24
Peak memory 199084 kb
Host smart-21dba8c0-6798-42aa-b835-d03476b445fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315370483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.1315370483
Directory /workspace/11.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup_reset.3458981030
Short name T856
Test name
Test status
Simulation time 230889494 ps
CPU time 1.28 seconds
Started Jun 10 07:45:11 PM PDT 24
Finished Jun 10 07:45:16 PM PDT 24
Peak memory 199652 kb
Host smart-75b99839-63a4-47f8-8c28-3022dc0ae32f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458981030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.3458981030
Directory /workspace/11.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.895902206
Short name T911
Test name
Test status
Simulation time 152121380 ps
CPU time 0.77 seconds
Started Jun 10 07:45:13 PM PDT 24
Finished Jun 10 07:45:17 PM PDT 24
Peak memory 199468 kb
Host smart-d2caf4a3-e75e-421f-9fe3-14ec4851f7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895902206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.895902206
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.3961235648
Short name T458
Test name
Test status
Simulation time 86515373 ps
CPU time 0.71 seconds
Started Jun 10 07:45:10 PM PDT 24
Finished Jun 10 07:45:15 PM PDT 24
Peak memory 198012 kb
Host smart-0973d433-e1ba-4aa9-a63d-2adef2056c8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961235648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.3961235648
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3472517363
Short name T657
Test name
Test status
Simulation time 30747552 ps
CPU time 0.62 seconds
Started Jun 10 07:45:11 PM PDT 24
Finished Jun 10 07:45:16 PM PDT 24
Peak memory 196864 kb
Host smart-70f06966-434f-4251-a4e4-f506d95a3ece
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472517363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.3472517363
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.492510687
Short name T224
Test name
Test status
Simulation time 487270192 ps
CPU time 0.94 seconds
Started Jun 10 07:45:15 PM PDT 24
Finished Jun 10 07:45:20 PM PDT 24
Peak memory 197760 kb
Host smart-e3623ae6-062f-483d-a6bc-9b86bcb9fe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492510687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.492510687
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.3210135140
Short name T687
Test name
Test status
Simulation time 80309366 ps
CPU time 0.62 seconds
Started Jun 10 07:45:14 PM PDT 24
Finished Jun 10 07:45:19 PM PDT 24
Peak memory 196928 kb
Host smart-b7187265-685d-4d35-a848-1fc3e0f05961
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210135140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.3210135140
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.35548173
Short name T805
Test name
Test status
Simulation time 30452887 ps
CPU time 0.63 seconds
Started Jun 10 07:45:12 PM PDT 24
Finished Jun 10 07:45:16 PM PDT 24
Peak memory 197612 kb
Host smart-baa46fe3-32ab-482f-9f66-89c7d66a841b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35548173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.35548173
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.2877151855
Short name T474
Test name
Test status
Simulation time 87554736 ps
CPU time 0.65 seconds
Started Jun 10 07:45:14 PM PDT 24
Finished Jun 10 07:45:19 PM PDT 24
Peak memory 200740 kb
Host smart-ec58f846-9fb7-4803-9287-0d4f056912f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877151855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.2877151855
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.3245870837
Short name T166
Test name
Test status
Simulation time 125855892 ps
CPU time 0.9 seconds
Started Jun 10 07:45:16 PM PDT 24
Finished Jun 10 07:45:20 PM PDT 24
Peak memory 198652 kb
Host smart-f6ff5d3b-1cd7-4077-a690-90f683ea5e45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245870837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_w
akeup_race.3245870837
Directory /workspace/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.231160283
Short name T295
Test name
Test status
Simulation time 25501738 ps
CPU time 0.66 seconds
Started Jun 10 07:45:13 PM PDT 24
Finished Jun 10 07:45:18 PM PDT 24
Peak memory 197840 kb
Host smart-c12db9a2-ff36-42af-b3b3-ba0a14a63b6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231160283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.231160283
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.2683540143
Short name T624
Test name
Test status
Simulation time 105070865 ps
CPU time 0.88 seconds
Started Jun 10 07:45:13 PM PDT 24
Finished Jun 10 07:45:17 PM PDT 24
Peak memory 208940 kb
Host smart-ca4cdeed-b25a-477c-a58d-220152580cb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683540143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.2683540143
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.2343541508
Short name T503
Test name
Test status
Simulation time 160631060 ps
CPU time 0.97 seconds
Started Jun 10 07:45:16 PM PDT 24
Finished Jun 10 07:45:20 PM PDT 24
Peak memory 199296 kb
Host smart-d23ee11d-0c75-4288-ba50-9c0ad25707f2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343541508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_
cm_ctrl_config_regwen.2343541508
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1133485110
Short name T439
Test name
Test status
Simulation time 855005916 ps
CPU time 2.48 seconds
Started Jun 10 07:45:17 PM PDT 24
Finished Jun 10 07:45:23 PM PDT 24
Peak memory 200580 kb
Host smart-e7535676-544b-4176-ac59-a53d1d9895dc
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133485110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1133485110
Directory /workspace/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2324534071
Short name T155
Test name
Test status
Simulation time 1326022394 ps
CPU time 2.22 seconds
Started Jun 10 07:45:14 PM PDT 24
Finished Jun 10 07:45:20 PM PDT 24
Peak memory 200600 kb
Host smart-faabd6a6-f733-44cd-8c39-1e5bf82c7bec
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324534071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2324534071
Directory /workspace/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.4025163787
Short name T274
Test name
Test status
Simulation time 176845941 ps
CPU time 0.88 seconds
Started Jun 10 07:45:14 PM PDT 24
Finished Jun 10 07:45:19 PM PDT 24
Peak memory 198912 kb
Host smart-9928d2c9-edcb-4318-a8c8-012599ca8c76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025163787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4025163787
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.2128712559
Short name T674
Test name
Test status
Simulation time 58538522 ps
CPU time 0.64 seconds
Started Jun 10 07:45:13 PM PDT 24
Finished Jun 10 07:45:17 PM PDT 24
Peak memory 198076 kb
Host smart-a0390c62-f606-4d31-a27f-f84a21cd834f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128712559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.2128712559
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all.3650827294
Short name T471
Test name
Test status
Simulation time 1852320906 ps
CPU time 3.73 seconds
Started Jun 10 07:45:15 PM PDT 24
Finished Jun 10 07:45:23 PM PDT 24
Peak memory 200688 kb
Host smart-4ffbf9ad-94a1-4643-84da-a30a08bac061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650827294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.3650827294
Directory /workspace/12.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all_with_rand_reset.3465642735
Short name T26
Test name
Test status
Simulation time 11134874593 ps
CPU time 14.48 seconds
Started Jun 10 07:45:17 PM PDT 24
Finished Jun 10 07:45:35 PM PDT 24
Peak memory 200820 kb
Host smart-8c4f2ae0-2882-4c44-844e-e3fee26c67bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465642735 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all_with_rand_reset.3465642735
Directory /workspace/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup.741564962
Short name T667
Test name
Test status
Simulation time 116637817 ps
CPU time 0.76 seconds
Started Jun 10 07:45:12 PM PDT 24
Finished Jun 10 07:45:17 PM PDT 24
Peak memory 197868 kb
Host smart-e7a19c4b-9738-44df-9fa3-b4d479b91399
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741564962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.741564962
Directory /workspace/12.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup_reset.2590527232
Short name T517
Test name
Test status
Simulation time 125656418 ps
CPU time 0.95 seconds
Started Jun 10 07:45:12 PM PDT 24
Finished Jun 10 07:45:17 PM PDT 24
Peak memory 198840 kb
Host smart-bcaba3cf-13e3-47b8-8bbc-050e9ca9ec2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590527232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.2590527232
Directory /workspace/12.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.3940275175
Short name T682
Test name
Test status
Simulation time 21142106 ps
CPU time 0.69 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:30 PM PDT 24
Peak memory 198680 kb
Host smart-d8e03bfc-8d1e-470f-abf4-0f69df23755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940275175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.3940275175
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.2648004348
Short name T364
Test name
Test status
Simulation time 58899795 ps
CPU time 0.77 seconds
Started Jun 10 07:45:26 PM PDT 24
Finished Jun 10 07:45:29 PM PDT 24
Peak memory 198708 kb
Host smart-01535be9-9aea-4e78-af0e-1758740aec15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648004348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.2648004348
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.3554459724
Short name T593
Test name
Test status
Simulation time 67874167 ps
CPU time 0.6 seconds
Started Jun 10 07:45:24 PM PDT 24
Finished Jun 10 07:45:26 PM PDT 24
Peak memory 197572 kb
Host smart-d649e9e5-0f73-4f35-ad44-2c2ca70612b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554459724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.3554459724
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.997478505
Short name T948
Test name
Test status
Simulation time 55509020 ps
CPU time 0.69 seconds
Started Jun 10 07:45:23 PM PDT 24
Finished Jun 10 07:45:24 PM PDT 24
Peak memory 197548 kb
Host smart-4314c0b8-69db-4369-88e7-946c27bbceae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997478505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.997478505
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.3394311810
Short name T851
Test name
Test status
Simulation time 72569827 ps
CPU time 0.59 seconds
Started Jun 10 07:45:26 PM PDT 24
Finished Jun 10 07:45:29 PM PDT 24
Peak memory 197952 kb
Host smart-38dc5395-ae8d-44cf-ac7e-56ecc74ab6a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394311810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.3394311810
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.2131202315
Short name T951
Test name
Test status
Simulation time 39644611 ps
CPU time 0.74 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:31 PM PDT 24
Peak memory 200744 kb
Host smart-be731720-6b6f-46f9-9894-874b8603a79a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131202315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.2131202315
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_wakeup_race.3971556884
Short name T190
Test name
Test status
Simulation time 72226253 ps
CPU time 0.7 seconds
Started Jun 10 07:45:23 PM PDT 24
Finished Jun 10 07:45:26 PM PDT 24
Peak memory 198692 kb
Host smart-2e3d5dbc-c295-4b5a-b07c-c1b6de8b5f1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971556884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_w
akeup_race.3971556884
Directory /workspace/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.3030388403
Short name T896
Test name
Test status
Simulation time 44703364 ps
CPU time 0.7 seconds
Started Jun 10 07:45:24 PM PDT 24
Finished Jun 10 07:45:27 PM PDT 24
Peak memory 198744 kb
Host smart-736aa911-688a-4a3e-b837-9179675fdf84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030388403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3030388403
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.4175661884
Short name T604
Test name
Test status
Simulation time 101611241 ps
CPU time 0.93 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:29 PM PDT 24
Peak memory 208988 kb
Host smart-6e0248f9-0a04-4a5a-a7ad-63a9925c3fd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175661884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.4175661884
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.3942202132
Short name T343
Test name
Test status
Simulation time 262480555 ps
CPU time 1.01 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:32 PM PDT 24
Peak memory 199624 kb
Host smart-3913d166-ba12-48be-96ad-848634238faa
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942202132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_
cm_ctrl_config_regwen.3942202132
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1012774929
Short name T584
Test name
Test status
Simulation time 828816250 ps
CPU time 2.15 seconds
Started Jun 10 07:45:26 PM PDT 24
Finished Jun 10 07:45:31 PM PDT 24
Peak memory 200548 kb
Host smart-f36ed1f5-0ac2-469f-a110-be04258657ed
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012774929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1012774929
Directory /workspace/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2946179175
Short name T307
Test name
Test status
Simulation time 944956612 ps
CPU time 2.61 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:32 PM PDT 24
Peak memory 200600 kb
Host smart-91acb274-8b7c-4bd6-b00c-d27f3702656f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946179175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2946179175
Directory /workspace/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.1534831568
Short name T637
Test name
Test status
Simulation time 53940192 ps
CPU time 0.87 seconds
Started Jun 10 07:45:26 PM PDT 24
Finished Jun 10 07:45:30 PM PDT 24
Peak memory 198760 kb
Host smart-e4d74e26-cba2-440a-936e-8506da051e37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534831568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1534831568
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.4046743103
Short name T101
Test name
Test status
Simulation time 29918537 ps
CPU time 0.66 seconds
Started Jun 10 07:45:30 PM PDT 24
Finished Jun 10 07:45:34 PM PDT 24
Peak memory 198072 kb
Host smart-11f6ed49-a2fe-4c8e-a03e-70a26f88a09a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046743103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.4046743103
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all.3756557049
Short name T742
Test name
Test status
Simulation time 763576073 ps
CPU time 3.37 seconds
Started Jun 10 07:45:28 PM PDT 24
Finished Jun 10 07:45:35 PM PDT 24
Peak memory 200656 kb
Host smart-2b3ff5f9-451a-4748-9d2c-d5825ab7babb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756557049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.3756557049
Directory /workspace/13.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all_with_rand_reset.2983479611
Short name T136
Test name
Test status
Simulation time 8388666677 ps
CPU time 12.86 seconds
Started Jun 10 07:45:22 PM PDT 24
Finished Jun 10 07:45:36 PM PDT 24
Peak memory 200892 kb
Host smart-6f7cd7c0-4ec5-428e-863e-046a6fccfc58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983479611 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all_with_rand_reset.2983479611
Directory /workspace/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup.243280256
Short name T248
Test name
Test status
Simulation time 295539371 ps
CPU time 1.3 seconds
Started Jun 10 07:45:23 PM PDT 24
Finished Jun 10 07:45:25 PM PDT 24
Peak memory 199244 kb
Host smart-7d6a7bb8-989c-491d-bb22-1dc72890e67f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243280256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.243280256
Directory /workspace/13.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup_reset.169853149
Short name T579
Test name
Test status
Simulation time 226315144 ps
CPU time 0.91 seconds
Started Jun 10 07:45:24 PM PDT 24
Finished Jun 10 07:45:26 PM PDT 24
Peak memory 199152 kb
Host smart-e284ee89-dd23-4152-a19f-e6a9a2bc5da0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169853149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.169853149
Directory /workspace/13.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.85329792
Short name T767
Test name
Test status
Simulation time 45429047 ps
CPU time 0.91 seconds
Started Jun 10 07:45:26 PM PDT 24
Finished Jun 10 07:45:29 PM PDT 24
Peak memory 199672 kb
Host smart-842ed85e-c0ec-4fdf-a5ee-e98f69466279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85329792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.85329792
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.2016279267
Short name T251
Test name
Test status
Simulation time 72025232 ps
CPU time 0.72 seconds
Started Jun 10 07:45:26 PM PDT 24
Finished Jun 10 07:45:29 PM PDT 24
Peak memory 198040 kb
Host smart-6378aa57-9d8c-47f9-9a85-bd4011375bb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016279267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.2016279267
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.214821856
Short name T578
Test name
Test status
Simulation time 68585283 ps
CPU time 0.6 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:30 PM PDT 24
Peak memory 197640 kb
Host smart-3eac0001-9e01-4eee-8b32-afa65aa2b948
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214821856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_
malfunc.214821856
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.2303894217
Short name T697
Test name
Test status
Simulation time 602187097 ps
CPU time 0.94 seconds
Started Jun 10 07:45:23 PM PDT 24
Finished Jun 10 07:45:25 PM PDT 24
Peak memory 197644 kb
Host smart-b14aa11e-4a39-4c29-a95c-f8a911da668f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303894217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.2303894217
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.2020367875
Short name T875
Test name
Test status
Simulation time 49329393 ps
CPU time 0.67 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:28 PM PDT 24
Peak memory 197600 kb
Host smart-4fe6f614-5290-4ffc-ad1d-95038375ff25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020367875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.2020367875
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.1598643774
Short name T496
Test name
Test status
Simulation time 27816326 ps
CPU time 0.6 seconds
Started Jun 10 07:45:26 PM PDT 24
Finished Jun 10 07:45:28 PM PDT 24
Peak memory 197628 kb
Host smart-c4c906b6-7736-4951-a2ec-7f533c4addb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598643774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.1598643774
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.1037189581
Short name T827
Test name
Test status
Simulation time 63890672 ps
CPU time 0.67 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:28 PM PDT 24
Peak memory 200536 kb
Host smart-54639903-360f-48e2-b6dc-b199e7999846
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037189581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.1037189581
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.1826683954
Short name T711
Test name
Test status
Simulation time 211706947 ps
CPU time 0.9 seconds
Started Jun 10 07:45:21 PM PDT 24
Finished Jun 10 07:45:23 PM PDT 24
Peak memory 199088 kb
Host smart-65138a53-56cf-4330-9bfc-a31679184f86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826683954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_w
akeup_race.1826683954
Directory /workspace/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.2607492197
Short name T950
Test name
Test status
Simulation time 116693671 ps
CPU time 0.95 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:28 PM PDT 24
Peak memory 199496 kb
Host smart-8606667a-9bf4-46c0-a58f-e817854fad61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607492197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.2607492197
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.606596903
Short name T483
Test name
Test status
Simulation time 98690858 ps
CPU time 0.9 seconds
Started Jun 10 07:45:28 PM PDT 24
Finished Jun 10 07:45:32 PM PDT 24
Peak memory 200764 kb
Host smart-3729cdf6-bd84-4e12-9533-4f63cc2e5431
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606596903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.606596903
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.3397050107
Short name T490
Test name
Test status
Simulation time 60809840 ps
CPU time 0.82 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:28 PM PDT 24
Peak memory 198480 kb
Host smart-084473df-514b-4ada-a151-8e3f8f56fe11
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397050107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_
cm_ctrl_config_regwen.3397050107
Directory /workspace/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1305542043
Short name T792
Test name
Test status
Simulation time 929492680 ps
CPU time 2.5 seconds
Started Jun 10 07:45:26 PM PDT 24
Finished Jun 10 07:45:31 PM PDT 24
Peak memory 200580 kb
Host smart-5575e6be-97ab-42db-8b9f-e2ed9f6a4523
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305542043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1305542043
Directory /workspace/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3672220665
Short name T990
Test name
Test status
Simulation time 844678997 ps
CPU time 3.13 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:34 PM PDT 24
Peak memory 200588 kb
Host smart-862eee8b-a1d1-4088-a3d3-8fef5892b7ae
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672220665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3672220665
Directory /workspace/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3109002891
Short name T206
Test name
Test status
Simulation time 104062956 ps
CPU time 0.9 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:28 PM PDT 24
Peak memory 198880 kb
Host smart-d7e950cd-3e2c-4a63-8660-b8de495fc25b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109002891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3109002891
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.619947156
Short name T536
Test name
Test status
Simulation time 59662675 ps
CPU time 0.64 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:30 PM PDT 24
Peak memory 198860 kb
Host smart-5b9dc96b-acb6-4647-afed-946024755b58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619947156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.619947156
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all.2443013916
Short name T780
Test name
Test status
Simulation time 984560881 ps
CPU time 3.23 seconds
Started Jun 10 07:45:30 PM PDT 24
Finished Jun 10 07:45:37 PM PDT 24
Peak memory 200476 kb
Host smart-d8891b98-ed5f-4b30-a0c4-1b51df6bdceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443013916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.2443013916
Directory /workspace/14.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup.2983471964
Short name T666
Test name
Test status
Simulation time 314916939 ps
CPU time 0.91 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:28 PM PDT 24
Peak memory 199252 kb
Host smart-37aec9fb-a61c-4d90-9ab7-4b5f2fcb0900
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983471964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.2983471964
Directory /workspace/14.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup_reset.2208952705
Short name T12
Test name
Test status
Simulation time 112606614 ps
CPU time 0.68 seconds
Started Jun 10 07:45:24 PM PDT 24
Finished Jun 10 07:45:27 PM PDT 24
Peak memory 198864 kb
Host smart-0845e0ef-60dd-491b-914a-46a58ea0ad2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208952705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.2208952705
Directory /workspace/14.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.1820018199
Short name T660
Test name
Test status
Simulation time 181905716 ps
CPU time 0.79 seconds
Started Jun 10 07:45:29 PM PDT 24
Finished Jun 10 07:45:34 PM PDT 24
Peak memory 199452 kb
Host smart-2e06d858-9e76-4b0a-8034-d829c648959e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820018199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1820018199
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.2578419164
Short name T592
Test name
Test status
Simulation time 89949442 ps
CPU time 0.69 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:30 PM PDT 24
Peak memory 198156 kb
Host smart-94e77055-95b6-4730-8ffd-84bedef18290
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578419164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.2578419164
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.2044512010
Short name T729
Test name
Test status
Simulation time 38231846 ps
CPU time 0.59 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:31 PM PDT 24
Peak memory 196888 kb
Host smart-4c263278-21a2-488a-a8af-de77bcfd3a8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044512010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.2044512010
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.689856850
Short name T994
Test name
Test status
Simulation time 303615638 ps
CPU time 0.97 seconds
Started Jun 10 07:45:29 PM PDT 24
Finished Jun 10 07:45:33 PM PDT 24
Peak memory 197620 kb
Host smart-41bf4d81-1fd2-4836-83c3-bbd139b6f534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689856850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.689856850
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.1064481348
Short name T849
Test name
Test status
Simulation time 48781073 ps
CPU time 0.62 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:31 PM PDT 24
Peak memory 197628 kb
Host smart-93f4a1d0-d3a1-4d84-9250-2e9a4a90e982
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064481348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.1064481348
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.3434878345
Short name T596
Test name
Test status
Simulation time 155968755 ps
CPU time 0.61 seconds
Started Jun 10 07:45:28 PM PDT 24
Finished Jun 10 07:45:32 PM PDT 24
Peak memory 197628 kb
Host smart-75d6264b-d657-4864-a8de-1cb2c32e9eec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434878345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.3434878345
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.863429870
Short name T847
Test name
Test status
Simulation time 40853229 ps
CPU time 0.69 seconds
Started Jun 10 07:45:30 PM PDT 24
Finished Jun 10 07:45:34 PM PDT 24
Peak memory 200844 kb
Host smart-e36b82ec-7a15-4702-8811-abd615a135fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863429870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_invali
d.863429870
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.908335369
Short name T710
Test name
Test status
Simulation time 302134926 ps
CPU time 1.29 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:28 PM PDT 24
Peak memory 199364 kb
Host smart-c77f3482-853f-4333-bd9e-8957175de210
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908335369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wa
keup_race.908335369
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.746149455
Short name T921
Test name
Test status
Simulation time 80066753 ps
CPU time 0.82 seconds
Started Jun 10 07:45:28 PM PDT 24
Finished Jun 10 07:45:32 PM PDT 24
Peak memory 199396 kb
Host smart-0b136b82-b5b2-4a60-b087-c3fc80d539bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746149455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.746149455
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.527865684
Short name T268
Test name
Test status
Simulation time 125271744 ps
CPU time 0.85 seconds
Started Jun 10 07:45:29 PM PDT 24
Finished Jun 10 07:45:33 PM PDT 24
Peak memory 208844 kb
Host smart-16f37cd5-ffc8-4550-a8df-d224baf628bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527865684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.527865684
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.2061315222
Short name T645
Test name
Test status
Simulation time 250992374 ps
CPU time 0.96 seconds
Started Jun 10 07:45:28 PM PDT 24
Finished Jun 10 07:45:32 PM PDT 24
Peak memory 199592 kb
Host smart-cf7782c8-f94a-4893-9224-f3333f55db89
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061315222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_
cm_ctrl_config_regwen.2061315222
Directory /workspace/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3421384960
Short name T391
Test name
Test status
Simulation time 824809460 ps
CPU time 2.24 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:29 PM PDT 24
Peak memory 200608 kb
Host smart-6bdacea2-a9e5-46c9-8301-1abd9f22eda1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421384960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3421384960
Directory /workspace/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2368936039
Short name T689
Test name
Test status
Simulation time 973700651 ps
CPU time 2.55 seconds
Started Jun 10 07:45:28 PM PDT 24
Finished Jun 10 07:45:34 PM PDT 24
Peak memory 200400 kb
Host smart-212c152a-0161-40fd-af14-89816def196e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368936039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2368936039
Directory /workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.4106867855
Short name T372
Test name
Test status
Simulation time 64894375 ps
CPU time 0.91 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:32 PM PDT 24
Peak memory 198652 kb
Host smart-841d65f3-ca4e-46b0-96e5-52d88dac5c29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106867855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4106867855
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.2530603817
Short name T301
Test name
Test status
Simulation time 37207949 ps
CPU time 0.65 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:28 PM PDT 24
Peak memory 198588 kb
Host smart-9ff720d0-f9e2-4987-9087-ac691e6f0822
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530603817 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.2530603817
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all.3298018224
Short name T434
Test name
Test status
Simulation time 471420941 ps
CPU time 1.07 seconds
Started Jun 10 07:45:29 PM PDT 24
Finished Jun 10 07:45:34 PM PDT 24
Peak memory 199900 kb
Host smart-d13c4f9e-fd6b-409b-82a3-954a83029cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298018224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.3298018224
Directory /workspace/15.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all_with_rand_reset.1939642829
Short name T396
Test name
Test status
Simulation time 10747521961 ps
CPU time 32.55 seconds
Started Jun 10 07:45:29 PM PDT 24
Finished Jun 10 07:46:06 PM PDT 24
Peak memory 200868 kb
Host smart-a1209586-2ff7-4124-b569-95ca3f59a188
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939642829 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all_with_rand_reset.1939642829
Directory /workspace/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup.2135476856
Short name T196
Test name
Test status
Simulation time 257574319 ps
CPU time 0.87 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:28 PM PDT 24
Peak memory 199096 kb
Host smart-5f423aa8-1fab-4653-aed2-3e62161980f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135476856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.2135476856
Directory /workspace/15.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup_reset.685073912
Short name T810
Test name
Test status
Simulation time 232354180 ps
CPU time 1.24 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:31 PM PDT 24
Peak memory 199804 kb
Host smart-3c221ae6-7f21-4ab2-ac73-ed4ddca6dd27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685073912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.685073912
Directory /workspace/15.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.4065280791
Short name T314
Test name
Test status
Simulation time 20469450 ps
CPU time 0.66 seconds
Started Jun 10 07:45:30 PM PDT 24
Finished Jun 10 07:45:35 PM PDT 24
Peak memory 198152 kb
Host smart-90119491-50a6-47ff-a949-3d7e61fbb55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065280791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.4065280791
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.150282801
Short name T905
Test name
Test status
Simulation time 28328190 ps
CPU time 0.62 seconds
Started Jun 10 07:45:26 PM PDT 24
Finished Jun 10 07:45:29 PM PDT 24
Peak memory 197556 kb
Host smart-df07e7ed-53b4-4611-af0d-b7f28e8973d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150282801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_
malfunc.150282801
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.1959120568
Short name T835
Test name
Test status
Simulation time 1888236471 ps
CPU time 0.99 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:40 PM PDT 24
Peak memory 197976 kb
Host smart-e1452b97-8d20-44ee-b7ee-6892c049dfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959120568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.1959120568
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.4089249895
Short name T837
Test name
Test status
Simulation time 44356529 ps
CPU time 0.65 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:39 PM PDT 24
Peak memory 196884 kb
Host smart-fa6ad32d-d829-49da-8252-92a8e6fd749b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089249895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.4089249895
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.4167286712
Short name T544
Test name
Test status
Simulation time 118954074 ps
CPU time 0.62 seconds
Started Jun 10 07:45:35 PM PDT 24
Finished Jun 10 07:45:38 PM PDT 24
Peak memory 197648 kb
Host smart-28261f3d-9a62-483c-80a6-88c1aeb02e4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167286712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.4167286712
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_wakeup_race.3923375886
Short name T34
Test name
Test status
Simulation time 609139630 ps
CPU time 0.84 seconds
Started Jun 10 07:45:29 PM PDT 24
Finished Jun 10 07:45:34 PM PDT 24
Peak memory 199112 kb
Host smart-c34895a8-0a0b-4959-8cf2-f08a2fab85a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923375886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_w
akeup_race.3923375886
Directory /workspace/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.50763945
Short name T714
Test name
Test status
Simulation time 116269432 ps
CPU time 0.83 seconds
Started Jun 10 07:45:25 PM PDT 24
Finished Jun 10 07:45:28 PM PDT 24
Peak memory 199292 kb
Host smart-fc7814a1-4e75-44d4-9833-26fa8c345545
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50763945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.50763945
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.2986520406
Short name T447
Test name
Test status
Simulation time 189450971 ps
CPU time 0.81 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:39 PM PDT 24
Peak memory 208920 kb
Host smart-c78eccdf-51e1-4d69-83cc-593f947a39f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986520406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.2986520406
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.3041887713
Short name T630
Test name
Test status
Simulation time 229466806 ps
CPU time 1.12 seconds
Started Jun 10 07:45:38 PM PDT 24
Finished Jun 10 07:45:41 PM PDT 24
Peak memory 199372 kb
Host smart-2d1f6617-98a8-45af-9c8c-d2cb178c1688
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041887713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_
cm_ctrl_config_regwen.3041887713
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.252046843
Short name T836
Test name
Test status
Simulation time 1033928107 ps
CPU time 1.98 seconds
Started Jun 10 07:45:29 PM PDT 24
Finished Jun 10 07:45:35 PM PDT 24
Peak memory 200680 kb
Host smart-c0429760-4387-42b4-8172-4dda830cf540
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252046843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.252046843
Directory /workspace/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3127296054
Short name T258
Test name
Test status
Simulation time 865012854 ps
CPU time 3.24 seconds
Started Jun 10 07:45:31 PM PDT 24
Finished Jun 10 07:45:38 PM PDT 24
Peak memory 200620 kb
Host smart-a36af6ce-bb69-49e7-ae90-26e971311807
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127296054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3127296054
Directory /workspace/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.618861577
Short name T562
Test name
Test status
Simulation time 340622481 ps
CPU time 0.89 seconds
Started Jun 10 07:45:28 PM PDT 24
Finished Jun 10 07:45:32 PM PDT 24
Peak memory 198876 kb
Host smart-6a591a5a-d001-4606-a8aa-7510a9ad402b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618861577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_
mubi.618861577
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.1537684953
Short name T418
Test name
Test status
Simulation time 31811540 ps
CPU time 0.67 seconds
Started Jun 10 07:45:27 PM PDT 24
Finished Jun 10 07:45:31 PM PDT 24
Peak memory 198924 kb
Host smart-f15e91d6-7fdd-403a-8b03-d36c3e302f21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537684953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.1537684953
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all.606486125
Short name T902
Test name
Test status
Simulation time 1374352310 ps
CPU time 4.89 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:44 PM PDT 24
Peak memory 200568 kb
Host smart-193f1eb5-9252-4e4c-b8ef-0e81da3f32c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606486125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.606486125
Directory /workspace/16.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all_with_rand_reset.744946586
Short name T384
Test name
Test status
Simulation time 5706585027 ps
CPU time 18.45 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:57 PM PDT 24
Peak memory 200808 kb
Host smart-29b8007d-64ce-497f-aefb-ba49ca5609aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744946586 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all_with_rand_reset.744946586
Directory /workspace/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup_reset.3250946197
Short name T784
Test name
Test status
Simulation time 88903614 ps
CPU time 0.72 seconds
Started Jun 10 07:45:22 PM PDT 24
Finished Jun 10 07:45:24 PM PDT 24
Peak memory 198376 kb
Host smart-7ef01541-2790-444d-aba6-d72237f5f20d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250946197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.3250946197
Directory /workspace/16.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.1707911759
Short name T275
Test name
Test status
Simulation time 349595917 ps
CPU time 0.85 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:40 PM PDT 24
Peak memory 199644 kb
Host smart-9bd8a12c-cac6-409f-a93d-6e9b705e43f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707911759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.1707911759
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.4077904363
Short name T9
Test name
Test status
Simulation time 28509573 ps
CPU time 0.63 seconds
Started Jun 10 07:45:42 PM PDT 24
Finished Jun 10 07:45:46 PM PDT 24
Peak memory 196880 kb
Host smart-476bb4a6-c890-4be2-b4f5-89720ededcef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077904363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.4077904363
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.1226929849
Short name T514
Test name
Test status
Simulation time 1150006115 ps
CPU time 0.95 seconds
Started Jun 10 07:45:40 PM PDT 24
Finished Jun 10 07:45:44 PM PDT 24
Peak memory 197932 kb
Host smart-f521ed40-dc8b-4861-97b9-88fd99847696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226929849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.1226929849
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.474891981
Short name T363
Test name
Test status
Simulation time 75953603 ps
CPU time 0.61 seconds
Started Jun 10 07:45:39 PM PDT 24
Finished Jun 10 07:45:43 PM PDT 24
Peak memory 197032 kb
Host smart-6ae29e71-b760-49ee-a817-982eb72e5a71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474891981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.474891981
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.874431840
Short name T253
Test name
Test status
Simulation time 31389530 ps
CPU time 0.65 seconds
Started Jun 10 07:45:38 PM PDT 24
Finished Jun 10 07:45:41 PM PDT 24
Peak memory 197944 kb
Host smart-90b652a5-2ba4-4ffc-bcf5-044d54f7a992
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874431840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.874431840
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3762526932
Short name T453
Test name
Test status
Simulation time 91963039 ps
CPU time 0.67 seconds
Started Jun 10 07:45:42 PM PDT 24
Finished Jun 10 07:45:47 PM PDT 24
Peak memory 200780 kb
Host smart-1d180e97-5b35-4a85-831e-597dd60a25ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762526932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3762526932
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.850063672
Short name T966
Test name
Test status
Simulation time 39978623 ps
CPU time 0.71 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:40 PM PDT 24
Peak memory 197816 kb
Host smart-120637ef-614b-4d4b-ae59-9a909a612ebe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850063672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wa
keup_race.850063672
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.1172441655
Short name T723
Test name
Test status
Simulation time 116745377 ps
CPU time 0.91 seconds
Started Jun 10 07:45:36 PM PDT 24
Finished Jun 10 07:45:39 PM PDT 24
Peak memory 199516 kb
Host smart-a9c12231-4b7f-4dfd-98a8-4e1651229132
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172441655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.1172441655
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.880325251
Short name T926
Test name
Test status
Simulation time 145976595 ps
CPU time 0.85 seconds
Started Jun 10 07:45:40 PM PDT 24
Finished Jun 10 07:45:44 PM PDT 24
Peak memory 208992 kb
Host smart-06771bc5-e656-44f3-8c37-17ebf1031eb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880325251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.880325251
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.2276157635
Short name T546
Test name
Test status
Simulation time 259797954 ps
CPU time 1.32 seconds
Started Jun 10 07:45:40 PM PDT 24
Finished Jun 10 07:45:45 PM PDT 24
Peak memory 200324 kb
Host smart-d90a4de0-8ec7-4685-9da5-6f5b4c27ff8f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276157635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_
cm_ctrl_config_regwen.2276157635
Directory /workspace/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3983953532
Short name T283
Test name
Test status
Simulation time 774638045 ps
CPU time 3.02 seconds
Started Jun 10 07:45:42 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 200584 kb
Host smart-566e2fc7-7ff2-4ddc-abd0-ac641ccbda6f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983953532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3983953532
Directory /workspace/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1289559075
Short name T239
Test name
Test status
Simulation time 1253069144 ps
CPU time 2.43 seconds
Started Jun 10 07:45:42 PM PDT 24
Finished Jun 10 07:45:48 PM PDT 24
Peak memory 200552 kb
Host smart-56eb9499-46d7-4984-8155-875b503754e7
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289559075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1289559075
Directory /workspace/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.3832733393
Short name T370
Test name
Test status
Simulation time 89482049 ps
CPU time 0.84 seconds
Started Jun 10 07:45:42 PM PDT 24
Finished Jun 10 07:45:46 PM PDT 24
Peak memory 198924 kb
Host smart-42ba9ee9-ab2d-4887-91fa-5808a59eb5ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832733393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3832733393
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.2324165412
Short name T93
Test name
Test status
Simulation time 55180003 ps
CPU time 0.63 seconds
Started Jun 10 07:45:36 PM PDT 24
Finished Jun 10 07:45:39 PM PDT 24
Peak memory 198136 kb
Host smart-76f7fbc5-da02-4553-8dfd-26c1067cedcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324165412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.2324165412
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all.23566621
Short name T109
Test name
Test status
Simulation time 1204164618 ps
CPU time 3.01 seconds
Started Jun 10 07:45:40 PM PDT 24
Finished Jun 10 07:45:46 PM PDT 24
Peak memory 200676 kb
Host smart-cfc34cb0-3237-4c5e-9862-7f9422702784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23566621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.23566621
Directory /workspace/17.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all_with_rand_reset.1205879828
Short name T139
Test name
Test status
Simulation time 3159386440 ps
CPU time 10.43 seconds
Started Jun 10 07:45:44 PM PDT 24
Finished Jun 10 07:45:58 PM PDT 24
Peak memory 200828 kb
Host smart-21596da5-702e-4c63-a4ed-2be31aadf6d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205879828 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all_with_rand_reset.1205879828
Directory /workspace/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup.243723086
Short name T234
Test name
Test status
Simulation time 233826442 ps
CPU time 1.37 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:41 PM PDT 24
Peak memory 200324 kb
Host smart-de12864a-e7da-4f6f-a09d-5d21ece40ae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243723086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.243723086
Directory /workspace/17.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup_reset.2067959649
Short name T813
Test name
Test status
Simulation time 387148164 ps
CPU time 1.16 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:40 PM PDT 24
Peak memory 200580 kb
Host smart-9d6c1ba8-aebf-46ed-84a7-f7ae7bf70614
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067959649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.2067959649
Directory /workspace/17.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.4209502836
Short name T134
Test name
Test status
Simulation time 32974100 ps
CPU time 1.06 seconds
Started Jun 10 07:45:44 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 200440 kb
Host smart-3feaf6ac-40d9-435c-8576-c3a6e11bf2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209502836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.4209502836
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.543801023
Short name T27
Test name
Test status
Simulation time 54053585 ps
CPU time 0.75 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 198608 kb
Host smart-643c48f7-612e-4240-b1e4-bc7f03399cc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543801023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disa
ble_rom_integrity_check.543801023
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.2995620142
Short name T614
Test name
Test status
Simulation time 31900399 ps
CPU time 0.61 seconds
Started Jun 10 07:45:38 PM PDT 24
Finished Jun 10 07:45:42 PM PDT 24
Peak memory 197532 kb
Host smart-7a62093a-6141-46b6-8780-328f1595d9ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995620142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.2995620142
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.967516814
Short name T550
Test name
Test status
Simulation time 1072956308 ps
CPU time 0.9 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 197640 kb
Host smart-20711d5d-9d3d-4480-8a1b-fdd26e57ecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967516814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.967516814
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.2575095383
Short name T680
Test name
Test status
Simulation time 40296817 ps
CPU time 0.59 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 197716 kb
Host smart-d9ef170b-b8d6-4144-951f-df3b730c7e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575095383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.2575095383
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.1661515599
Short name T222
Test name
Test status
Simulation time 74981926 ps
CPU time 0.6 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 197912 kb
Host smart-a47e9d74-f1cb-4910-ad74-57d648a0faea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661515599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1661515599
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.885797616
Short name T412
Test name
Test status
Simulation time 112361764 ps
CPU time 0.65 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 200824 kb
Host smart-eb056f22-1f44-4b49-aaa3-d29a0523e100
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885797616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invali
d.885797616
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.2055476090
Short name T770
Test name
Test status
Simulation time 63815040 ps
CPU time 0.66 seconds
Started Jun 10 07:45:47 PM PDT 24
Finished Jun 10 07:45:51 PM PDT 24
Peak memory 198624 kb
Host smart-d656751e-2df8-4fff-b11c-c06fdcf9d472
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055476090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_w
akeup_race.2055476090
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.430527281
Short name T481
Test name
Test status
Simulation time 99831110 ps
CPU time 0.79 seconds
Started Jun 10 07:45:42 PM PDT 24
Finished Jun 10 07:45:47 PM PDT 24
Peak memory 199292 kb
Host smart-53a47622-49ab-4925-bd97-9fef56840bd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430527281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.430527281
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.4054692836
Short name T386
Test name
Test status
Simulation time 140101997 ps
CPU time 0.87 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:50 PM PDT 24
Peak memory 200824 kb
Host smart-48db4430-3205-467d-bf59-5f3d7d68932a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054692836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.4054692836
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.463130101
Short name T512
Test name
Test status
Simulation time 113068984 ps
CPU time 0.65 seconds
Started Jun 10 07:45:44 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 198108 kb
Host smart-39c715f8-a9df-4e6e-808b-d7f4443cac95
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463130101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_c
m_ctrl_config_regwen.463130101
Directory /workspace/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3019509592
Short name T790
Test name
Test status
Simulation time 880440371 ps
CPU time 3.02 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:52 PM PDT 24
Peak memory 200608 kb
Host smart-a1d35ac9-0bd8-496a-bb93-d32605c9f4cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019509592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3019509592
Directory /workspace/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.59191360
Short name T335
Test name
Test status
Simulation time 988333069 ps
CPU time 2.7 seconds
Started Jun 10 07:45:43 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 200572 kb
Host smart-3de2598f-d1e6-412a-b90a-c76df320a2a8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59191360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.59191360
Directory /workspace/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.2691594146
Short name T4
Test name
Test status
Simulation time 192765695 ps
CPU time 0.91 seconds
Started Jun 10 07:45:42 PM PDT 24
Finished Jun 10 07:45:47 PM PDT 24
Peak memory 198900 kb
Host smart-d32b60b2-3bda-48c8-a89e-155a626d36ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691594146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2691594146
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.3212233267
Short name T387
Test name
Test status
Simulation time 31907113 ps
CPU time 0.71 seconds
Started Jun 10 07:45:41 PM PDT 24
Finished Jun 10 07:45:45 PM PDT 24
Peak memory 198924 kb
Host smart-040ffdc5-3a15-404e-bfd6-4be19fff63b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212233267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.3212233267
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all.957049754
Short name T482
Test name
Test status
Simulation time 2021886749 ps
CPU time 6 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:55 PM PDT 24
Peak memory 200704 kb
Host smart-d5a2fd3f-ac32-49d3-9e52-a0f2ee486a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957049754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.957049754
Directory /workspace/18.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all_with_rand_reset.3852429056
Short name T978
Test name
Test status
Simulation time 12407047863 ps
CPU time 37.3 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:46:26 PM PDT 24
Peak memory 200980 kb
Host smart-72b4157f-1327-4110-bee2-6b49561231f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852429056 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all_with_rand_reset.3852429056
Directory /workspace/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.3004623969
Short name T164
Test name
Test status
Simulation time 230803519 ps
CPU time 1.22 seconds
Started Jun 10 07:45:38 PM PDT 24
Finished Jun 10 07:45:43 PM PDT 24
Peak memory 199292 kb
Host smart-1433be17-9d55-4ba3-ac3b-8a906f8d33bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004623969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.3004623969
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup_reset.431396049
Short name T532
Test name
Test status
Simulation time 286672342 ps
CPU time 1.12 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:50 PM PDT 24
Peak memory 200552 kb
Host smart-7aee311b-0c95-44e5-b0b2-929dbb94196d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431396049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.431396049
Directory /workspace/18.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.158074410
Short name T484
Test name
Test status
Simulation time 41334604 ps
CPU time 0.79 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:40 PM PDT 24
Peak memory 199588 kb
Host smart-ab9c1ab2-5fa0-4a4e-99af-944ec11bb9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158074410 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.158074410
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.32839570
Short name T843
Test name
Test status
Simulation time 77599764 ps
CPU time 0.71 seconds
Started Jun 10 07:45:39 PM PDT 24
Finished Jun 10 07:45:43 PM PDT 24
Peak memory 198040 kb
Host smart-519e1ea1-dc32-492b-a36b-7440d3288cd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32839570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disab
le_rom_integrity_check.32839570
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.2655711300
Short name T858
Test name
Test status
Simulation time 38162830 ps
CPU time 0.58 seconds
Started Jun 10 07:45:38 PM PDT 24
Finished Jun 10 07:45:41 PM PDT 24
Peak memory 197572 kb
Host smart-918a09c6-9dc8-4d37-8f2a-0f91cefe3345
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655711300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.2655711300
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.918300065
Short name T324
Test name
Test status
Simulation time 607858922 ps
CPU time 0.95 seconds
Started Jun 10 07:45:36 PM PDT 24
Finished Jun 10 07:45:39 PM PDT 24
Peak memory 197660 kb
Host smart-413fd42c-5df4-4fbc-9cf7-cfc756ff0fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918300065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.918300065
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.1246740814
Short name T102
Test name
Test status
Simulation time 57401696 ps
CPU time 0.69 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:40 PM PDT 24
Peak memory 196884 kb
Host smart-4ff8ebca-cc4b-4338-ab35-7907c6fd368c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246740814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.1246740814
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.2291049316
Short name T92
Test name
Test status
Simulation time 44474245 ps
CPU time 0.65 seconds
Started Jun 10 07:45:47 PM PDT 24
Finished Jun 10 07:45:51 PM PDT 24
Peak memory 197616 kb
Host smart-28289d64-ba8c-4da2-a527-0c13e6bbd2ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291049316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.2291049316
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.2256560152
Short name T907
Test name
Test status
Simulation time 42109498 ps
CPU time 0.71 seconds
Started Jun 10 07:45:39 PM PDT 24
Finished Jun 10 07:45:43 PM PDT 24
Peak memory 200752 kb
Host smart-fa0f6cbb-79f7-4917-be17-411d37a0292d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256560152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.2256560152
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.3392594123
Short name T653
Test name
Test status
Simulation time 258606354 ps
CPU time 1.27 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:50 PM PDT 24
Peak memory 199044 kb
Host smart-353e8447-23eb-469f-b9dc-6334dfb6565a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392594123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_w
akeup_race.3392594123
Directory /workspace/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.1425184043
Short name T278
Test name
Test status
Simulation time 45218800 ps
CPU time 0.76 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 198336 kb
Host smart-3b8cc6f1-b97c-4559-8783-7cb34693d003
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425184043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.1425184043
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.1285541375
Short name T555
Test name
Test status
Simulation time 167231832 ps
CPU time 0.77 seconds
Started Jun 10 07:45:36 PM PDT 24
Finished Jun 10 07:45:39 PM PDT 24
Peak memory 208912 kb
Host smart-2230f17b-7e5b-47c0-aed0-dfc280dba857
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285541375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.1285541375
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.4210192942
Short name T888
Test name
Test status
Simulation time 254907314 ps
CPU time 1.21 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:41 PM PDT 24
Peak memory 199528 kb
Host smart-ff256071-ff85-4758-b541-6f10681ffb33
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210192942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_
cm_ctrl_config_regwen.4210192942
Directory /workspace/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2596017386
Short name T468
Test name
Test status
Simulation time 1696784243 ps
CPU time 2.08 seconds
Started Jun 10 07:45:35 PM PDT 24
Finished Jun 10 07:45:39 PM PDT 24
Peak memory 200640 kb
Host smart-45873ec4-24c2-49d8-866d-bd8b89f63755
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596017386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2596017386
Directory /workspace/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3176430296
Short name T419
Test name
Test status
Simulation time 784784244 ps
CPU time 3.4 seconds
Started Jun 10 07:45:34 PM PDT 24
Finished Jun 10 07:45:40 PM PDT 24
Peak memory 200624 kb
Host smart-563cae12-da25-480b-b505-967ea89a0a09
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176430296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3176430296
Directory /workspace/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.938579027
Short name T727
Test name
Test status
Simulation time 714696094 ps
CPU time 0.88 seconds
Started Jun 10 07:45:35 PM PDT 24
Finished Jun 10 07:45:38 PM PDT 24
Peak memory 198736 kb
Host smart-03bec0b4-2f34-4113-aa0f-945442efad63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938579027 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_
mubi.938579027
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.1997840674
Short name T221
Test name
Test status
Simulation time 59649326 ps
CPU time 0.63 seconds
Started Jun 10 07:45:40 PM PDT 24
Finished Jun 10 07:45:44 PM PDT 24
Peak memory 198932 kb
Host smart-68914c88-2003-406f-af3e-cd58d0475f93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997840674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.1997840674
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all.4044018784
Short name T768
Test name
Test status
Simulation time 609788193 ps
CPU time 2.43 seconds
Started Jun 10 07:45:39 PM PDT 24
Finished Jun 10 07:45:45 PM PDT 24
Peak memory 200660 kb
Host smart-c04bf2af-1b72-4513-ae61-6fcebc85f965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044018784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.4044018784
Directory /workspace/19.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all_with_rand_reset.3117609869
Short name T795
Test name
Test status
Simulation time 7611154494 ps
CPU time 11.82 seconds
Started Jun 10 07:45:38 PM PDT 24
Finished Jun 10 07:45:53 PM PDT 24
Peak memory 200908 kb
Host smart-000215df-355e-4f39-9ed7-54b50c4854b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117609869 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all_with_rand_reset.3117609869
Directory /workspace/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup.1393891582
Short name T936
Test name
Test status
Simulation time 43056148 ps
CPU time 0.63 seconds
Started Jun 10 07:45:37 PM PDT 24
Finished Jun 10 07:45:40 PM PDT 24
Peak memory 197772 kb
Host smart-565b164c-17fc-4ddf-b6df-19cdefc75c66
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393891582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.1393891582
Directory /workspace/19.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup_reset.90000062
Short name T322
Test name
Test status
Simulation time 103030743 ps
CPU time 0.88 seconds
Started Jun 10 07:45:39 PM PDT 24
Finished Jun 10 07:45:43 PM PDT 24
Peak memory 198964 kb
Host smart-6a706b0c-48a5-4f69-83ac-8e272ebd788e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90000062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.90000062
Directory /workspace/19.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.924281702
Short name T498
Test name
Test status
Simulation time 74981176 ps
CPU time 0.85 seconds
Started Jun 10 07:44:42 PM PDT 24
Finished Jun 10 07:44:49 PM PDT 24
Peak memory 199764 kb
Host smart-818297c2-4e5f-4e9c-8409-21c3e181291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924281702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.924281702
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.3512759208
Short name T293
Test name
Test status
Simulation time 81939380 ps
CPU time 0.65 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 198180 kb
Host smart-7c456111-0cc7-4214-a72e-f123f4ca777e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512759208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.3512759208
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2657283895
Short name T788
Test name
Test status
Simulation time 30208689 ps
CPU time 0.64 seconds
Started Jun 10 07:44:40 PM PDT 24
Finished Jun 10 07:44:46 PM PDT 24
Peak memory 197644 kb
Host smart-6c2b8f69-1ae8-4022-a114-5bff929c69e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657283895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.2657283895
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.2205736344
Short name T339
Test name
Test status
Simulation time 632551754 ps
CPU time 0.97 seconds
Started Jun 10 07:44:40 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 198028 kb
Host smart-54ca5ef6-6b45-435b-ad40-53efc3759674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205736344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2205736344
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.4064349024
Short name T642
Test name
Test status
Simulation time 36188770 ps
CPU time 0.59 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:51 PM PDT 24
Peak memory 197556 kb
Host smart-8595f972-5d3c-4a13-9ecf-a938c6d6d799
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064349024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.4064349024
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.3556859248
Short name T688
Test name
Test status
Simulation time 71788804 ps
CPU time 0.6 seconds
Started Jun 10 07:44:41 PM PDT 24
Finished Jun 10 07:44:47 PM PDT 24
Peak memory 198020 kb
Host smart-a2f5e05a-e740-4c21-95f9-c83658c6a669
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556859248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.3556859248
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2389394646
Short name T417
Test name
Test status
Simulation time 44518975 ps
CPU time 0.7 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:51 PM PDT 24
Peak memory 200816 kb
Host smart-c49e460b-0119-496d-9e92-7b1e0b03224e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389394646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2389394646
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.4280487669
Short name T825
Test name
Test status
Simulation time 194636845 ps
CPU time 1.03 seconds
Started Jun 10 07:44:41 PM PDT 24
Finished Jun 10 07:44:47 PM PDT 24
Peak memory 199256 kb
Host smart-8fcbed5c-75b5-44b4-bd47-72005954da60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280487669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wa
keup_race.4280487669
Directory /workspace/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.3704557655
Short name T670
Test name
Test status
Simulation time 48149634 ps
CPU time 0.62 seconds
Started Jun 10 07:44:40 PM PDT 24
Finished Jun 10 07:44:46 PM PDT 24
Peak memory 197840 kb
Host smart-2f519718-163e-4100-9bed-f838f654380b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704557655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.3704557655
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.201485993
Short name T585
Test name
Test status
Simulation time 101078151 ps
CPU time 0.97 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 208864 kb
Host smart-56a8cd13-cc5e-4df6-abd1-a5715c1726d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201485993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.201485993
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1980702139
Short name T30
Test name
Test status
Simulation time 374525898 ps
CPU time 1.23 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 216440 kb
Host smart-5102a1e9-95fe-4a96-aaa3-d94cec496823
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980702139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1980702139
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.859901460
Short name T716
Test name
Test status
Simulation time 780786443 ps
CPU time 3.06 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:47 PM PDT 24
Peak memory 200588 kb
Host smart-9b68a1fe-ae40-41eb-8129-53bc4ed207ba
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859901460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.859901460
Directory /workspace/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1482030785
Short name T160
Test name
Test status
Simulation time 67389520 ps
CPU time 0.98 seconds
Started Jun 10 07:44:46 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 198896 kb
Host smart-9d1a10db-6818-4ce5-9c56-4693acae9c73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482030785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1482030785
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.1110999024
Short name T360
Test name
Test status
Simulation time 38810977 ps
CPU time 0.63 seconds
Started Jun 10 07:44:40 PM PDT 24
Finished Jun 10 07:44:46 PM PDT 24
Peak memory 198128 kb
Host smart-d0496e68-5b09-4945-8849-64d35c51e5f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110999024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.1110999024
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all.2684162657
Short name T701
Test name
Test status
Simulation time 1490144603 ps
CPU time 2.33 seconds
Started Jun 10 07:44:42 PM PDT 24
Finished Jun 10 07:44:50 PM PDT 24
Peak memory 200616 kb
Host smart-e4e6fe10-138d-4ea0-94fb-6a5ea4fa565c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684162657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.2684162657
Directory /workspace/2.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all_with_rand_reset.1819085707
Short name T977
Test name
Test status
Simulation time 6490504320 ps
CPU time 9.08 seconds
Started Jun 10 07:44:38 PM PDT 24
Finished Jun 10 07:44:51 PM PDT 24
Peak memory 200888 kb
Host smart-8bac5e7b-c2ad-458a-976c-7bd906e8757c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819085707 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all_with_rand_reset.1819085707
Directory /workspace/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup.1299194044
Short name T228
Test name
Test status
Simulation time 244452372 ps
CPU time 1.31 seconds
Started Jun 10 07:44:42 PM PDT 24
Finished Jun 10 07:44:49 PM PDT 24
Peak memory 199272 kb
Host smart-de668a54-8d57-4d78-9273-47985a665634
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299194044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.1299194044
Directory /workspace/2.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup_reset.2442956897
Short name T303
Test name
Test status
Simulation time 208709446 ps
CPU time 0.73 seconds
Started Jun 10 07:44:42 PM PDT 24
Finished Jun 10 07:44:48 PM PDT 24
Peak memory 198992 kb
Host smart-c79dbc0a-6b08-41b2-ab1f-ba1ac79a26f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442956897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.2442956897
Directory /workspace/2.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.385649150
Short name T613
Test name
Test status
Simulation time 60745210 ps
CPU time 0.8 seconds
Started Jun 10 07:45:41 PM PDT 24
Finished Jun 10 07:45:45 PM PDT 24
Peak memory 199612 kb
Host smart-851f3164-8a54-4da2-82aa-dd76f7810100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385649150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.385649150
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.2520639300
Short name T930
Test name
Test status
Simulation time 66136670 ps
CPU time 0.69 seconds
Started Jun 10 07:45:42 PM PDT 24
Finished Jun 10 07:45:47 PM PDT 24
Peak memory 198576 kb
Host smart-272cdf55-64b2-4de8-876f-d16c72764460
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520639300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.2520639300
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3725332227
Short name T702
Test name
Test status
Simulation time 76875336 ps
CPU time 0.59 seconds
Started Jun 10 07:45:39 PM PDT 24
Finished Jun 10 07:45:43 PM PDT 24
Peak memory 197620 kb
Host smart-f03c3705-cf48-498a-b4c1-4feba44f456f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725332227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.3725332227
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.4179227043
Short name T567
Test name
Test status
Simulation time 314419512 ps
CPU time 0.95 seconds
Started Jun 10 07:45:42 PM PDT 24
Finished Jun 10 07:45:46 PM PDT 24
Peak memory 197588 kb
Host smart-1732e6d0-379b-46f2-bbb3-cded36e60044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179227043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.4179227043
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.2224103998
Short name T923
Test name
Test status
Simulation time 33955499 ps
CPU time 0.67 seconds
Started Jun 10 07:45:40 PM PDT 24
Finished Jun 10 07:45:44 PM PDT 24
Peak memory 197556 kb
Host smart-596d34b3-e911-444c-b68f-9c792e27285b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224103998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.2224103998
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.2990675876
Short name T918
Test name
Test status
Simulation time 76160210 ps
CPU time 0.63 seconds
Started Jun 10 07:45:43 PM PDT 24
Finished Jun 10 07:45:47 PM PDT 24
Peak memory 197644 kb
Host smart-cf22c298-a460-4478-9e33-90ceebaec01b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990675876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.2990675876
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.2777848420
Short name T669
Test name
Test status
Simulation time 53095063 ps
CPU time 0.69 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 200780 kb
Host smart-61ab1edc-c4ba-48e2-82bc-ca3483caa7dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777848420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.2777848420
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.786929199
Short name T541
Test name
Test status
Simulation time 255766932 ps
CPU time 1.26 seconds
Started Jun 10 07:45:40 PM PDT 24
Finished Jun 10 07:45:44 PM PDT 24
Peak memory 199108 kb
Host smart-c4944659-6e6b-434d-8de8-363e8ef54a8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786929199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_wa
keup_race.786929199
Directory /workspace/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.311529885
Short name T39
Test name
Test status
Simulation time 88513541 ps
CPU time 0.84 seconds
Started Jun 10 07:45:41 PM PDT 24
Finished Jun 10 07:45:46 PM PDT 24
Peak memory 198384 kb
Host smart-f3ae36f2-0dd6-4d6b-bc22-b37169133bad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311529885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.311529885
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.3895206047
Short name T947
Test name
Test status
Simulation time 127461304 ps
CPU time 0.8 seconds
Started Jun 10 07:45:44 PM PDT 24
Finished Jun 10 07:45:48 PM PDT 24
Peak memory 200756 kb
Host smart-db482fc1-955b-4254-8dae-92a2e9b5716c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895206047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3895206047
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.3832933614
Short name T407
Test name
Test status
Simulation time 121952564 ps
CPU time 0.82 seconds
Started Jun 10 07:45:44 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 199328 kb
Host smart-4973c2ec-50c9-4be9-89c4-eabab496da1f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832933614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_
cm_ctrl_config_regwen.3832933614
Directory /workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1788383337
Short name T479
Test name
Test status
Simulation time 818999373 ps
CPU time 3.36 seconds
Started Jun 10 07:45:39 PM PDT 24
Finished Jun 10 07:45:45 PM PDT 24
Peak memory 200672 kb
Host smart-bab2ae79-d3eb-48ec-9c98-621b3ab3b7e8
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788383337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1788383337
Directory /workspace/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.676833544
Short name T214
Test name
Test status
Simulation time 920983259 ps
CPU time 2.22 seconds
Started Jun 10 07:45:42 PM PDT 24
Finished Jun 10 07:45:48 PM PDT 24
Peak memory 200392 kb
Host smart-0e12286c-a757-470f-b379-17350be73049
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676833544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.676833544
Directory /workspace/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.1235690463
Short name T595
Test name
Test status
Simulation time 67180323 ps
CPU time 0.67 seconds
Started Jun 10 07:45:39 PM PDT 24
Finished Jun 10 07:45:43 PM PDT 24
Peak memory 198064 kb
Host smart-aa3954d3-967b-4604-86f6-16f29b20c970
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235690463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.1235690463
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all.523085063
Short name T740
Test name
Test status
Simulation time 308290547 ps
CPU time 1.3 seconds
Started Jun 10 07:45:38 PM PDT 24
Finished Jun 10 07:45:41 PM PDT 24
Peak memory 200576 kb
Host smart-b7483773-a998-4b62-8e7a-3a3746142ff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523085063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.523085063
Directory /workspace/20.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup.2445557093
Short name T441
Test name
Test status
Simulation time 108240334 ps
CPU time 0.75 seconds
Started Jun 10 07:45:40 PM PDT 24
Finished Jun 10 07:45:43 PM PDT 24
Peak memory 197992 kb
Host smart-b04f77ca-f229-486b-9ad2-2f8e82377aca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445557093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.2445557093
Directory /workspace/20.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup_reset.2410720029
Short name T922
Test name
Test status
Simulation time 247670179 ps
CPU time 1.09 seconds
Started Jun 10 07:45:40 PM PDT 24
Finished Jun 10 07:45:45 PM PDT 24
Peak memory 199912 kb
Host smart-f6e8bec2-fadc-4894-af2e-c4785ec262cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410720029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.2410720029
Directory /workspace/20.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.1001671324
Short name T791
Test name
Test status
Simulation time 38445387 ps
CPU time 0.84 seconds
Started Jun 10 07:45:43 PM PDT 24
Finished Jun 10 07:45:47 PM PDT 24
Peak memory 199592 kb
Host smart-00560748-fa9b-426a-9809-44a5e89a4c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001671324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.1001671324
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.3071013719
Short name T968
Test name
Test status
Simulation time 87685394 ps
CPU time 0.69 seconds
Started Jun 10 07:45:47 PM PDT 24
Finished Jun 10 07:45:51 PM PDT 24
Peak memory 198664 kb
Host smart-ab3b4b22-c3aa-4876-bb57-1508672b47e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071013719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.3071013719
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.4187624806
Short name T556
Test name
Test status
Simulation time 45626800 ps
CPU time 0.57 seconds
Started Jun 10 07:45:39 PM PDT 24
Finished Jun 10 07:45:43 PM PDT 24
Peak memory 197644 kb
Host smart-7767f8a2-6657-4b2c-84a6-805fdd78b323
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187624806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.4187624806
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.1274694445
Short name T480
Test name
Test status
Simulation time 161878741 ps
CPU time 0.94 seconds
Started Jun 10 07:45:46 PM PDT 24
Finished Jun 10 07:45:51 PM PDT 24
Peak memory 197940 kb
Host smart-0a49ae1d-f604-4d9d-aa8b-d834bb9e2b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274694445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1274694445
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.3839049778
Short name T17
Test name
Test status
Simulation time 38013797 ps
CPU time 0.6 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:56 PM PDT 24
Peak memory 197588 kb
Host smart-ea49ea6a-ba09-4f5f-9fde-e25b4dff5d95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839049778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.3839049778
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.2188758186
Short name T914
Test name
Test status
Simulation time 52101621 ps
CPU time 0.63 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:57 PM PDT 24
Peak memory 197724 kb
Host smart-86ad5d95-5c34-46c6-b60f-e1299b66b059
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188758186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.2188758186
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.2869812521
Short name T535
Test name
Test status
Simulation time 83052779 ps
CPU time 0.77 seconds
Started Jun 10 07:45:57 PM PDT 24
Finished Jun 10 07:46:00 PM PDT 24
Peak memory 200804 kb
Host smart-79bf7825-4b80-4869-85d3-9ecf50c9630f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869812521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.2869812521
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.1978513441
Short name T720
Test name
Test status
Simulation time 486972886 ps
CPU time 0.97 seconds
Started Jun 10 07:45:44 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 199360 kb
Host smart-af03404f-1321-4b77-8947-070caafe23c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978513441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_w
akeup_race.1978513441
Directory /workspace/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.213482977
Short name T548
Test name
Test status
Simulation time 210593731 ps
CPU time 0.9 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 199472 kb
Host smart-02a32b40-2fba-405c-a887-701fd1e5d11c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213482977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.213482977
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.3931899881
Short name T961
Test name
Test status
Simulation time 115310579 ps
CPU time 0.86 seconds
Started Jun 10 07:45:51 PM PDT 24
Finished Jun 10 07:45:54 PM PDT 24
Peak memory 208956 kb
Host smart-b92adfba-77c4-43be-bdcf-e8eeacdb7447
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931899881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.3931899881
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.4172896107
Short name T304
Test name
Test status
Simulation time 278863020 ps
CPU time 0.97 seconds
Started Jun 10 07:45:49 PM PDT 24
Finished Jun 10 07:45:53 PM PDT 24
Peak memory 199644 kb
Host smart-dd8fb5f0-8f88-44a3-ad60-57d1ce8593c8
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172896107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_
cm_ctrl_config_regwen.4172896107
Directory /workspace/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2261561115
Short name T913
Test name
Test status
Simulation time 1932765838 ps
CPU time 1.96 seconds
Started Jun 10 07:45:44 PM PDT 24
Finished Jun 10 07:45:50 PM PDT 24
Peak memory 200728 kb
Host smart-4fabc73f-4232-48bc-8f31-2bd5ef24bfac
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261561115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2261561115
Directory /workspace/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.68542314
Short name T695
Test name
Test status
Simulation time 810080724 ps
CPU time 3.32 seconds
Started Jun 10 07:45:44 PM PDT 24
Finished Jun 10 07:45:51 PM PDT 24
Peak memory 200632 kb
Host smart-913c393a-5426-4992-b573-e7012a04edc0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68542314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.68542314
Directory /workspace/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.1211216908
Short name T347
Test name
Test status
Simulation time 152598737 ps
CPU time 0.95 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:50 PM PDT 24
Peak memory 198952 kb
Host smart-646c1a52-67fd-4e41-83ef-f935a7076080
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211216908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1211216908
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.760196543
Short name T591
Test name
Test status
Simulation time 29975952 ps
CPU time 0.66 seconds
Started Jun 10 07:45:43 PM PDT 24
Finished Jun 10 07:45:47 PM PDT 24
Peak memory 197984 kb
Host smart-eb6ae39a-bf10-4555-8274-ceb69b4c4965
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760196543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.760196543
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all.28796254
Short name T829
Test name
Test status
Simulation time 969875612 ps
CPU time 4.34 seconds
Started Jun 10 07:45:52 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 200684 kb
Host smart-75e2a90f-5283-4138-9cea-7257e7d618a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28796254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.28796254
Directory /workspace/21.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all_with_rand_reset.4069393342
Short name T991
Test name
Test status
Simulation time 11634125622 ps
CPU time 8.82 seconds
Started Jun 10 07:45:51 PM PDT 24
Finished Jun 10 07:46:02 PM PDT 24
Peak memory 200820 kb
Host smart-1a9b453e-5427-4a45-b14f-497fe96aa674
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069393342 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all_with_rand_reset.4069393342
Directory /workspace/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup.529016506
Short name T802
Test name
Test status
Simulation time 336874146 ps
CPU time 1.12 seconds
Started Jun 10 07:45:43 PM PDT 24
Finished Jun 10 07:45:48 PM PDT 24
Peak memory 199352 kb
Host smart-30e339d1-aa78-448a-8e10-e43bd7cbbd68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529016506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.529016506
Directory /workspace/21.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup_reset.3350734109
Short name T785
Test name
Test status
Simulation time 357103321 ps
CPU time 0.95 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:45:50 PM PDT 24
Peak memory 199472 kb
Host smart-af36e8f4-d323-4723-a6be-433459d3ed14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350734109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.3350734109
Directory /workspace/21.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.3148901148
Short name T405
Test name
Test status
Simulation time 47294393 ps
CPU time 0.94 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:57 PM PDT 24
Peak memory 200332 kb
Host smart-d4d5f9ad-717a-4e86-ac6f-def79552703f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148901148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.3148901148
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.499256976
Short name T764
Test name
Test status
Simulation time 59595483 ps
CPU time 0.69 seconds
Started Jun 10 07:45:56 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 197916 kb
Host smart-1426ecdf-fa8a-457e-bb5f-5f9d040689b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499256976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disa
ble_rom_integrity_check.499256976
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.1313936398
Short name T627
Test name
Test status
Simulation time 30818560 ps
CPU time 0.63 seconds
Started Jun 10 07:45:47 PM PDT 24
Finished Jun 10 07:45:51 PM PDT 24
Peak memory 196864 kb
Host smart-3daa850f-27cf-4c57-a181-83031210df90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313936398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.1313936398
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.2463305129
Short name T806
Test name
Test status
Simulation time 632395086 ps
CPU time 0.97 seconds
Started Jun 10 07:45:55 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 197896 kb
Host smart-e7c4594a-5eed-4868-a0f2-997d86fd68d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463305129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2463305129
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.2063734295
Short name T677
Test name
Test status
Simulation time 45821796 ps
CPU time 0.68 seconds
Started Jun 10 07:45:55 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 197584 kb
Host smart-03a0769f-4ad9-464b-a250-9ccb59dfbffe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063734295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2063734295
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.1043610922
Short name T874
Test name
Test status
Simulation time 47063958 ps
CPU time 0.61 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:57 PM PDT 24
Peak memory 197592 kb
Host smart-0d2321d9-7ba7-4ae0-833c-a16ce9f88404
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043610922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.1043610922
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.134264826
Short name T32
Test name
Test status
Simulation time 43952717 ps
CPU time 0.73 seconds
Started Jun 10 07:45:56 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 200748 kb
Host smart-baea8329-3dd1-4ff7-b282-1fa904cd1775
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134264826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invali
d.134264826
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_wakeup_race.2239522978
Short name T520
Test name
Test status
Simulation time 182807385 ps
CPU time 0.77 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:56 PM PDT 24
Peak memory 198692 kb
Host smart-dba3ac32-4817-4894-90d6-8dabafe91fcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239522978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_w
akeup_race.2239522978
Directory /workspace/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.800779071
Short name T878
Test name
Test status
Simulation time 37799839 ps
CPU time 0.64 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:56 PM PDT 24
Peak memory 197584 kb
Host smart-72a15c10-f270-478a-ad57-92b5c24e6cfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800779071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.800779071
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.1608064335
Short name T216
Test name
Test status
Simulation time 150784843 ps
CPU time 0.88 seconds
Started Jun 10 07:45:54 PM PDT 24
Finished Jun 10 07:45:58 PM PDT 24
Peak memory 208844 kb
Host smart-9da95198-0c58-4ce6-9945-03ed2c5b1f79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608064335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.1608064335
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.2337847949
Short name T709
Test name
Test status
Simulation time 293914803 ps
CPU time 0.83 seconds
Started Jun 10 07:45:52 PM PDT 24
Finished Jun 10 07:45:56 PM PDT 24
Peak memory 198756 kb
Host smart-e0094f2a-ffcf-44a1-9bff-b985668fa919
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337847949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_
cm_ctrl_config_regwen.2337847949
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.925233453
Short name T316
Test name
Test status
Simulation time 1142054543 ps
CPU time 2.09 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:58 PM PDT 24
Peak memory 200588 kb
Host smart-1a22c80f-da2c-4da6-803e-17f93fe07050
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925233453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.925233453
Directory /workspace/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.832419747
Short name T581
Test name
Test status
Simulation time 1082251702 ps
CPU time 2.61 seconds
Started Jun 10 07:45:48 PM PDT 24
Finished Jun 10 07:45:54 PM PDT 24
Peak memory 200624 kb
Host smart-a17a88bc-250e-44e3-9bae-61d5dd109fa6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832419747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.832419747
Directory /workspace/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.4264896483
Short name T356
Test name
Test status
Simulation time 222966092 ps
CPU time 0.8 seconds
Started Jun 10 07:45:51 PM PDT 24
Finished Jun 10 07:45:54 PM PDT 24
Peak memory 198892 kb
Host smart-21fe9f23-881b-4429-9923-56d75b966798
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264896483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4264896483
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.3945010098
Short name T676
Test name
Test status
Simulation time 66370488 ps
CPU time 0.61 seconds
Started Jun 10 07:45:48 PM PDT 24
Finished Jun 10 07:45:52 PM PDT 24
Peak memory 198932 kb
Host smart-189f7f8f-7625-48ac-aba3-7abebf00eea4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945010098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.3945010098
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all_with_rand_reset.2452511113
Short name T48
Test name
Test status
Simulation time 5699700382 ps
CPU time 14.27 seconds
Started Jun 10 07:45:45 PM PDT 24
Finished Jun 10 07:46:03 PM PDT 24
Peak memory 200848 kb
Host smart-f6064b76-2895-4444-bce6-be46f072e17e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452511113 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all_with_rand_reset.2452511113
Directory /workspace/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup.1793011698
Short name T654
Test name
Test status
Simulation time 33813901 ps
CPU time 0.66 seconds
Started Jun 10 07:45:47 PM PDT 24
Finished Jun 10 07:45:51 PM PDT 24
Peak memory 197804 kb
Host smart-20df8d82-8af0-41ba-bb70-a3e2bab38fca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793011698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.1793011698
Directory /workspace/22.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup_reset.1056646906
Short name T975
Test name
Test status
Simulation time 191014329 ps
CPU time 0.69 seconds
Started Jun 10 07:45:46 PM PDT 24
Finished Jun 10 07:45:50 PM PDT 24
Peak memory 198072 kb
Host smart-3990a6bc-f510-4e19-82cb-2dbe4c231432
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056646906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.1056646906
Directory /workspace/22.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.3600947363
Short name T350
Test name
Test status
Simulation time 42993960 ps
CPU time 0.97 seconds
Started Jun 10 07:45:47 PM PDT 24
Finished Jun 10 07:45:51 PM PDT 24
Peak memory 199928 kb
Host smart-07d73667-813d-4608-b5e9-be73e3a0e494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600947363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.3600947363
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.3083527642
Short name T741
Test name
Test status
Simulation time 47475120 ps
CPU time 0.81 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:57 PM PDT 24
Peak memory 198700 kb
Host smart-8fd86659-4ebe-43bc-a878-34173f038422
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083527642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.3083527642
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.4235309307
Short name T819
Test name
Test status
Simulation time 41301244 ps
CPU time 0.59 seconds
Started Jun 10 07:45:49 PM PDT 24
Finished Jun 10 07:45:53 PM PDT 24
Peak memory 196848 kb
Host smart-877a3db0-e68c-4f3a-880c-fe434a7838be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235309307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.4235309307
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.1624854665
Short name T684
Test name
Test status
Simulation time 3008573295 ps
CPU time 0.93 seconds
Started Jun 10 07:45:46 PM PDT 24
Finished Jun 10 07:45:51 PM PDT 24
Peak memory 197668 kb
Host smart-5ff71722-47bf-4ef4-862e-fd559f5969c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624854665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.1624854665
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.379694319
Short name T478
Test name
Test status
Simulation time 66356178 ps
CPU time 0.61 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:56 PM PDT 24
Peak memory 197392 kb
Host smart-85f3e060-df1e-4861-8587-1cbcf24371a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379694319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.379694319
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.688330927
Short name T199
Test name
Test status
Simulation time 62378824 ps
CPU time 0.65 seconds
Started Jun 10 07:45:55 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 197892 kb
Host smart-589c3172-154c-4dc9-959e-5fc5960100cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688330927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.688330927
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.3387499794
Short name T202
Test name
Test status
Simulation time 50046661 ps
CPU time 0.75 seconds
Started Jun 10 07:46:01 PM PDT 24
Finished Jun 10 07:46:03 PM PDT 24
Peak memory 200936 kb
Host smart-37d90cbc-1aa5-4ee6-ba96-d9346b8ad0ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387499794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.3387499794
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.1875793144
Short name T81
Test name
Test status
Simulation time 175156924 ps
CPU time 0.81 seconds
Started Jun 10 07:45:49 PM PDT 24
Finished Jun 10 07:45:53 PM PDT 24
Peak memory 198092 kb
Host smart-7234a238-ceb2-4d05-939f-14bf36be76c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875793144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_w
akeup_race.1875793144
Directory /workspace/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.989541235
Short name T898
Test name
Test status
Simulation time 36330872 ps
CPU time 0.75 seconds
Started Jun 10 07:45:51 PM PDT 24
Finished Jun 10 07:45:55 PM PDT 24
Peak memory 198708 kb
Host smart-bb38d477-02f7-4f11-b553-c11d70b48d06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989541235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.989541235
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.3348382150
Short name T220
Test name
Test status
Simulation time 152615023 ps
CPU time 0.83 seconds
Started Jun 10 07:45:55 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 208976 kb
Host smart-0fcd3dec-8352-4411-8f49-25093dbcccf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348382150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.3348382150
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.3118124298
Short name T934
Test name
Test status
Simulation time 71509288 ps
CPU time 0.7 seconds
Started Jun 10 07:45:52 PM PDT 24
Finished Jun 10 07:45:56 PM PDT 24
Peak memory 198684 kb
Host smart-8323b266-03cb-49aa-8a99-77d0a7c42354
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118124298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_
cm_ctrl_config_regwen.3118124298
Directory /workspace/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.991270699
Short name T957
Test name
Test status
Simulation time 979945366 ps
CPU time 2.58 seconds
Started Jun 10 07:45:55 PM PDT 24
Finished Jun 10 07:46:00 PM PDT 24
Peak memory 200556 kb
Host smart-4c9cbb70-af71-4043-9e21-b7eb968d041a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991270699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.991270699
Directory /workspace/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3935392827
Short name T626
Test name
Test status
Simulation time 830949393 ps
CPU time 2.6 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 200572 kb
Host smart-f7b7d26f-02f8-4c0b-858d-ddbcba1b3d31
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935392827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3935392827
Directory /workspace/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.2969718186
Short name T141
Test name
Test status
Simulation time 316811778 ps
CPU time 0.87 seconds
Started Jun 10 07:45:46 PM PDT 24
Finished Jun 10 07:45:50 PM PDT 24
Peak memory 198740 kb
Host smart-6fb7a6b6-1910-4221-a5db-7e0fe09c91bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969718186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2969718186
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.1840212866
Short name T857
Test name
Test status
Simulation time 113284865 ps
CPU time 0.61 seconds
Started Jun 10 07:45:51 PM PDT 24
Finished Jun 10 07:45:55 PM PDT 24
Peak memory 198136 kb
Host smart-efea38f0-06e7-4791-91b6-0846b8009d0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840212866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.1840212866
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all.655888689
Short name T589
Test name
Test status
Simulation time 1365457773 ps
CPU time 2.15 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:58 PM PDT 24
Peak memory 200640 kb
Host smart-68aa3c7c-4a60-46e4-9387-c46a75c2bcf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655888689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.655888689
Directory /workspace/23.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all_with_rand_reset.2530153582
Short name T531
Test name
Test status
Simulation time 8166847076 ps
CPU time 11.44 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:46:08 PM PDT 24
Peak memory 200752 kb
Host smart-8ede9d4b-fc8f-4fe3-a08b-4403e2638b08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530153582 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all_with_rand_reset.2530153582
Directory /workspace/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.4127479836
Short name T658
Test name
Test status
Simulation time 207090616 ps
CPU time 0.81 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:57 PM PDT 24
Peak memory 198152 kb
Host smart-2d9b2744-2896-45b4-a92c-a86428df5c68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127479836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.4127479836
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup_reset.1818127704
Short name T338
Test name
Test status
Simulation time 230516129 ps
CPU time 0.86 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:57 PM PDT 24
Peak memory 199692 kb
Host smart-40ae0413-2c75-4a0a-86e8-cbe9867468e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818127704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.1818127704
Directory /workspace/23.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.3017286956
Short name T859
Test name
Test status
Simulation time 18381704 ps
CPU time 0.71 seconds
Started Jun 10 07:45:49 PM PDT 24
Finished Jun 10 07:45:53 PM PDT 24
Peak memory 198684 kb
Host smart-886d42b8-2cc8-490d-9803-255ccf802780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017286956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.3017286956
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.3074133012
Short name T174
Test name
Test status
Simulation time 114468239 ps
CPU time 0.68 seconds
Started Jun 10 07:45:51 PM PDT 24
Finished Jun 10 07:45:55 PM PDT 24
Peak memory 198668 kb
Host smart-78fb9ce6-3960-43d1-8781-bb5e288102e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074133012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.3074133012
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3728403506
Short name T460
Test name
Test status
Simulation time 33568683 ps
CPU time 0.66 seconds
Started Jun 10 07:46:00 PM PDT 24
Finished Jun 10 07:46:02 PM PDT 24
Peak memory 196868 kb
Host smart-6eaa469a-f550-4302-bb86-3a4f31c57586
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728403506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.3728403506
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.1265897149
Short name T576
Test name
Test status
Simulation time 160769565 ps
CPU time 0.99 seconds
Started Jun 10 07:46:01 PM PDT 24
Finished Jun 10 07:46:03 PM PDT 24
Peak memory 197740 kb
Host smart-428ccbe2-6332-4ee8-b6db-b3d9183e76c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265897149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.1265897149
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.3015577576
Short name T612
Test name
Test status
Simulation time 68315637 ps
CPU time 0.63 seconds
Started Jun 10 07:46:01 PM PDT 24
Finished Jun 10 07:46:03 PM PDT 24
Peak memory 197760 kb
Host smart-15ad2569-da9e-4aa1-8720-498ccf4b3a8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015577576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.3015577576
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.3831840297
Short name T565
Test name
Test status
Simulation time 47934967 ps
CPU time 0.61 seconds
Started Jun 10 07:45:56 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 197624 kb
Host smart-6fb1d314-ea72-40a5-86f2-a0bfe6d9171b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831840297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.3831840297
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.1115206232
Short name T389
Test name
Test status
Simulation time 64024879 ps
CPU time 0.68 seconds
Started Jun 10 07:46:00 PM PDT 24
Finished Jun 10 07:46:02 PM PDT 24
Peak memory 200884 kb
Host smart-05a4b230-3460-4aa2-8de0-610f049fc519
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115206232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.1115206232
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_wakeup_race.3404690503
Short name T753
Test name
Test status
Simulation time 165229016 ps
CPU time 0.89 seconds
Started Jun 10 07:45:55 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 198688 kb
Host smart-408391e6-8818-4476-b34b-284653b86ec5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404690503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_w
akeup_race.3404690503
Directory /workspace/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.3321676557
Short name T744
Test name
Test status
Simulation time 80799459 ps
CPU time 0.69 seconds
Started Jun 10 07:45:54 PM PDT 24
Finished Jun 10 07:45:58 PM PDT 24
Peak memory 198052 kb
Host smart-977dad45-85a1-484f-97aa-637fa6ea8c85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321676557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.3321676557
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.3040270117
Short name T488
Test name
Test status
Simulation time 126265931 ps
CPU time 0.88 seconds
Started Jun 10 07:45:50 PM PDT 24
Finished Jun 10 07:45:54 PM PDT 24
Peak memory 208968 kb
Host smart-25343058-be77-41ad-a946-b57462b54c4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040270117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.3040270117
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1273391985
Short name T582
Test name
Test status
Simulation time 334658479 ps
CPU time 1.01 seconds
Started Jun 10 07:45:50 PM PDT 24
Finished Jun 10 07:45:54 PM PDT 24
Peak memory 199596 kb
Host smart-67266d1c-32f0-4d58-8159-98c4f22391b6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273391985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_
cm_ctrl_config_regwen.1273391985
Directory /workspace/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2762813599
Short name T465
Test name
Test status
Simulation time 778890597 ps
CPU time 3.09 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 200532 kb
Host smart-d66956f0-9435-46ea-a273-c6bbe0b7420a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762813599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2762813599
Directory /workspace/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1611593512
Short name T365
Test name
Test status
Simulation time 888101866 ps
CPU time 3.42 seconds
Started Jun 10 07:45:47 PM PDT 24
Finished Jun 10 07:45:54 PM PDT 24
Peak memory 200596 kb
Host smart-d1971a32-1c54-401f-b448-7c6c4ddf502d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611593512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1611593512
Directory /workspace/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.1887536019
Short name T812
Test name
Test status
Simulation time 167161115 ps
CPU time 0.86 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:57 PM PDT 24
Peak memory 198928 kb
Host smart-48f9da18-bf64-40e1-a99d-2cbd56fe70e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887536019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1887536019
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.2290973463
Short name T371
Test name
Test status
Simulation time 57533208 ps
CPU time 0.68 seconds
Started Jun 10 07:45:49 PM PDT 24
Finished Jun 10 07:45:53 PM PDT 24
Peak memory 198964 kb
Host smart-89fab4e9-3d3a-4ac0-9fec-82de95a78067
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290973463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2290973463
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all.1333435923
Short name T842
Test name
Test status
Simulation time 697437462 ps
CPU time 2.52 seconds
Started Jun 10 07:45:54 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 200600 kb
Host smart-416191d1-21e3-4482-a044-5c6a2c55d4ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333435923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.1333435923
Directory /workspace/24.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all_with_rand_reset.1297513554
Short name T149
Test name
Test status
Simulation time 4149993210 ps
CPU time 8.13 seconds
Started Jun 10 07:45:57 PM PDT 24
Finished Jun 10 07:46:07 PM PDT 24
Peak memory 200772 kb
Host smart-eb079b79-2b27-4557-8dec-542c4f8468be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297513554 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all_with_rand_reset.1297513554
Directory /workspace/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup.903490877
Short name T366
Test name
Test status
Simulation time 272013201 ps
CPU time 0.91 seconds
Started Jun 10 07:46:02 PM PDT 24
Finished Jun 10 07:46:04 PM PDT 24
Peak memory 198004 kb
Host smart-caa5ff52-bf17-4ded-be65-56017b27a28c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903490877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.903490877
Directory /workspace/24.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup_reset.1172116102
Short name T945
Test name
Test status
Simulation time 86605164 ps
CPU time 0.86 seconds
Started Jun 10 07:45:55 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 198484 kb
Host smart-c0b01a36-c92f-4ce9-ba30-8f87bee91313
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172116102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.1172116102
Directory /workspace/24.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.1605369611
Short name T879
Test name
Test status
Simulation time 39285453 ps
CPU time 0.83 seconds
Started Jun 10 07:45:56 PM PDT 24
Finished Jun 10 07:46:00 PM PDT 24
Peak memory 199600 kb
Host smart-2812239b-9615-4372-9f5c-9f8a0d19c92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605369611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.1605369611
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.1543877224
Short name T757
Test name
Test status
Simulation time 29858897 ps
CPU time 0.62 seconds
Started Jun 10 07:45:58 PM PDT 24
Finished Jun 10 07:46:00 PM PDT 24
Peak memory 196852 kb
Host smart-1c1d1f18-987c-4f9f-b016-a873952c04ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543877224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.1543877224
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.601179877
Short name T675
Test name
Test status
Simulation time 658071492 ps
CPU time 0.97 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:09 PM PDT 24
Peak memory 197656 kb
Host smart-80278e25-a8e5-4f34-b3c1-4f1ad92e9f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601179877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.601179877
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.1898533453
Short name T551
Test name
Test status
Simulation time 40945588 ps
CPU time 0.67 seconds
Started Jun 10 07:46:08 PM PDT 24
Finished Jun 10 07:46:14 PM PDT 24
Peak memory 197644 kb
Host smart-13d59113-b642-4ff2-b851-bdb413f228ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898533453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.1898533453
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.1272308361
Short name T904
Test name
Test status
Simulation time 47684260 ps
CPU time 0.68 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:07 PM PDT 24
Peak memory 197628 kb
Host smart-1df87efc-6a95-49ca-90d6-e7ec309f7c4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272308361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.1272308361
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.3155774907
Short name T995
Test name
Test status
Simulation time 84358365 ps
CPU time 0.68 seconds
Started Jun 10 07:46:04 PM PDT 24
Finished Jun 10 07:46:06 PM PDT 24
Peak memory 200800 kb
Host smart-8147caf1-542a-44bc-b9bf-ce82e06b55ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155774907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.3155774907
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.526421375
Short name T623
Test name
Test status
Simulation time 193759265 ps
CPU time 0.8 seconds
Started Jun 10 07:45:52 PM PDT 24
Finished Jun 10 07:45:56 PM PDT 24
Peak memory 198080 kb
Host smart-0bfdcb99-3cf9-4c9c-97ce-a18b062acbf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526421375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wa
keup_race.526421375
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.467575902
Short name T42
Test name
Test status
Simulation time 85666551 ps
CPU time 0.82 seconds
Started Jun 10 07:45:56 PM PDT 24
Finished Jun 10 07:46:00 PM PDT 24
Peak memory 198716 kb
Host smart-2fe55810-ae0e-442c-b602-e1c59afb18d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467575902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.467575902
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.1553674661
Short name T865
Test name
Test status
Simulation time 93569801 ps
CPU time 0.93 seconds
Started Jun 10 07:46:06 PM PDT 24
Finished Jun 10 07:46:09 PM PDT 24
Peak memory 208980 kb
Host smart-5b97a3c8-e90e-48c5-a5e9-c4b23af536fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553674661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.1553674661
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.3139994854
Short name T402
Test name
Test status
Simulation time 124056525 ps
CPU time 0.91 seconds
Started Jun 10 07:46:04 PM PDT 24
Finished Jun 10 07:46:05 PM PDT 24
Peak memory 198312 kb
Host smart-17757f2b-ce8f-4bfd-a2ed-1c1caf5077e7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139994854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_
cm_ctrl_config_regwen.3139994854
Directory /workspace/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.134276251
Short name T105
Test name
Test status
Simulation time 1171196898 ps
CPU time 2.1 seconds
Started Jun 10 07:45:53 PM PDT 24
Finished Jun 10 07:45:58 PM PDT 24
Peak memory 200572 kb
Host smart-d9c189a5-8df3-4440-8f6e-a9ef169f32a9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134276251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.134276251
Directory /workspace/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.885009307
Short name T98
Test name
Test status
Simulation time 880975038 ps
CPU time 2.39 seconds
Started Jun 10 07:45:55 PM PDT 24
Finished Jun 10 07:46:00 PM PDT 24
Peak memory 200576 kb
Host smart-5205ab6c-4fa9-4348-a541-447ccf332303
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885009307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.885009307
Directory /workspace/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2460171857
Short name T403
Test name
Test status
Simulation time 125033351 ps
CPU time 0.91 seconds
Started Jun 10 07:45:54 PM PDT 24
Finished Jun 10 07:45:58 PM PDT 24
Peak memory 199028 kb
Host smart-69fb9219-dd12-47be-880f-973dc65372e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460171857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2460171857
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.1033561886
Short name T414
Test name
Test status
Simulation time 29201499 ps
CPU time 0.69 seconds
Started Jun 10 07:45:57 PM PDT 24
Finished Jun 10 07:46:00 PM PDT 24
Peak memory 198936 kb
Host smart-92eff7f0-1a1b-4bda-8f36-c5e7b464b5bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033561886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.1033561886
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all.1446428604
Short name T749
Test name
Test status
Simulation time 1258486103 ps
CPU time 2.01 seconds
Started Jun 10 07:46:08 PM PDT 24
Finished Jun 10 07:46:15 PM PDT 24
Peak memory 200644 kb
Host smart-c170a52b-09bd-4bb6-bd85-6bf2f42d4122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446428604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.1446428604
Directory /workspace/25.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all_with_rand_reset.2480517144
Short name T25
Test name
Test status
Simulation time 13612340031 ps
CPU time 18.62 seconds
Started Jun 10 07:46:09 PM PDT 24
Finished Jun 10 07:46:33 PM PDT 24
Peak memory 200884 kb
Host smart-706fb34f-5310-40ce-9db1-4aea99b90181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480517144 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all_with_rand_reset.2480517144
Directory /workspace/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup.3187299036
Short name T931
Test name
Test status
Simulation time 162637535 ps
CPU time 1.03 seconds
Started Jun 10 07:45:57 PM PDT 24
Finished Jun 10 07:46:01 PM PDT 24
Peak memory 199224 kb
Host smart-410ccffc-7e28-45e9-b22e-aad64506bb14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187299036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.3187299036
Directory /workspace/25.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup_reset.2165426630
Short name T588
Test name
Test status
Simulation time 132666027 ps
CPU time 0.94 seconds
Started Jun 10 07:45:55 PM PDT 24
Finished Jun 10 07:45:59 PM PDT 24
Peak memory 198576 kb
Host smart-79c0312d-f76b-43a4-bc30-73e2aa1aced1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165426630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.2165426630
Directory /workspace/25.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.898339616
Short name T528
Test name
Test status
Simulation time 30746534 ps
CPU time 0.7 seconds
Started Jun 10 07:46:13 PM PDT 24
Finished Jun 10 07:46:19 PM PDT 24
Peak memory 198616 kb
Host smart-ae65a555-a2b5-469f-bc18-60315d2454c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898339616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.898339616
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.902262757
Short name T36
Test name
Test status
Simulation time 56301454 ps
CPU time 0.78 seconds
Started Jun 10 07:46:12 PM PDT 24
Finished Jun 10 07:46:18 PM PDT 24
Peak memory 198008 kb
Host smart-e297da23-d9e4-4191-bf8b-186a0c27336e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902262757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disa
ble_rom_integrity_check.902262757
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.2620878725
Short name T11
Test name
Test status
Simulation time 43483369 ps
CPU time 0.62 seconds
Started Jun 10 07:46:09 PM PDT 24
Finished Jun 10 07:46:15 PM PDT 24
Peak memory 196820 kb
Host smart-bf008c10-1499-4357-9905-7de1188a8115
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620878725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.2620878725
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.994325757
Short name T328
Test name
Test status
Simulation time 161103097 ps
CPU time 1.06 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:12 PM PDT 24
Peak memory 197692 kb
Host smart-489b22bc-ce40-44d0-88fa-1cb9ab8eb432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994325757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.994325757
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.411722042
Short name T238
Test name
Test status
Simulation time 74796776 ps
CPU time 0.63 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:08 PM PDT 24
Peak memory 197536 kb
Host smart-22615958-6cf1-4996-9277-f4767ed80d94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411722042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.411722042
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.3088631440
Short name T309
Test name
Test status
Simulation time 56401132 ps
CPU time 0.61 seconds
Started Jun 10 07:46:12 PM PDT 24
Finished Jun 10 07:46:18 PM PDT 24
Peak memory 197960 kb
Host smart-9c0b2d69-0107-40a6-8ed7-882eec477b79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088631440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.3088631440
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.346828861
Short name T14
Test name
Test status
Simulation time 43730385 ps
CPU time 0.75 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:11 PM PDT 24
Peak memory 200844 kb
Host smart-17096c9b-d3a7-461b-877b-21fae0a1f829
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346828861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invali
d.346828861
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_wakeup_race.4291853802
Short name T725
Test name
Test status
Simulation time 56672815 ps
CPU time 0.82 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:12 PM PDT 24
Peak memory 197828 kb
Host smart-9d7300d4-623b-4a26-a6d4-d8d219a0532d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291853802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_w
akeup_race.4291853802
Directory /workspace/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.3652305289
Short name T197
Test name
Test status
Simulation time 33910480 ps
CPU time 0.66 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:08 PM PDT 24
Peak memory 197808 kb
Host smart-cd99a610-f873-4d44-b454-8d8f383f2f80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652305289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.3652305289
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.1542611553
Short name T285
Test name
Test status
Simulation time 104476043 ps
CPU time 0.92 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:13 PM PDT 24
Peak memory 209056 kb
Host smart-7d0172ca-597a-4524-b088-f21890943fc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542611553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.1542611553
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.1414844007
Short name T738
Test name
Test status
Simulation time 304252327 ps
CPU time 1.01 seconds
Started Jun 10 07:46:09 PM PDT 24
Finished Jun 10 07:46:15 PM PDT 24
Peak memory 199612 kb
Host smart-e3249e16-8949-4935-a704-3b1e35538f99
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414844007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_
cm_ctrl_config_regwen.1414844007
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2218602119
Short name T752
Test name
Test status
Simulation time 1523902705 ps
CPU time 2.23 seconds
Started Jun 10 07:46:08 PM PDT 24
Finished Jun 10 07:46:16 PM PDT 24
Peak memory 200576 kb
Host smart-c619fada-255e-4653-8850-5d798a87b90f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218602119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2218602119
Directory /workspace/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3352681951
Short name T47
Test name
Test status
Simulation time 979394733 ps
CPU time 2.09 seconds
Started Jun 10 07:46:03 PM PDT 24
Finished Jun 10 07:46:06 PM PDT 24
Peak memory 200640 kb
Host smart-34015366-8c11-4553-a821-337f68150637
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352681951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3352681951
Directory /workspace/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.1253290440
Short name T500
Test name
Test status
Simulation time 63092855 ps
CPU time 0.93 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:12 PM PDT 24
Peak memory 198600 kb
Host smart-956f690c-d93f-43fa-ac1c-980baf34549b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253290440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1253290440
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.1574175537
Short name T61
Test name
Test status
Simulation time 70183684 ps
CPU time 0.65 seconds
Started Jun 10 07:46:04 PM PDT 24
Finished Jun 10 07:46:06 PM PDT 24
Peak memory 198940 kb
Host smart-cd6fe9e4-02e5-4802-957f-911855d83a97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574175537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1574175537
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all.1860606398
Short name T673
Test name
Test status
Simulation time 1032743207 ps
CPU time 2.41 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:13 PM PDT 24
Peak memory 200704 kb
Host smart-fab16c88-44ef-44c1-8b93-264e8fa4d206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860606398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.1860606398
Directory /workspace/26.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all_with_rand_reset.4139635844
Short name T776
Test name
Test status
Simulation time 11261686115 ps
CPU time 15.59 seconds
Started Jun 10 07:46:08 PM PDT 24
Finished Jun 10 07:46:28 PM PDT 24
Peak memory 200784 kb
Host smart-f45372e8-ce3e-4b97-b3a2-f81c05304d48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139635844 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all_with_rand_reset.4139635844
Directory /workspace/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup.579530586
Short name T269
Test name
Test status
Simulation time 273195898 ps
CPU time 0.92 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:12 PM PDT 24
Peak memory 199300 kb
Host smart-98fb57f1-68d2-421a-b036-23bf3263e0be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579530586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.579530586
Directory /workspace/26.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup_reset.3259521975
Short name T161
Test name
Test status
Simulation time 239862529 ps
CPU time 1.23 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:12 PM PDT 24
Peak memory 199728 kb
Host smart-5bc698c7-eb64-4db9-9a73-2a6428db41bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259521975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.3259521975
Directory /workspace/26.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.2264101840
Short name T648
Test name
Test status
Simulation time 42808537 ps
CPU time 0.86 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:08 PM PDT 24
Peak memory 199588 kb
Host smart-654eb2d0-9f2d-40d4-a2cb-c9c19872890b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264101840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.2264101840
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.3513839050
Short name T566
Test name
Test status
Simulation time 72745485 ps
CPU time 0.74 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:08 PM PDT 24
Peak memory 198084 kb
Host smart-04ffba76-55a5-4057-8c4f-88316c63c810
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513839050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.3513839050
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.2213161276
Short name T294
Test name
Test status
Simulation time 30500142 ps
CPU time 0.64 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:08 PM PDT 24
Peak memory 196852 kb
Host smart-def20d93-0377-4926-9597-e2afbc8f0842
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213161276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.2213161276
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.4212069730
Short name T693
Test name
Test status
Simulation time 609096506 ps
CPU time 1.01 seconds
Started Jun 10 07:46:06 PM PDT 24
Finished Jun 10 07:46:10 PM PDT 24
Peak memory 197944 kb
Host smart-1c7b2e7c-df7d-4d00-ac8c-12be23571e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212069730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.4212069730
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.2683436947
Short name T820
Test name
Test status
Simulation time 71426306 ps
CPU time 0.63 seconds
Started Jun 10 07:46:06 PM PDT 24
Finished Jun 10 07:46:10 PM PDT 24
Peak memory 197588 kb
Host smart-84be2f66-16d8-4f57-afea-7b73963c4aeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683436947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.2683436947
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.1653896054
Short name T103
Test name
Test status
Simulation time 41888897 ps
CPU time 0.67 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:08 PM PDT 24
Peak memory 197652 kb
Host smart-788c655d-47fb-4b8f-bf26-13a4dd6bb41b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653896054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.1653896054
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.3419059128
Short name T240
Test name
Test status
Simulation time 43019967 ps
CPU time 0.77 seconds
Started Jun 10 07:46:06 PM PDT 24
Finished Jun 10 07:46:09 PM PDT 24
Peak memory 200816 kb
Host smart-a1f96be2-f704-4cb3-99e4-dbe78687cdab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419059128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.3419059128
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_wakeup_race.752466266
Short name T793
Test name
Test status
Simulation time 128831263 ps
CPU time 0.87 seconds
Started Jun 10 07:46:08 PM PDT 24
Finished Jun 10 07:46:13 PM PDT 24
Peak memory 198684 kb
Host smart-414c0878-8a9d-41dd-9497-300fba31bd52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752466266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wa
keup_race.752466266
Directory /workspace/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.4124077389
Short name T362
Test name
Test status
Simulation time 74311458 ps
CPU time 0.96 seconds
Started Jun 10 07:46:12 PM PDT 24
Finished Jun 10 07:46:18 PM PDT 24
Peak memory 199524 kb
Host smart-12ad7edd-2900-43af-bcd4-a7ce096770b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124077389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.4124077389
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.2558811438
Short name T707
Test name
Test status
Simulation time 172191178 ps
CPU time 0.79 seconds
Started Jun 10 07:46:04 PM PDT 24
Finished Jun 10 07:46:05 PM PDT 24
Peak memory 208960 kb
Host smart-9d445334-2c3c-4976-b062-074448ae97cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558811438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.2558811438
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.3938343409
Short name T266
Test name
Test status
Simulation time 61259422 ps
CPU time 0.63 seconds
Started Jun 10 07:46:06 PM PDT 24
Finished Jun 10 07:46:10 PM PDT 24
Peak memory 198680 kb
Host smart-f19d1223-eb19-464c-b884-c91f3f4bc04a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938343409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_
cm_ctrl_config_regwen.3938343409
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.531980227
Short name T227
Test name
Test status
Simulation time 864619936 ps
CPU time 3.06 seconds
Started Jun 10 07:46:04 PM PDT 24
Finished Jun 10 07:46:08 PM PDT 24
Peak memory 200536 kb
Host smart-9aff565c-028f-444a-aba1-e8d32e72124c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531980227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.531980227
Directory /workspace/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3824408678
Short name T145
Test name
Test status
Simulation time 894567190 ps
CPU time 3.2 seconds
Started Jun 10 07:46:01 PM PDT 24
Finished Jun 10 07:46:06 PM PDT 24
Peak memory 200640 kb
Host smart-69e994d7-8da7-4679-a494-3e3e37497e59
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824408678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3824408678
Directory /workspace/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.4239960139
Short name T250
Test name
Test status
Simulation time 114727378 ps
CPU time 0.82 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:08 PM PDT 24
Peak memory 198828 kb
Host smart-f63f5edd-51e6-4b83-b127-ec52f9583a1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239960139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4239960139
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.3894733456
Short name T932
Test name
Test status
Simulation time 50673545 ps
CPU time 0.66 seconds
Started Jun 10 07:46:04 PM PDT 24
Finished Jun 10 07:46:07 PM PDT 24
Peak memory 198892 kb
Host smart-f65faf23-6332-4b9b-a58d-7af75fbec01a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894733456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.3894733456
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all.2832468393
Short name T985
Test name
Test status
Simulation time 287585805 ps
CPU time 1.16 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:08 PM PDT 24
Peak memory 200504 kb
Host smart-888fd222-7207-4c1d-9a6e-53c4a2eef04e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832468393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.2832468393
Directory /workspace/27.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all_with_rand_reset.4063575391
Short name T959
Test name
Test status
Simulation time 8887941322 ps
CPU time 20.79 seconds
Started Jun 10 07:46:06 PM PDT 24
Finished Jun 10 07:46:31 PM PDT 24
Peak memory 200804 kb
Host smart-4206b840-d11e-4eb2-b637-ffe9b702016e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063575391 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all_with_rand_reset.4063575391
Directory /workspace/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup.932310600
Short name T449
Test name
Test status
Simulation time 318282584 ps
CPU time 1.1 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:07 PM PDT 24
Peak memory 199392 kb
Host smart-9c01fd47-7e44-4a57-a554-0ff5085d0ffc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932310600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.932310600
Directory /workspace/27.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup_reset.3610742991
Short name T392
Test name
Test status
Simulation time 299322405 ps
CPU time 0.93 seconds
Started Jun 10 07:46:15 PM PDT 24
Finished Jun 10 07:46:20 PM PDT 24
Peak memory 199692 kb
Host smart-07129400-4f1d-4697-a477-3756a393b7bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610742991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.3610742991
Directory /workspace/27.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.1899003634
Short name T16
Test name
Test status
Simulation time 111345740 ps
CPU time 0.85 seconds
Started Jun 10 07:46:10 PM PDT 24
Finished Jun 10 07:46:16 PM PDT 24
Peak memory 199716 kb
Host smart-a2a60829-74e6-40bb-8c7d-eb9876a60714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899003634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.1899003634
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.2526572012
Short name T399
Test name
Test status
Simulation time 56007772 ps
CPU time 0.78 seconds
Started Jun 10 07:46:06 PM PDT 24
Finished Jun 10 07:46:09 PM PDT 24
Peak memory 198640 kb
Host smart-079e29de-77ca-45d7-90f1-c52f3ce0da68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526572012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.2526572012
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.3245716879
Short name T862
Test name
Test status
Simulation time 31508430 ps
CPU time 0.6 seconds
Started Jun 10 07:46:12 PM PDT 24
Finished Jun 10 07:46:18 PM PDT 24
Peak memory 197572 kb
Host smart-cc3e2734-2af9-41e1-94be-7af7698f45da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245716879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.3245716879
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.1801433997
Short name T361
Test name
Test status
Simulation time 162657626 ps
CPU time 0.95 seconds
Started Jun 10 07:46:10 PM PDT 24
Finished Jun 10 07:46:16 PM PDT 24
Peak memory 197804 kb
Host smart-e5e2aa5d-b8c1-4455-8073-9e91c890689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801433997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1801433997
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.2363962925
Short name T443
Test name
Test status
Simulation time 86797647 ps
CPU time 0.65 seconds
Started Jun 10 07:46:08 PM PDT 24
Finished Jun 10 07:46:14 PM PDT 24
Peak memory 197640 kb
Host smart-f1d9b713-0717-4d14-87a5-3cab5a14c530
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363962925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.2363962925
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.3248276241
Short name T348
Test name
Test status
Simulation time 65953588 ps
CPU time 0.62 seconds
Started Jun 10 07:46:08 PM PDT 24
Finished Jun 10 07:46:14 PM PDT 24
Peak memory 197632 kb
Host smart-5cf619e2-22a9-4eb8-afa1-d124d6fd30bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248276241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3248276241
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.1925450564
Short name T296
Test name
Test status
Simulation time 44597418 ps
CPU time 0.69 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:08 PM PDT 24
Peak memory 200648 kb
Host smart-fe7641c2-7121-4827-a28a-7446b78ab0d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925450564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.1925450564
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.446818508
Short name T236
Test name
Test status
Simulation time 48675354 ps
CPU time 0.68 seconds
Started Jun 10 07:46:10 PM PDT 24
Finished Jun 10 07:46:16 PM PDT 24
Peak memory 198508 kb
Host smart-849d5f0a-b214-4c0d-85ef-80d5d31449e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446818508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wa
keup_race.446818508
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.3133334908
Short name T946
Test name
Test status
Simulation time 90101504 ps
CPU time 0.77 seconds
Started Jun 10 07:46:09 PM PDT 24
Finished Jun 10 07:46:15 PM PDT 24
Peak memory 197884 kb
Host smart-38e26282-7c42-4016-8566-aee8346d12d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133334908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.3133334908
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.3058491736
Short name T1
Test name
Test status
Simulation time 158425168 ps
CPU time 0.85 seconds
Started Jun 10 07:46:06 PM PDT 24
Finished Jun 10 07:46:10 PM PDT 24
Peak memory 208884 kb
Host smart-5de08f73-91f0-46f2-99ce-f01c53e8545b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058491736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.3058491736
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.2835018169
Short name T883
Test name
Test status
Simulation time 209352355 ps
CPU time 1.22 seconds
Started Jun 10 07:45:57 PM PDT 24
Finished Jun 10 07:46:01 PM PDT 24
Peak memory 199472 kb
Host smart-342e3b63-678d-412a-bc77-68a80c42d80e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835018169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_
cm_ctrl_config_regwen.2835018169
Directory /workspace/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2558350310
Short name T838
Test name
Test status
Simulation time 1953279552 ps
CPU time 1.78 seconds
Started Jun 10 07:46:10 PM PDT 24
Finished Jun 10 07:46:17 PM PDT 24
Peak memory 200636 kb
Host smart-75b18d08-5850-42d5-9530-b3cf97da5f8d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558350310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2558350310
Directory /workspace/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.4047046715
Short name T730
Test name
Test status
Simulation time 145405126 ps
CPU time 0.95 seconds
Started Jun 10 07:46:09 PM PDT 24
Finished Jun 10 07:46:16 PM PDT 24
Peak memory 198932 kb
Host smart-d7f0c42c-69af-407e-bf18-699d74f6f555
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047046715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4047046715
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.2630845706
Short name T475
Test name
Test status
Simulation time 39228402 ps
CPU time 0.66 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:11 PM PDT 24
Peak memory 198148 kb
Host smart-e1150228-5646-4e66-a0f2-d379daa71168
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630845706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.2630845706
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all.3651061764
Short name T845
Test name
Test status
Simulation time 990561212 ps
CPU time 3.4 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:16 PM PDT 24
Peak memory 200592 kb
Host smart-8596229c-62c9-4666-a953-6b63364f9a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651061764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.3651061764
Directory /workspace/28.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all_with_rand_reset.3779610256
Short name T53
Test name
Test status
Simulation time 10364245854 ps
CPU time 31.73 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 200820 kb
Host smart-4762674a-3310-4ed5-85cb-38e9ce680289
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779610256 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all_with_rand_reset.3779610256
Directory /workspace/28.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup.2048948043
Short name T962
Test name
Test status
Simulation time 252642335 ps
CPU time 0.77 seconds
Started Jun 10 07:46:08 PM PDT 24
Finished Jun 10 07:46:13 PM PDT 24
Peak memory 198016 kb
Host smart-3acdd790-e144-4b4f-89bd-54eb9adc23c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048948043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.2048948043
Directory /workspace/28.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup_reset.3644773964
Short name T210
Test name
Test status
Simulation time 213459697 ps
CPU time 1.14 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:08 PM PDT 24
Peak memory 199788 kb
Host smart-7f506d1f-6ea3-4a9d-921f-4cb922cf32a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644773964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.3644773964
Directory /workspace/28.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.2385708739
Short name T615
Test name
Test status
Simulation time 43386928 ps
CPU time 0.66 seconds
Started Jun 10 07:46:16 PM PDT 24
Finished Jun 10 07:46:21 PM PDT 24
Peak memory 198088 kb
Host smart-592ab57f-e1cf-472a-8640-56baca4887e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385708739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.2385708739
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.2663003802
Short name T425
Test name
Test status
Simulation time 70445676 ps
CPU time 0.86 seconds
Started Jun 10 07:46:23 PM PDT 24
Finished Jun 10 07:46:29 PM PDT 24
Peak memory 198616 kb
Host smart-9d0b0ae6-2245-4ff8-97c2-a2c136dc8475
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663003802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.2663003802
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.130039350
Short name T527
Test name
Test status
Simulation time 28958987 ps
CPU time 0.63 seconds
Started Jun 10 07:46:16 PM PDT 24
Finished Jun 10 07:46:21 PM PDT 24
Peak memory 195672 kb
Host smart-7b91ab6a-d932-4a4e-9503-3d19514a2786
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130039350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_
malfunc.130039350
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.2352049786
Short name T91
Test name
Test status
Simulation time 164822650 ps
CPU time 0.95 seconds
Started Jun 10 07:46:23 PM PDT 24
Finished Jun 10 07:46:30 PM PDT 24
Peak memory 197636 kb
Host smart-2784126c-eca3-4917-a7f1-e09f921ea6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352049786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.2352049786
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.3384080641
Short name T398
Test name
Test status
Simulation time 51327407 ps
CPU time 0.62 seconds
Started Jun 10 07:46:25 PM PDT 24
Finished Jun 10 07:46:33 PM PDT 24
Peak memory 197732 kb
Host smart-57d5cf4f-d49a-4411-ab7a-c63d9e6a6e9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384080641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.3384080641
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.702129840
Short name T575
Test name
Test status
Simulation time 51506311 ps
CPU time 0.61 seconds
Started Jun 10 07:46:21 PM PDT 24
Finished Jun 10 07:46:25 PM PDT 24
Peak memory 197660 kb
Host smart-d8098583-026b-4166-9705-f0a8b52ff90f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702129840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.702129840
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.199561160
Short name T992
Test name
Test status
Simulation time 42907713 ps
CPU time 0.74 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:34 PM PDT 24
Peak memory 200872 kb
Host smart-93ed33d0-f0ea-4693-ad04-cd7c670158bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199561160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invali
d.199561160
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.2335294833
Short name T833
Test name
Test status
Simulation time 62080888 ps
CPU time 0.73 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:13 PM PDT 24
Peak memory 197872 kb
Host smart-987845f8-8425-4007-bbf5-013c70a6b48b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335294833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_w
akeup_race.2335294833
Directory /workspace/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.4043295668
Short name T910
Test name
Test status
Simulation time 74625878 ps
CPU time 0.85 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:12 PM PDT 24
Peak memory 198620 kb
Host smart-d6644f34-80bd-48f0-b3a1-20f1f26a094a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043295668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.4043295668
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.1065034172
Short name T974
Test name
Test status
Simulation time 152177947 ps
CPU time 0.87 seconds
Started Jun 10 07:46:23 PM PDT 24
Finished Jun 10 07:46:29 PM PDT 24
Peak memory 208888 kb
Host smart-506abe08-1ea9-4f82-aa9b-d6a41983c350
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065034172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.1065034172
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.1819027551
Short name T530
Test name
Test status
Simulation time 40064467 ps
CPU time 0.68 seconds
Started Jun 10 07:46:06 PM PDT 24
Finished Jun 10 07:46:10 PM PDT 24
Peak memory 198084 kb
Host smart-027cc515-4f10-4113-aee9-27c490726273
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819027551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_
cm_ctrl_config_regwen.1819027551
Directory /workspace/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1082137102
Short name T175
Test name
Test status
Simulation time 741547757 ps
CPU time 3.05 seconds
Started Jun 10 07:46:13 PM PDT 24
Finished Jun 10 07:46:22 PM PDT 24
Peak memory 200524 kb
Host smart-94ebd2f3-5e03-4b63-b86c-d4f0f3d4eb21
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082137102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1082137102
Directory /workspace/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1770607835
Short name T641
Test name
Test status
Simulation time 866560001 ps
CPU time 3.35 seconds
Started Jun 10 07:46:05 PM PDT 24
Finished Jun 10 07:46:10 PM PDT 24
Peak memory 200652 kb
Host smart-f1c8db7b-9b32-4800-be08-b8bdd97e1b9c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770607835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1770607835
Directory /workspace/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1273388275
Short name T31
Test name
Test status
Simulation time 85871713 ps
CPU time 0.95 seconds
Started Jun 10 07:46:16 PM PDT 24
Finished Jun 10 07:46:22 PM PDT 24
Peak memory 197356 kb
Host smart-b3ac24d1-c65f-4ca3-bc37-c7ef3e0a18a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273388275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1273388275
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.1534093153
Short name T291
Test name
Test status
Simulation time 31507404 ps
CPU time 0.68 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:13 PM PDT 24
Peak memory 198892 kb
Host smart-6e9c23e5-06c2-4fee-91b0-aa5ddd131f16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534093153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1534093153
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all.311321465
Short name T652
Test name
Test status
Simulation time 61149267 ps
CPU time 0.68 seconds
Started Jun 10 07:46:22 PM PDT 24
Finished Jun 10 07:46:28 PM PDT 24
Peak memory 198416 kb
Host smart-a7ee9b64-59ed-4c21-aa10-a6718a3d260e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311321465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.311321465
Directory /workspace/29.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all_with_rand_reset.2603189241
Short name T410
Test name
Test status
Simulation time 7672711858 ps
CPU time 26.42 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:47:04 PM PDT 24
Peak memory 200880 kb
Host smart-0722b85a-0805-462d-b451-d17d6632a3ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603189241 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all_with_rand_reset.2603189241
Directory /workspace/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup.2094064309
Short name T651
Test name
Test status
Simulation time 115930709 ps
CPU time 0.7 seconds
Started Jun 10 07:46:07 PM PDT 24
Finished Jun 10 07:46:11 PM PDT 24
Peak memory 198672 kb
Host smart-c3ec16b0-f49b-4d67-a75b-018007f8771a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094064309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.2094064309
Directory /workspace/29.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup_reset.2829366111
Short name T699
Test name
Test status
Simulation time 103983983 ps
CPU time 0.89 seconds
Started Jun 10 07:46:06 PM PDT 24
Finished Jun 10 07:46:11 PM PDT 24
Peak memory 198832 kb
Host smart-784f0edf-3a77-43eb-8ba3-e827b8b8b384
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829366111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.2829366111
Directory /workspace/29.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.2704108691
Short name T700
Test name
Test status
Simulation time 25435334 ps
CPU time 0.62 seconds
Started Jun 10 07:44:46 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 198712 kb
Host smart-b8e36253-b03b-49ab-ba9e-a728070d7fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704108691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.2704108691
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.3625300067
Short name T580
Test name
Test status
Simulation time 51580065 ps
CPU time 0.78 seconds
Started Jun 10 07:44:46 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 198364 kb
Host smart-3fb0b7a1-34de-4e28-9442-4ce06599d683
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625300067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.3625300067
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2099594439
Short name T352
Test name
Test status
Simulation time 29488091 ps
CPU time 0.65 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 197568 kb
Host smart-2d40dc57-351b-4e88-9805-0f570dee6179
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099594439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.2099594439
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.1852709416
Short name T462
Test name
Test status
Simulation time 160820443 ps
CPU time 0.92 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 197592 kb
Host smart-9605ad4e-26c3-4b45-a0c1-a410e91ce0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852709416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.1852709416
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.907977293
Short name T609
Test name
Test status
Simulation time 56831409 ps
CPU time 0.62 seconds
Started Jun 10 07:44:44 PM PDT 24
Finished Jun 10 07:44:51 PM PDT 24
Peak memory 197600 kb
Host smart-831cbe5d-79c2-4036-bd5a-1ed97207b033
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907977293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.907977293
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.713274257
Short name T358
Test name
Test status
Simulation time 37491320 ps
CPU time 0.64 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 197572 kb
Host smart-b68ec635-bc98-4490-a0d9-e3cea47da9d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713274257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.713274257
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1357381765
Short name T728
Test name
Test status
Simulation time 44559365 ps
CPU time 0.73 seconds
Started Jun 10 07:44:48 PM PDT 24
Finished Jun 10 07:44:55 PM PDT 24
Peak memory 200788 kb
Host smart-e691651d-662b-465c-a0f1-c6623f790ffb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357381765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1357381765
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.1960814866
Short name T8
Test name
Test status
Simulation time 152019285 ps
CPU time 0.73 seconds
Started Jun 10 07:44:42 PM PDT 24
Finished Jun 10 07:44:49 PM PDT 24
Peak memory 197912 kb
Host smart-17e267c5-12ac-4144-9c1f-51dd7beb5af2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960814866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wa
keup_race.1960814866
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.672919786
Short name T401
Test name
Test status
Simulation time 40183565 ps
CPU time 0.73 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 198612 kb
Host smart-5d67133f-d948-424c-a2cd-9ce5873d9fba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672919786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.672919786
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.2225473328
Short name T933
Test name
Test status
Simulation time 153637637 ps
CPU time 0.84 seconds
Started Jun 10 07:44:47 PM PDT 24
Finished Jun 10 07:44:55 PM PDT 24
Peak memory 208908 kb
Host smart-f88e496d-91d8-4639-9099-a1684ef033f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225473328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.2225473328
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.141140132
Short name T21
Test name
Test status
Simulation time 372098951 ps
CPU time 1.47 seconds
Started Jun 10 07:44:48 PM PDT 24
Finished Jun 10 07:44:56 PM PDT 24
Peak memory 216360 kb
Host smart-e9629826-4bb8-40ee-bca6-2671795b8405
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141140132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.141140132
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.3285798751
Short name T769
Test name
Test status
Simulation time 358122473 ps
CPU time 1.01 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 200344 kb
Host smart-9c19cbf6-b9ea-48a9-8650-9458dcaea321
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285798751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_c
m_ctrl_config_regwen.3285798751
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3774981804
Short name T643
Test name
Test status
Simulation time 863455769 ps
CPU time 3.2 seconds
Started Jun 10 07:44:48 PM PDT 24
Finished Jun 10 07:44:58 PM PDT 24
Peak memory 200544 kb
Host smart-18a09d64-551d-405e-810b-cfe0eac677e1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774981804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3774981804
Directory /workspace/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1786998214
Short name T762
Test name
Test status
Simulation time 872607120 ps
CPU time 3.14 seconds
Started Jun 10 07:44:46 PM PDT 24
Finished Jun 10 07:44:54 PM PDT 24
Peak memory 200608 kb
Host smart-a82d4c5e-f02d-4819-ba9c-e7ca48b558c2
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786998214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1786998214
Directory /workspace/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2184920150
Short name T625
Test name
Test status
Simulation time 117228392 ps
CPU time 0.88 seconds
Started Jun 10 07:44:46 PM PDT 24
Finished Jun 10 07:44:54 PM PDT 24
Peak memory 198972 kb
Host smart-3c210ae3-6776-49d5-9663-3d3ef2252376
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184920150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2184920150
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.2499866600
Short name T142
Test name
Test status
Simulation time 43149881 ps
CPU time 0.66 seconds
Started Jun 10 07:44:42 PM PDT 24
Finished Jun 10 07:44:49 PM PDT 24
Peak memory 198048 kb
Host smart-7336e350-d5af-4764-9c96-71fe347875e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499866600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.2499866600
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all.1017597632
Short name T94
Test name
Test status
Simulation time 758349063 ps
CPU time 3.42 seconds
Started Jun 10 07:44:46 PM PDT 24
Finished Jun 10 07:44:56 PM PDT 24
Peak memory 200676 kb
Host smart-56b4f21e-420e-46b5-b362-7eadbbf046d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017597632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.1017597632
Directory /workspace/3.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3202212195
Short name T138
Test name
Test status
Simulation time 12718371214 ps
CPU time 26.87 seconds
Started Jun 10 07:44:47 PM PDT 24
Finished Jun 10 07:45:20 PM PDT 24
Peak memory 200804 kb
Host smart-07fd0237-32c8-4901-9133-47d482033a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202212195 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all_with_rand_reset.3202212195
Directory /workspace/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup.35544809
Short name T513
Test name
Test status
Simulation time 193145187 ps
CPU time 0.82 seconds
Started Jun 10 07:44:41 PM PDT 24
Finished Jun 10 07:44:48 PM PDT 24
Peak memory 198056 kb
Host smart-369b5fea-a92a-41e5-ab84-a19c5539ce43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35544809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.35544809
Directory /workspace/3.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup_reset.756924462
Short name T601
Test name
Test status
Simulation time 199843464 ps
CPU time 1.13 seconds
Started Jun 10 07:44:45 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 200612 kb
Host smart-2c83ff11-3fe6-4b11-be55-cb203b99062a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756924462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.756924462
Directory /workspace/3.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.796620829
Short name T111
Test name
Test status
Simulation time 36048580 ps
CPU time 0.84 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:30 PM PDT 24
Peak memory 199708 kb
Host smart-e7cd6150-1b80-4cb8-a6ba-f2d5682747e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796620829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.796620829
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.1338025366
Short name T909
Test name
Test status
Simulation time 67709940 ps
CPU time 0.74 seconds
Started Jun 10 07:46:25 PM PDT 24
Finished Jun 10 07:46:33 PM PDT 24
Peak memory 198696 kb
Host smart-62389fa6-e6c3-4f19-8d46-c72ab61a295f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338025366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.1338025366
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.1782172193
Short name T35
Test name
Test status
Simulation time 32570441 ps
CPU time 0.65 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:31 PM PDT 24
Peak memory 196796 kb
Host smart-7fccbdd9-b4d5-41bf-aa89-8548f31e3baa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782172193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.1782172193
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.560972454
Short name T486
Test name
Test status
Simulation time 1161759938 ps
CPU time 1 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:30 PM PDT 24
Peak memory 198060 kb
Host smart-de8094ac-ef42-416c-bf29-12a6a4f2da5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560972454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.560972454
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.4070395256
Short name T772
Test name
Test status
Simulation time 39042593 ps
CPU time 0.65 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:36 PM PDT 24
Peak memory 197656 kb
Host smart-dfce27fc-92ce-46e1-a6b9-7f707950728a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070395256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.4070395256
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.3859077506
Short name T515
Test name
Test status
Simulation time 79444099 ps
CPU time 0.59 seconds
Started Jun 10 07:46:20 PM PDT 24
Finished Jun 10 07:46:24 PM PDT 24
Peak memory 197728 kb
Host smart-31d34a20-b1ff-45e7-af2f-1288bbaad955
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859077506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.3859077506
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.2848452850
Short name T516
Test name
Test status
Simulation time 84434572 ps
CPU time 0.68 seconds
Started Jun 10 07:46:25 PM PDT 24
Finished Jun 10 07:46:31 PM PDT 24
Peak memory 200784 kb
Host smart-68af66bb-85b0-4b85-bb10-a80244e771a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848452850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.2848452850
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.2944918376
Short name T193
Test name
Test status
Simulation time 291361936 ps
CPU time 0.9 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 199308 kb
Host smart-f510b820-10e4-462a-a39a-6bc4088af63f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944918376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_w
akeup_race.2944918376
Directory /workspace/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.2899268377
Short name T292
Test name
Test status
Simulation time 223854706 ps
CPU time 0.74 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:37 PM PDT 24
Peak memory 198132 kb
Host smart-505141de-72ad-49b5-af48-b08d4394e6ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899268377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.2899268377
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.3555923043
Short name T270
Test name
Test status
Simulation time 105480279 ps
CPU time 0.88 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:36 PM PDT 24
Peak memory 208980 kb
Host smart-71b32890-1e83-4d13-b191-5bc7f1a3e572
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555923043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.3555923043
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.1643644088
Short name T942
Test name
Test status
Simulation time 170894356 ps
CPU time 0.79 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 198288 kb
Host smart-2d35a5fc-e473-4ea2-af69-0888f516a704
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643644088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_
cm_ctrl_config_regwen.1643644088
Directory /workspace/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2184110696
Short name T467
Test name
Test status
Simulation time 809051096 ps
CPU time 2.85 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:40 PM PDT 24
Peak memory 200476 kb
Host smart-0d127c59-c13e-4d84-b903-9e1ece9cd8c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184110696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2184110696
Directory /workspace/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4008823699
Short name T327
Test name
Test status
Simulation time 814419990 ps
CPU time 3.29 seconds
Started Jun 10 07:46:25 PM PDT 24
Finished Jun 10 07:46:37 PM PDT 24
Peak memory 200684 kb
Host smart-b1359e95-f57d-48c8-8c95-a6be4d8b824c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008823699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4008823699
Directory /workspace/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.2045035998
Short name T518
Test name
Test status
Simulation time 61866220 ps
CPU time 0.85 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:30 PM PDT 24
Peak memory 198848 kb
Host smart-b860a0ff-9b15-46eb-8266-567e10e270f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045035998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2045035998
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.36788588
Short name T381
Test name
Test status
Simulation time 29378855 ps
CPU time 0.68 seconds
Started Jun 10 07:46:23 PM PDT 24
Finished Jun 10 07:46:28 PM PDT 24
Peak memory 198860 kb
Host smart-1d058f28-827a-4001-a626-9e299d46df2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36788588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.36788588
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all.3053336743
Short name T542
Test name
Test status
Simulation time 2215580619 ps
CPU time 2.12 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:37 PM PDT 24
Peak memory 200656 kb
Host smart-9e90c55c-2216-4add-bed3-1dfb96e3d538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053336743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.3053336743
Directory /workspace/30.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all_with_rand_reset.437828923
Short name T83
Test name
Test status
Simulation time 14492644686 ps
CPU time 20.61 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 200840 kb
Host smart-9b0e2303-10d0-449d-a057-6d03a8080e98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437828923 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all_with_rand_reset.437828923
Directory /workspace/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup.754642638
Short name T632
Test name
Test status
Simulation time 49887225 ps
CPU time 0.72 seconds
Started Jun 10 07:46:23 PM PDT 24
Finished Jun 10 07:46:29 PM PDT 24
Peak memory 198060 kb
Host smart-c51d3096-59bf-42f7-a224-9e8a42624412
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754642638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.754642638
Directory /workspace/30.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.1186991255
Short name T937
Test name
Test status
Simulation time 406361004 ps
CPU time 1.11 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:36 PM PDT 24
Peak memory 200456 kb
Host smart-d2eaf663-8b3c-4bae-8411-80eec0f54ebd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186991255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.1186991255
Directory /workspace/30.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.2170711696
Short name T894
Test name
Test status
Simulation time 221485383 ps
CPU time 0.68 seconds
Started Jun 10 07:46:22 PM PDT 24
Finished Jun 10 07:46:27 PM PDT 24
Peak memory 198304 kb
Host smart-160fcf24-beac-47f3-9920-674b39daa4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170711696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.2170711696
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.523169040
Short name T786
Test name
Test status
Simulation time 64935735 ps
CPU time 0.74 seconds
Started Jun 10 07:46:23 PM PDT 24
Finished Jun 10 07:46:29 PM PDT 24
Peak memory 198284 kb
Host smart-d822956c-e7da-4f81-be55-9be15fecbbdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523169040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disa
ble_rom_integrity_check.523169040
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.4205789275
Short name T89
Test name
Test status
Simulation time 30377114 ps
CPU time 0.66 seconds
Started Jun 10 07:46:25 PM PDT 24
Finished Jun 10 07:46:32 PM PDT 24
Peak memory 197540 kb
Host smart-bdd751fd-0205-40c8-b46b-4fbd73339f59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205789275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.4205789275
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.4050158488
Short name T489
Test name
Test status
Simulation time 690843176 ps
CPU time 0.94 seconds
Started Jun 10 07:46:22 PM PDT 24
Finished Jun 10 07:46:26 PM PDT 24
Peak memory 197644 kb
Host smart-2dde1ba1-b59e-4e8a-a014-ecce3c947aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050158488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.4050158488
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.1963086514
Short name T252
Test name
Test status
Simulation time 34657713 ps
CPU time 0.64 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:31 PM PDT 24
Peak memory 197568 kb
Host smart-bd439109-639b-424e-90b7-cbdab685c354
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963086514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.1963086514
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.1993808976
Short name T431
Test name
Test status
Simulation time 69925445 ps
CPU time 0.64 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:35 PM PDT 24
Peak memory 197612 kb
Host smart-65245f42-c462-4744-953a-9a18531c9243
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993808976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.1993808976
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.3289127082
Short name T721
Test name
Test status
Simulation time 108182473 ps
CPU time 0.72 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:36 PM PDT 24
Peak memory 200884 kb
Host smart-13d71d3a-8702-417f-8296-68176aa02c37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289127082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.3289127082
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.2473663149
Short name T143
Test name
Test status
Simulation time 336266305 ps
CPU time 0.89 seconds
Started Jun 10 07:46:22 PM PDT 24
Finished Jun 10 07:46:28 PM PDT 24
Peak memory 199140 kb
Host smart-740e9c63-c9f5-4249-8367-28883840a414
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473663149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_w
akeup_race.2473663149
Directory /workspace/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.2445388422
Short name T529
Test name
Test status
Simulation time 20709818 ps
CPU time 0.66 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:34 PM PDT 24
Peak memory 198676 kb
Host smart-49d60e0d-b51d-42b1-890d-fc69fcddc5b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445388422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.2445388422
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.4005664056
Short name T244
Test name
Test status
Simulation time 121159253 ps
CPU time 0.89 seconds
Started Jun 10 07:46:25 PM PDT 24
Finished Jun 10 07:46:34 PM PDT 24
Peak memory 200712 kb
Host smart-b1d80afe-c43e-417e-8c4b-b548c0d82deb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005664056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.4005664056
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.3637345723
Short name T96
Test name
Test status
Simulation time 49110986 ps
CPU time 0.71 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:34 PM PDT 24
Peak memory 198152 kb
Host smart-1e572a50-28be-4598-bad9-38aac27ffd69
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637345723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_
cm_ctrl_config_regwen.3637345723
Directory /workspace/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3249317507
Short name T678
Test name
Test status
Simulation time 870814458 ps
CPU time 2.57 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:33 PM PDT 24
Peak memory 200624 kb
Host smart-7341a8f1-20f8-4827-90e5-5e1d0ec422f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249317507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3249317507
Directory /workspace/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.182824070
Short name T861
Test name
Test status
Simulation time 2097197745 ps
CPU time 1.98 seconds
Started Jun 10 07:46:28 PM PDT 24
Finished Jun 10 07:46:40 PM PDT 24
Peak memory 200328 kb
Host smart-51979611-7036-4951-a96f-750b1f9be41e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182824070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.182824070
Directory /workspace/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3610594096
Short name T618
Test name
Test status
Simulation time 161685319 ps
CPU time 0.86 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:35 PM PDT 24
Peak memory 198924 kb
Host smart-c2e105b1-e2f2-48b5-85bb-277cf597fa65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610594096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3610594096
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.380523325
Short name T685
Test name
Test status
Simulation time 62150124 ps
CPU time 0.64 seconds
Started Jun 10 07:46:21 PM PDT 24
Finished Jun 10 07:46:25 PM PDT 24
Peak memory 198116 kb
Host smart-98993b49-9cb3-4f8d-aa2b-da199c5dba24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380523325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.380523325
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all.3254633075
Short name T38
Test name
Test status
Simulation time 378004515 ps
CPU time 0.91 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:36 PM PDT 24
Peak memory 199440 kb
Host smart-316c85b2-6623-4c7b-878c-3c73d46e14b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254633075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.3254633075
Directory /workspace/31.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all_with_rand_reset.4291343728
Short name T74
Test name
Test status
Simulation time 4281066928 ps
CPU time 13.68 seconds
Started Jun 10 07:46:25 PM PDT 24
Finished Jun 10 07:46:46 PM PDT 24
Peak memory 200912 kb
Host smart-8a5b0c9a-ccf0-4e7a-a53a-db73b7430717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291343728 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all_with_rand_reset.4291343728
Directory /workspace/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup.2006493104
Short name T444
Test name
Test status
Simulation time 353609507 ps
CPU time 0.96 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:35 PM PDT 24
Peak memory 199160 kb
Host smart-cf02b3de-5069-40ec-9323-d30f0fdaaf1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006493104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.2006493104
Directory /workspace/31.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup_reset.2686736984
Short name T167
Test name
Test status
Simulation time 105903630 ps
CPU time 0.69 seconds
Started Jun 10 07:46:29 PM PDT 24
Finished Jun 10 07:46:40 PM PDT 24
Peak memory 198032 kb
Host smart-012c53a1-93b4-4a2d-960e-bcbc4352c143
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686736984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.2686736984
Directory /workspace/31.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.2905764058
Short name T383
Test name
Test status
Simulation time 34600378 ps
CPU time 0.76 seconds
Started Jun 10 07:46:22 PM PDT 24
Finished Jun 10 07:46:28 PM PDT 24
Peak memory 198500 kb
Host smart-4c0667fe-c02c-4a8e-9153-b6b7e35e850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905764058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.2905764058
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.48492409
Short name T185
Test name
Test status
Simulation time 65116732 ps
CPU time 0.69 seconds
Started Jun 10 07:46:22 PM PDT 24
Finished Jun 10 07:46:27 PM PDT 24
Peak memory 198712 kb
Host smart-d096f9de-4863-4c56-a5f3-56c6fa27bbc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48492409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disab
le_rom_integrity_check.48492409
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.2464349662
Short name T493
Test name
Test status
Simulation time 31326728 ps
CPU time 0.66 seconds
Started Jun 10 07:46:28 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 196868 kb
Host smart-555b58d1-70f6-479b-9756-79a43537e19c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464349662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.2464349662
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.3598037942
Short name T104
Test name
Test status
Simulation time 597754075 ps
CPU time 0.94 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:37 PM PDT 24
Peak memory 197936 kb
Host smart-7991ea25-ff5b-474d-b2b6-bbf0b613c9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598037942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.3598037942
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.1598228533
Short name T18
Test name
Test status
Simulation time 31650758 ps
CPU time 0.62 seconds
Started Jun 10 07:46:25 PM PDT 24
Finished Jun 10 07:46:33 PM PDT 24
Peak memory 197680 kb
Host smart-bdf1ee7f-45b3-4938-ae37-8de6e92cc1bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598228533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.1598228533
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.2098643216
Short name T561
Test name
Test status
Simulation time 83332130 ps
CPU time 0.6 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:35 PM PDT 24
Peak memory 197712 kb
Host smart-975a62ba-5420-458c-9491-7186e28734f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098643216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.2098643216
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.743575834
Short name T45
Test name
Test status
Simulation time 76917314 ps
CPU time 0.69 seconds
Started Jun 10 07:46:23 PM PDT 24
Finished Jun 10 07:46:30 PM PDT 24
Peak memory 200836 kb
Host smart-7284b276-3d37-4630-826b-7b1738d14ddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743575834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invali
d.743575834
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_wakeup_race.709334338
Short name T754
Test name
Test status
Simulation time 89246895 ps
CPU time 0.79 seconds
Started Jun 10 07:46:10 PM PDT 24
Finished Jun 10 07:46:16 PM PDT 24
Peak memory 198692 kb
Host smart-41a57dd8-6fdc-47c2-94e2-f6f6851c2abc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709334338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wa
keup_race.709334338
Directory /workspace/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.1153501714
Short name T162
Test name
Test status
Simulation time 56123822 ps
CPU time 0.63 seconds
Started Jun 10 07:46:23 PM PDT 24
Finished Jun 10 07:46:30 PM PDT 24
Peak memory 198164 kb
Host smart-5a84ecbc-6e3c-4908-80ab-56c814af1003
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153501714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.1153501714
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.2525226014
Short name T726
Test name
Test status
Simulation time 160036169 ps
CPU time 0.84 seconds
Started Jun 10 07:46:22 PM PDT 24
Finished Jun 10 07:46:27 PM PDT 24
Peak memory 209068 kb
Host smart-5dc89a88-56d3-4edd-8777-34b2373d43f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525226014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.2525226014
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.863891447
Short name T472
Test name
Test status
Simulation time 365630561 ps
CPU time 1.01 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:30 PM PDT 24
Peak memory 200364 kb
Host smart-2af2fcdd-777f-44dd-b6a7-c192817ba98e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863891447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_c
m_ctrl_config_regwen.863891447
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.44432559
Short name T559
Test name
Test status
Simulation time 922954398 ps
CPU time 2.45 seconds
Started Jun 10 07:46:28 PM PDT 24
Finished Jun 10 07:46:41 PM PDT 24
Peak memory 200628 kb
Host smart-619dfaa8-0174-4bc3-b8c5-344c0513b588
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44432559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +
UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.44432559
Directory /workspace/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1297147878
Short name T451
Test name
Test status
Simulation time 824095104 ps
CPU time 3.22 seconds
Started Jun 10 07:46:25 PM PDT 24
Finished Jun 10 07:46:34 PM PDT 24
Peak memory 200576 kb
Host smart-b07fa5f7-f64e-43b7-8fdd-3f2f69844f76
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297147878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1297147878
Directory /workspace/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.4011587387
Short name T801
Test name
Test status
Simulation time 143175534 ps
CPU time 0.82 seconds
Started Jun 10 07:46:25 PM PDT 24
Finished Jun 10 07:46:32 PM PDT 24
Peak memory 199200 kb
Host smart-6fe86ba5-036f-4e33-b718-d587527f26ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011587387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4011587387
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.495171332
Short name T492
Test name
Test status
Simulation time 34532807 ps
CPU time 0.66 seconds
Started Jun 10 07:46:28 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 198924 kb
Host smart-98db49bd-ba37-4409-8031-508494657f7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495171332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.495171332
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all.1940031159
Short name T107
Test name
Test status
Simulation time 776382193 ps
CPU time 3.61 seconds
Started Jun 10 07:46:25 PM PDT 24
Finished Jun 10 07:46:34 PM PDT 24
Peak memory 200644 kb
Host smart-2f94aaad-de15-469e-a782-396d0d963f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940031159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.1940031159
Directory /workspace/32.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all_with_rand_reset.4085060492
Short name T151
Test name
Test status
Simulation time 5453650630 ps
CPU time 6.88 seconds
Started Jun 10 07:46:29 PM PDT 24
Finished Jun 10 07:46:46 PM PDT 24
Peak memory 200824 kb
Host smart-41030b06-90b2-4f5d-8824-bf953e9078c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085060492 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all_with_rand_reset.4085060492
Directory /workspace/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.48638687
Short name T429
Test name
Test status
Simulation time 71032582 ps
CPU time 0.83 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 198672 kb
Host smart-af6ecbde-bb1e-4ebd-865e-1922a83a160f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48638687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.48638687
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup_reset.242714582
Short name T890
Test name
Test status
Simulation time 173292988 ps
CPU time 0.8 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:30 PM PDT 24
Peak memory 198840 kb
Host smart-1710ced6-0883-4f7e-957f-089ae680383b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242714582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.242714582
Directory /workspace/32.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.3444082459
Short name T435
Test name
Test status
Simulation time 47905337 ps
CPU time 0.89 seconds
Started Jun 10 07:46:29 PM PDT 24
Finished Jun 10 07:46:40 PM PDT 24
Peak memory 199528 kb
Host smart-0a13147f-97fc-4640-9d3b-d02baaa0c59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444082459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.3444082459
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.1333191900
Short name T90
Test name
Test status
Simulation time 132822776 ps
CPU time 0.69 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:37 PM PDT 24
Peak memory 198196 kb
Host smart-6cdbe153-76be-4685-9d94-d0754251ee91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333191900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.1333191900
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2924233958
Short name T450
Test name
Test status
Simulation time 29112617 ps
CPU time 0.65 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:34 PM PDT 24
Peak memory 196824 kb
Host smart-06f372e5-4cfa-4006-bcc8-c99679396062
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924233958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.2924233958
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.2389499269
Short name T611
Test name
Test status
Simulation time 164164234 ps
CPU time 1.02 seconds
Started Jun 10 07:46:28 PM PDT 24
Finished Jun 10 07:46:39 PM PDT 24
Peak memory 197600 kb
Host smart-c4580737-c876-4e43-8dfb-d68024c20a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389499269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2389499269
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.3473376477
Short name T306
Test name
Test status
Simulation time 89541153 ps
CPU time 0.6 seconds
Started Jun 10 07:46:28 PM PDT 24
Finished Jun 10 07:46:39 PM PDT 24
Peak memory 196908 kb
Host smart-70c5f4fd-4886-4dd3-932b-caaa19596f8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473376477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.3473376477
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.1381326645
Short name T886
Test name
Test status
Simulation time 140849372 ps
CPU time 0.66 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:31 PM PDT 24
Peak memory 197624 kb
Host smart-9fbc3083-a9cc-4e3c-a166-f737af8195c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381326645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.1381326645
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.1933114272
Short name T430
Test name
Test status
Simulation time 41796948 ps
CPU time 0.71 seconds
Started Jun 10 07:46:28 PM PDT 24
Finished Jun 10 07:46:39 PM PDT 24
Peak memory 200856 kb
Host smart-14a0beaa-81ed-43f1-b1b7-cd5d7ce1c2eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933114272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.1933114272
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.2831076466
Short name T887
Test name
Test status
Simulation time 425850652 ps
CPU time 1.06 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:31 PM PDT 24
Peak memory 199368 kb
Host smart-86d11553-544c-4f87-9e73-321f8b43bdaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831076466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_w
akeup_race.2831076466
Directory /workspace/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.369350447
Short name T421
Test name
Test status
Simulation time 38361806 ps
CPU time 0.72 seconds
Started Jun 10 07:46:25 PM PDT 24
Finished Jun 10 07:46:34 PM PDT 24
Peak memory 198600 kb
Host smart-3564c238-f7da-4883-a888-cdfe3ae7f963
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369350447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.369350447
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.4212693003
Short name T619
Test name
Test status
Simulation time 129486442 ps
CPU time 0.79 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:34 PM PDT 24
Peak memory 208984 kb
Host smart-6183ab7c-ffc5-41ca-8f6e-19f2b9bcab67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212693003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.4212693003
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.1336308259
Short name T265
Test name
Test status
Simulation time 219609875 ps
CPU time 1.22 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:35 PM PDT 24
Peak memory 200308 kb
Host smart-37bb9854-a381-4901-a177-f0b0e06e20dd
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336308259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_
cm_ctrl_config_regwen.1336308259
Directory /workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4228423103
Short name T949
Test name
Test status
Simulation time 996815612 ps
CPU time 2.89 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:32 PM PDT 24
Peak memory 200632 kb
Host smart-3cfeedfb-9a4c-494b-a4fb-acaea547d2c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228423103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4228423103
Directory /workspace/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.106425822
Short name T586
Test name
Test status
Simulation time 1400158757 ps
CPU time 2.06 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:37 PM PDT 24
Peak memory 200636 kb
Host smart-bd2e041e-b862-4712-8358-4e0ed0bd0845
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106425822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.106425822
Directory /workspace/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.3104798932
Short name T510
Test name
Test status
Simulation time 65313589 ps
CPU time 0.94 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:36 PM PDT 24
Peak memory 198860 kb
Host smart-b0fdc0b7-5377-4ccd-8a3d-5cd8b689ff6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104798932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3104798932
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.3972995011
Short name T211
Test name
Test status
Simulation time 30006170 ps
CPU time 0.7 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:35 PM PDT 24
Peak memory 198916 kb
Host smart-19f6be2c-37ce-4e02-84c3-94bbcf5bee89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972995011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.3972995011
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all.3549470859
Short name T445
Test name
Test status
Simulation time 997565246 ps
CPU time 1.93 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 200708 kb
Host smart-7a90b604-cc2a-4f7a-9e70-4fb464f91ba0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549470859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.3549470859
Directory /workspace/33.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all_with_rand_reset.1469863902
Short name T732
Test name
Test status
Simulation time 9158576500 ps
CPU time 18.4 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:56 PM PDT 24
Peak memory 200844 kb
Host smart-d9c21b00-40bb-4fce-b373-ede1d721f404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469863902 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all_with_rand_reset.1469863902
Directory /workspace/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup.3897649794
Short name T587
Test name
Test status
Simulation time 300607016 ps
CPU time 1.3 seconds
Started Jun 10 07:46:22 PM PDT 24
Finished Jun 10 07:46:28 PM PDT 24
Peak memory 199208 kb
Host smart-f042950d-7da7-4d39-bcc8-846de0202922
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897649794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.3897649794
Directory /workspace/33.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup_reset.629687993
Short name T390
Test name
Test status
Simulation time 347774235 ps
CPU time 1.25 seconds
Started Jun 10 07:46:29 PM PDT 24
Finished Jun 10 07:46:40 PM PDT 24
Peak memory 200636 kb
Host smart-f06d88c4-83e8-4327-92bf-26dceb770809
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629687993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.629687993
Directory /workspace/33.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.2075082494
Short name T692
Test name
Test status
Simulation time 70244381 ps
CPU time 0.86 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 199752 kb
Host smart-c54cff2d-3565-434c-8dcf-d72c23cf760c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075082494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.2075082494
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.561092113
Short name T427
Test name
Test status
Simulation time 176760312 ps
CPU time 0.66 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:37 PM PDT 24
Peak memory 198120 kb
Host smart-926fb2fb-83ad-4fba-be10-4731aa11f37d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561092113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disa
ble_rom_integrity_check.561092113
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1304428664
Short name T170
Test name
Test status
Simulation time 42062696 ps
CPU time 0.61 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:36 PM PDT 24
Peak memory 196844 kb
Host smart-6d719ef9-7ba5-435b-8751-ba64d92619c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304428664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.1304428664
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.2724346613
Short name T839
Test name
Test status
Simulation time 321257579 ps
CPU time 0.92 seconds
Started Jun 10 07:46:30 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 197956 kb
Host smart-295529da-9a8d-42cd-a6e1-c1fad9e26b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724346613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.2724346613
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.3634579514
Short name T466
Test name
Test status
Simulation time 79684759 ps
CPU time 0.62 seconds
Started Jun 10 07:46:30 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 197692 kb
Host smart-96830b8c-0357-4e0c-8b75-94a91399c9ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634579514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.3634579514
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.1558515052
Short name T939
Test name
Test status
Simulation time 51648391 ps
CPU time 0.63 seconds
Started Jun 10 07:46:30 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 197960 kb
Host smart-e6f65b53-9c22-4fb2-9fc6-51ca13190567
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558515052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.1558515052
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.3048325909
Short name T519
Test name
Test status
Simulation time 55674324 ps
CPU time 0.71 seconds
Started Jun 10 07:46:31 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 200416 kb
Host smart-707aa799-ec6a-457d-8045-5e15276a9f45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048325909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.3048325909
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.3003270796
Short name T525
Test name
Test status
Simulation time 250076347 ps
CPU time 0.96 seconds
Started Jun 10 07:46:31 PM PDT 24
Finished Jun 10 07:46:43 PM PDT 24
Peak memory 198708 kb
Host smart-868e66ff-505c-4bba-b97f-4161f40e0a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003270796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_w
akeup_race.3003270796
Directory /workspace/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.2350999033
Short name T194
Test name
Test status
Simulation time 81320176 ps
CPU time 0.74 seconds
Started Jun 10 07:46:28 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 198740 kb
Host smart-1efbf23e-d491-4b86-b6bf-08fb3354f2ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350999033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.2350999033
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.4282571339
Short name T168
Test name
Test status
Simulation time 103459634 ps
CPU time 0.96 seconds
Started Jun 10 07:46:31 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 208908 kb
Host smart-8f7b7b84-5375-4a97-9948-28654ec13e6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282571339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.4282571339
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.81626194
Short name T346
Test name
Test status
Simulation time 93415733 ps
CPU time 0.87 seconds
Started Jun 10 07:46:30 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 198272 kb
Host smart-73db7632-84cf-431c-9ff5-3c65490f2482
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81626194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm
_ctrl_config_regwen.81626194
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2496524321
Short name T393
Test name
Test status
Simulation time 1105596601 ps
CPU time 2.05 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 200644 kb
Host smart-e5eeddb5-97d1-46c7-89fb-d8f5695408da
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496524321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2496524321
Directory /workspace/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1945553273
Short name T965
Test name
Test status
Simulation time 1030672593 ps
CPU time 2.02 seconds
Started Jun 10 07:46:24 PM PDT 24
Finished Jun 10 07:46:32 PM PDT 24
Peak memory 200524 kb
Host smart-82c0f3fb-6bcb-4c16-99dc-b6c5451917a5
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945553273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1945553273
Directory /workspace/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2032977638
Short name T491
Test name
Test status
Simulation time 55058504 ps
CPU time 0.86 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 198960 kb
Host smart-f629933a-08bc-485c-9e17-72d143690c70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032977638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2032977638
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.1781365070
Short name T259
Test name
Test status
Simulation time 28926358 ps
CPU time 0.7 seconds
Started Jun 10 07:46:26 PM PDT 24
Finished Jun 10 07:46:35 PM PDT 24
Peak memory 198900 kb
Host smart-2daba6d6-8616-44db-9bf1-add93e57df33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781365070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.1781365070
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all.234495099
Short name T113
Test name
Test status
Simulation time 2039929179 ps
CPU time 7.08 seconds
Started Jun 10 07:46:28 PM PDT 24
Finished Jun 10 07:46:46 PM PDT 24
Peak memory 200592 kb
Host smart-71cc1e49-bfc3-4ee9-9681-3efcb06d394c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234495099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.234495099
Directory /workspace/34.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all_with_rand_reset.3714661444
Short name T422
Test name
Test status
Simulation time 8775887028 ps
CPU time 12.53 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:56 PM PDT 24
Peak memory 200836 kb
Host smart-ee362ead-472f-42dc-a2e8-19fc28dae9a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714661444 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all_with_rand_reset.3714661444
Directory /workspace/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup.2795257192
Short name T573
Test name
Test status
Simulation time 87758225 ps
CPU time 0.82 seconds
Started Jun 10 07:46:23 PM PDT 24
Finished Jun 10 07:46:29 PM PDT 24
Peak memory 197828 kb
Host smart-7c91814b-5026-43c1-baff-d8860e904093
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795257192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.2795257192
Directory /workspace/34.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup_reset.3968718629
Short name T289
Test name
Test status
Simulation time 184651910 ps
CPU time 1.16 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:37 PM PDT 24
Peak memory 199620 kb
Host smart-8a9f0dae-3502-4f82-b693-7c884dfb6109
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968718629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.3968718629
Directory /workspace/34.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.304791408
Short name T242
Test name
Test status
Simulation time 26676596 ps
CPU time 0.83 seconds
Started Jun 10 07:46:31 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 199688 kb
Host smart-3b889106-9ec5-40cb-82a4-cf9d86f51418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304791408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.304791408
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.522722754
Short name T605
Test name
Test status
Simulation time 116854992 ps
CPU time 0.7 seconds
Started Jun 10 07:46:34 PM PDT 24
Finished Jun 10 07:46:45 PM PDT 24
Peak memory 198180 kb
Host smart-7b92d0cd-f255-4dbc-8af1-43f8d035e2d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522722754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disa
ble_rom_integrity_check.522722754
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.2783641971
Short name T617
Test name
Test status
Simulation time 43145860 ps
CPU time 0.6 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 197420 kb
Host smart-4ce7ea11-7a19-4f8c-ac9f-6763da46d5b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783641971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.2783641971
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.1640806920
Short name T696
Test name
Test status
Simulation time 163833248 ps
CPU time 1.01 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:45 PM PDT 24
Peak memory 197728 kb
Host smart-334fe126-bf91-45ba-bd5b-48559f617c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640806920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.1640806920
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.915536259
Short name T811
Test name
Test status
Simulation time 47313443 ps
CPU time 0.67 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 197748 kb
Host smart-5dff14b0-be6a-4ef4-84ec-269263f9e9f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915536259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.915536259
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.984691020
Short name T351
Test name
Test status
Simulation time 81632162 ps
CPU time 0.61 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:45 PM PDT 24
Peak memory 197596 kb
Host smart-d93b24ba-7d2e-4665-b6e3-7b862b842989
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984691020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.984691020
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.2247006984
Short name T600
Test name
Test status
Simulation time 41878772 ps
CPU time 0.76 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 200812 kb
Host smart-a2419c1a-4596-48a0-aaab-27c399eab7eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247006984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.2247006984
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.2653886845
Short name T62
Test name
Test status
Simulation time 256935798 ps
CPU time 1.25 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 199412 kb
Host smart-193b8f8a-1692-4a88-9149-aa7b21d857ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653886845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_w
akeup_race.2653886845
Directory /workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.320913452
Short name T507
Test name
Test status
Simulation time 68358919 ps
CPU time 0.85 seconds
Started Jun 10 07:46:31 PM PDT 24
Finished Jun 10 07:46:43 PM PDT 24
Peak memory 198712 kb
Host smart-56035771-92a3-4075-81ce-1be7c79fea90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320913452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.320913452
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.1255778828
Short name T982
Test name
Test status
Simulation time 324820290 ps
CPU time 0.81 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 208984 kb
Host smart-adb9786f-f4e9-44e6-91dc-cc34165776fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255778828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.1255778828
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.1822169888
Short name T765
Test name
Test status
Simulation time 248438591 ps
CPU time 0.97 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:49 PM PDT 24
Peak memory 199584 kb
Host smart-1fc27da8-34f6-49cf-a4dd-5018f6126e48
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822169888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_
cm_ctrl_config_regwen.1822169888
Directory /workspace/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1654417202
Short name T321
Test name
Test status
Simulation time 982964155 ps
CPU time 2.09 seconds
Started Jun 10 07:46:32 PM PDT 24
Finished Jun 10 07:46:45 PM PDT 24
Peak memory 200708 kb
Host smart-dac368e6-d09e-41ea-aabf-5f26fdeb1f3d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654417202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1654417202
Directory /workspace/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1002422486
Short name T616
Test name
Test status
Simulation time 1008834843 ps
CPU time 1.98 seconds
Started Jun 10 07:46:30 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 200536 kb
Host smart-6619d968-f030-4289-85a0-189c6652d44b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002422486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1002422486
Directory /workspace/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2957137743
Short name T863
Test name
Test status
Simulation time 88755774 ps
CPU time 0.81 seconds
Started Jun 10 07:46:28 PM PDT 24
Finished Jun 10 07:46:39 PM PDT 24
Peak memory 198792 kb
Host smart-c0f65661-a9e4-42e7-9037-50bff21e3b88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957137743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2957137743
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.2882834246
Short name T204
Test name
Test status
Simulation time 66565188 ps
CPU time 0.63 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:48 PM PDT 24
Peak memory 198076 kb
Host smart-3f44e72f-3e32-4b16-a44a-bb94f913969b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882834246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2882834246
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all.2542776418
Short name T86
Test name
Test status
Simulation time 1898669000 ps
CPU time 3.24 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:47 PM PDT 24
Peak memory 200748 kb
Host smart-8c47e689-5dcf-4406-9721-674a6e638939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542776418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.2542776418
Directory /workspace/35.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all_with_rand_reset.3336661116
Short name T413
Test name
Test status
Simulation time 13011950367 ps
CPU time 19.87 seconds
Started Jun 10 07:46:30 PM PDT 24
Finished Jun 10 07:47:01 PM PDT 24
Peak memory 200856 kb
Host smart-7e2923fe-7cf9-47a8-b2df-e497b688dd1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336661116 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all_with_rand_reset.3336661116
Directory /workspace/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup.1453884374
Short name T298
Test name
Test status
Simulation time 70926903 ps
CPU time 0.63 seconds
Started Jun 10 07:46:31 PM PDT 24
Finished Jun 10 07:46:43 PM PDT 24
Peak memory 197780 kb
Host smart-d31f32e7-cc78-435c-b925-d562275db015
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453884374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.1453884374
Directory /workspace/35.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup_reset.569069739
Short name T733
Test name
Test status
Simulation time 187454662 ps
CPU time 0.68 seconds
Started Jun 10 07:46:30 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 198560 kb
Host smart-012d7bfc-d46d-4373-9d0e-2d6227409fea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569069739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.569069739
Directory /workspace/35.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.2393465508
Short name T428
Test name
Test status
Simulation time 23140408 ps
CPU time 0.65 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 198148 kb
Host smart-af6379ff-03ca-4dee-9923-cef000ded9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393465508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.2393465508
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.3075916324
Short name T337
Test name
Test status
Simulation time 97187533 ps
CPU time 0.68 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 198632 kb
Host smart-1c05d6d8-e977-4af7-86f2-c3d1732f7e72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075916324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.3075916324
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.589222995
Short name T574
Test name
Test status
Simulation time 30375255 ps
CPU time 0.62 seconds
Started Jun 10 07:46:32 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 197492 kb
Host smart-6fa467d0-b588-407f-b818-8c36ee01c28f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589222995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_
malfunc.589222995
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.2701261815
Short name T336
Test name
Test status
Simulation time 164983230 ps
CPU time 0.96 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 197932 kb
Host smart-658b034a-a445-4aa3-8aeb-bdb7abb55635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701261815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.2701261815
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.3952845035
Short name T681
Test name
Test status
Simulation time 34743800 ps
CPU time 0.63 seconds
Started Jun 10 07:46:32 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 197620 kb
Host smart-081b58c5-255f-4523-85c2-ab6b6cc431ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952845035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.3952845035
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.3320730546
Short name T411
Test name
Test status
Simulation time 22329476 ps
CPU time 0.59 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:46:50 PM PDT 24
Peak memory 197628 kb
Host smart-d179ab9a-710b-41e0-93ea-b433b9e5f774
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320730546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3320730546
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.1952160464
Short name T853
Test name
Test status
Simulation time 38766597 ps
CPU time 0.71 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 200836 kb
Host smart-7d162d1c-1102-4e97-8512-cf5ee5bebf18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952160464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.1952160464
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.554922946
Short name T602
Test name
Test status
Simulation time 82909449 ps
CPU time 0.68 seconds
Started Jun 10 07:46:32 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 198060 kb
Host smart-e0c2f71d-1ece-4a83-bf52-729af8a909e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554922946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_wa
keup_race.554922946
Directory /workspace/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.1885274716
Short name T286
Test name
Test status
Simulation time 57724488 ps
CPU time 0.65 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 198720 kb
Host smart-4a223115-1367-44c2-9615-2ee15baab2eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885274716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.1885274716
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.3429504711
Short name T766
Test name
Test status
Simulation time 166680424 ps
CPU time 0.78 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 208896 kb
Host smart-81d1806d-84d1-467c-ad16-3b8483e6619f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429504711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.3429504711
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.3595362707
Short name T881
Test name
Test status
Simulation time 98546607 ps
CPU time 0.7 seconds
Started Jun 10 07:46:36 PM PDT 24
Finished Jun 10 07:46:48 PM PDT 24
Peak memory 197688 kb
Host smart-659024eb-0a22-4139-9f19-cd5eea967b99
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595362707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_
cm_ctrl_config_regwen.3595362707
Directory /workspace/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4038980398
Short name T215
Test name
Test status
Simulation time 917748188 ps
CPU time 2.41 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:46 PM PDT 24
Peak memory 200712 kb
Host smart-4979d71e-df7a-47e0-9ed8-91c2b45e0df1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038980398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4038980398
Directory /workspace/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.631691277
Short name T610
Test name
Test status
Simulation time 870769355 ps
CPU time 3 seconds
Started Jun 10 07:46:30 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 200680 kb
Host smart-011dff4c-cecd-4cff-a70b-d42123ea3284
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631691277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.631691277
Directory /workspace/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1936849905
Short name T522
Test name
Test status
Simulation time 77877542 ps
CPU time 0.92 seconds
Started Jun 10 07:46:32 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 198768 kb
Host smart-9806c7bf-0afb-4bce-a976-548472698a6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936849905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1936849905
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.4070382940
Short name T263
Test name
Test status
Simulation time 29363234 ps
CPU time 0.63 seconds
Started Jun 10 07:46:36 PM PDT 24
Finished Jun 10 07:46:47 PM PDT 24
Peak memory 198928 kb
Host smart-5dd31b42-a60c-4a2f-8440-7d13250f8a9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070382940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.4070382940
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all.3365053719
Short name T880
Test name
Test status
Simulation time 1078054716 ps
CPU time 1.76 seconds
Started Jun 10 07:46:41 PM PDT 24
Finished Jun 10 07:46:55 PM PDT 24
Peak memory 200404 kb
Host smart-56c1f9d0-f90f-481a-8526-f40c4f27c245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365053719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.3365053719
Directory /workspace/36.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all_with_rand_reset.3660599450
Short name T834
Test name
Test status
Simulation time 9117980154 ps
CPU time 11.9 seconds
Started Jun 10 07:46:41 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 200868 kb
Host smart-e45011a2-be09-4f13-a792-77ea1c6ae023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660599450 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all_with_rand_reset.3660599450
Directory /workspace/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup.1896749367
Short name T416
Test name
Test status
Simulation time 357498638 ps
CPU time 1.03 seconds
Started Jun 10 07:46:31 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 199260 kb
Host smart-d4f693ab-dec0-4542-8c8c-8b66cc491f4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896749367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.1896749367
Directory /workspace/36.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup_reset.2677485914
Short name T95
Test name
Test status
Simulation time 77878758 ps
CPU time 0.62 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 197868 kb
Host smart-b8d3a75b-2df8-4e50-80f2-59792813d90d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677485914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.2677485914
Directory /workspace/36.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.3290790398
Short name T916
Test name
Test status
Simulation time 21417874 ps
CPU time 0.64 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:49 PM PDT 24
Peak memory 198144 kb
Host smart-0ed921ad-7903-4706-ac9c-a2698b233fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290790398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.3290790398
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.1023823750
Short name T232
Test name
Test status
Simulation time 87995363 ps
CPU time 0.69 seconds
Started Jun 10 07:46:36 PM PDT 24
Finished Jun 10 07:46:48 PM PDT 24
Peak memory 198684 kb
Host smart-562e731a-393c-45fa-b725-701bf3a2af30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023823750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.1023823750
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.2992124259
Short name T233
Test name
Test status
Simulation time 41773913 ps
CPU time 0.57 seconds
Started Jun 10 07:46:36 PM PDT 24
Finished Jun 10 07:46:47 PM PDT 24
Peak memory 197548 kb
Host smart-470f1303-6997-45ce-a16e-423b0a06e7ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992124259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.2992124259
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.1974404885
Short name T563
Test name
Test status
Simulation time 306789307 ps
CPU time 1.03 seconds
Started Jun 10 07:46:29 PM PDT 24
Finished Jun 10 07:46:41 PM PDT 24
Peak memory 197664 kb
Host smart-8bdab207-d97f-4d31-9d90-f2d2a1f09ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974404885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.1974404885
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.3768405448
Short name T433
Test name
Test status
Simulation time 69789322 ps
CPU time 0.55 seconds
Started Jun 10 07:46:35 PM PDT 24
Finished Jun 10 07:46:46 PM PDT 24
Peak memory 197692 kb
Host smart-411e38c0-0635-4f0d-a828-2104483348ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768405448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.3768405448
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.3483992522
Short name T454
Test name
Test status
Simulation time 51373931 ps
CPU time 0.58 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:49 PM PDT 24
Peak memory 197604 kb
Host smart-23fcc382-74e3-45b3-9856-b270bec6aed1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483992522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.3483992522
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.723560429
Short name T505
Test name
Test status
Simulation time 123802821 ps
CPU time 0.64 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:48 PM PDT 24
Peak memory 200904 kb
Host smart-e4f227c5-5119-43b3-abcf-9ef316371ba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723560429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invali
d.723560429
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_wakeup_race.1898103390
Short name T704
Test name
Test status
Simulation time 74619672 ps
CPU time 0.77 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:48 PM PDT 24
Peak memory 198044 kb
Host smart-cf60b790-59f6-4b9e-b369-659ddc39b76a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898103390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_w
akeup_race.1898103390
Directory /workspace/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.834457300
Short name T217
Test name
Test status
Simulation time 31630569 ps
CPU time 0.68 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 198020 kb
Host smart-fae3b4e8-eec5-4d7f-823a-91c276cae128
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834457300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.834457300
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.3234129709
Short name T750
Test name
Test status
Simulation time 98668220 ps
CPU time 0.9 seconds
Started Jun 10 07:46:30 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 208912 kb
Host smart-f84cb269-2a63-46c6-a00d-4af51848f306
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234129709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.3234129709
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.1534657493
Short name T831
Test name
Test status
Simulation time 88041837 ps
CPU time 0.7 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:49 PM PDT 24
Peak memory 198404 kb
Host smart-47fad5d4-391a-4d5b-8bd7-6f6dc1701b42
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534657493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_
cm_ctrl_config_regwen.1534657493
Directory /workspace/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1400012613
Short name T504
Test name
Test status
Simulation time 821875103 ps
CPU time 3.25 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 200636 kb
Host smart-cdc1846f-c333-49c0-9f37-af197ffdfd8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400012613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1400012613
Directory /workspace/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3741854118
Short name T803
Test name
Test status
Simulation time 1189520383 ps
CPU time 1.94 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:50 PM PDT 24
Peak memory 200544 kb
Host smart-369bc9bc-04c4-46b1-a9a2-cc0bf5cd8a2f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741854118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3741854118
Directory /workspace/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.140090101
Short name T832
Test name
Test status
Simulation time 108226378 ps
CPU time 0.89 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:49 PM PDT 24
Peak memory 198864 kb
Host smart-33bc9103-b2e3-4765-b98f-de226f1b382f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140090101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_
mubi.140090101
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.1478346451
Short name T983
Test name
Test status
Simulation time 34239572 ps
CPU time 0.68 seconds
Started Jun 10 07:46:36 PM PDT 24
Finished Jun 10 07:46:48 PM PDT 24
Peak memory 198384 kb
Host smart-859ea7d2-30f9-464d-8c4d-40005010e291
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478346451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.1478346451
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all.3238064965
Short name T388
Test name
Test status
Simulation time 3872104085 ps
CPU time 4.72 seconds
Started Jun 10 07:46:36 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 200712 kb
Host smart-c33922a5-4d04-4dbb-82b6-f7cdb42a6d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238064965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.3238064965
Directory /workspace/37.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all_with_rand_reset.4049162447
Short name T76
Test name
Test status
Simulation time 5623960563 ps
CPU time 18.43 seconds
Started Jun 10 07:46:28 PM PDT 24
Finished Jun 10 07:46:57 PM PDT 24
Peak memory 200832 kb
Host smart-8b6dd6a7-6473-4f79-942b-5e82a2ef48df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049162447 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all_with_rand_reset.4049162447
Directory /workspace/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup.2857890011
Short name T495
Test name
Test status
Simulation time 328663176 ps
CPU time 0.92 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 199192 kb
Host smart-172b238e-bd91-40ce-bef0-a06bf0726ccb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857890011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.2857890011
Directory /workspace/37.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup_reset.2462143188
Short name T925
Test name
Test status
Simulation time 63953716 ps
CPU time 0.71 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:45 PM PDT 24
Peak memory 199176 kb
Host smart-0241878d-863a-472b-800f-8f3e7b3d1b8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462143188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.2462143188
Directory /workspace/37.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.3599126175
Short name T901
Test name
Test status
Simulation time 60809400 ps
CPU time 0.65 seconds
Started Jun 10 07:46:30 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 198072 kb
Host smart-9c314c31-ed75-4c56-a1dc-77846aefd2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599126175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.3599126175
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.3513417485
Short name T540
Test name
Test status
Simulation time 56298620 ps
CPU time 0.79 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:49 PM PDT 24
Peak memory 198640 kb
Host smart-4c914990-d714-4db7-9d1f-b6eaeb08b599
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513417485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.3513417485
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.4033850312
Short name T345
Test name
Test status
Simulation time 38772792 ps
CPU time 0.56 seconds
Started Jun 10 07:46:29 PM PDT 24
Finished Jun 10 07:46:40 PM PDT 24
Peak memory 196868 kb
Host smart-d5b016b6-2cb0-4724-ad82-4c513ac5b096
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033850312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.4033850312
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.605201405
Short name T43
Test name
Test status
Simulation time 612702355 ps
CPU time 1 seconds
Started Jun 10 07:46:32 PM PDT 24
Finished Jun 10 07:46:44 PM PDT 24
Peak memory 197944 kb
Host smart-e41a7652-dca1-4df1-b74c-f57ad457cdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605201405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.605201405
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.4227446747
Short name T620
Test name
Test status
Simulation time 31764949 ps
CPU time 0.63 seconds
Started Jun 10 07:46:36 PM PDT 24
Finished Jun 10 07:46:48 PM PDT 24
Peak memory 196928 kb
Host smart-d14fe8ac-6831-4cea-b46e-47163efd1481
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227446747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.4227446747
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.765837286
Short name T760
Test name
Test status
Simulation time 46882735 ps
CPU time 0.58 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:49 PM PDT 24
Peak memory 197716 kb
Host smart-649c9e0a-5aaf-4c66-be6b-692ce0fdaaa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765837286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.765837286
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.454257998
Short name T424
Test name
Test status
Simulation time 39341057 ps
CPU time 0.71 seconds
Started Jun 10 07:46:41 PM PDT 24
Finished Jun 10 07:46:54 PM PDT 24
Peak memory 200716 kb
Host smart-e678491f-76ad-48f9-8ad6-2bdb483058b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454257998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invali
d.454257998
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.4222379658
Short name T980
Test name
Test status
Simulation time 214511818 ps
CPU time 0.95 seconds
Started Jun 10 07:46:30 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 199068 kb
Host smart-9917a15e-8074-4538-9d17-dadb24010036
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222379658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_w
akeup_race.4222379658
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.75424720
Short name T969
Test name
Test status
Simulation time 141997171 ps
CPU time 0.81 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:38 PM PDT 24
Peak memory 198708 kb
Host smart-342037eb-5c95-4bfc-b7de-b79c235073c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75424720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.75424720
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.840557587
Short name T683
Test name
Test status
Simulation time 121324124 ps
CPU time 0.9 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 208892 kb
Host smart-c5152053-d1cc-4fde-8989-afa74b475e34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840557587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.840557587
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.2596964928
Short name T463
Test name
Test status
Simulation time 94495686 ps
CPU time 0.72 seconds
Started Jun 10 07:46:33 PM PDT 24
Finished Jun 10 07:46:45 PM PDT 24
Peak memory 198344 kb
Host smart-b1fcdd7d-1da3-4d2f-8a8e-86fdc510c4f2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596964928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_
cm_ctrl_config_regwen.2596964928
Directory /workspace/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2381679810
Short name T373
Test name
Test status
Simulation time 847451517 ps
CPU time 2.94 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:54 PM PDT 24
Peak memory 200700 kb
Host smart-692c0ca5-4d79-4098-a5ea-ffc7401a9e48
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381679810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2381679810
Directory /workspace/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1933225481
Short name T814
Test name
Test status
Simulation time 948709643 ps
CPU time 2.21 seconds
Started Jun 10 07:46:29 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 200636 kb
Host smart-581cd140-c39f-4598-82a9-1329b8fab846
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933225481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1933225481
Directory /workspace/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.695401179
Short name T984
Test name
Test status
Simulation time 143729159 ps
CPU time 0.82 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:49 PM PDT 24
Peak memory 198816 kb
Host smart-76314369-f302-451e-9471-4e4720b991f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695401179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_
mubi.695401179
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.154906616
Short name T397
Test name
Test status
Simulation time 61846886 ps
CPU time 0.62 seconds
Started Jun 10 07:46:36 PM PDT 24
Finished Jun 10 07:46:47 PM PDT 24
Peak memory 198888 kb
Host smart-27ea0975-c70f-4ea5-9fac-a25879606fe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154906616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.154906616
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all.3856650636
Short name T663
Test name
Test status
Simulation time 318704557 ps
CPU time 1.65 seconds
Started Jun 10 07:46:51 PM PDT 24
Finished Jun 10 07:47:01 PM PDT 24
Peak memory 200308 kb
Host smart-d104db42-c9a0-408d-88f3-478832ecf0ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856650636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.3856650636
Directory /workspace/38.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all_with_rand_reset.3600385763
Short name T65
Test name
Test status
Simulation time 2856958280 ps
CPU time 11.8 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:47:03 PM PDT 24
Peak memory 200860 kb
Host smart-88740ee1-87c5-4b8c-98da-77f15170e108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600385763 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all_with_rand_reset.3600385763
Directory /workspace/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup.572909669
Short name T735
Test name
Test status
Simulation time 27240737 ps
CPU time 0.64 seconds
Started Jun 10 07:46:41 PM PDT 24
Finished Jun 10 07:46:53 PM PDT 24
Peak memory 198760 kb
Host smart-db2b20cd-46e9-4e52-bd12-240d55ce6395
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572909669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.572909669
Directory /workspace/38.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup_reset.576693740
Short name T40
Test name
Test status
Simulation time 63647649 ps
CPU time 0.78 seconds
Started Jun 10 07:46:27 PM PDT 24
Finished Jun 10 07:46:36 PM PDT 24
Peak memory 198864 kb
Host smart-5b6eaacb-a775-4205-ba48-c5575b1eab9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576693740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.576693740
Directory /workspace/38.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.1923112133
Short name T745
Test name
Test status
Simulation time 86970771 ps
CPU time 0.71 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 198284 kb
Host smart-fa35d0f7-b62c-4fdf-a2c2-12903d778101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923112133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1923112133
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.3159174745
Short name T334
Test name
Test status
Simulation time 63527357 ps
CPU time 0.79 seconds
Started Jun 10 07:46:42 PM PDT 24
Finished Jun 10 07:46:55 PM PDT 24
Peak memory 198580 kb
Host smart-54d74dfa-7baf-4d5f-84c5-0cb204a48880
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159174745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.3159174745
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.321545957
Short name T423
Test name
Test status
Simulation time 38820960 ps
CPU time 0.6 seconds
Started Jun 10 07:46:42 PM PDT 24
Finished Jun 10 07:46:54 PM PDT 24
Peak memory 196732 kb
Host smart-8fdcf2b6-073b-4216-85cf-4c648cd91072
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321545957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_
malfunc.321545957
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.2814669668
Short name T382
Test name
Test status
Simulation time 584889919 ps
CPU time 1.01 seconds
Started Jun 10 07:46:42 PM PDT 24
Finished Jun 10 07:46:55 PM PDT 24
Peak memory 197956 kb
Host smart-7b7d4f54-473f-4e79-b36d-0286467be0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814669668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.2814669668
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.1498859869
Short name T621
Test name
Test status
Simulation time 59972941 ps
CPU time 0.66 seconds
Started Jun 10 07:46:45 PM PDT 24
Finished Jun 10 07:46:57 PM PDT 24
Peak memory 197576 kb
Host smart-3cb26f26-8a9b-4747-8944-6c34c55973b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498859869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.1498859869
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.1997764300
Short name T822
Test name
Test status
Simulation time 56042698 ps
CPU time 0.59 seconds
Started Jun 10 07:46:35 PM PDT 24
Finished Jun 10 07:46:46 PM PDT 24
Peak memory 197660 kb
Host smart-897d1e49-d12b-4dde-858b-ab567344b244
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997764300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1997764300
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.1967102321
Short name T646
Test name
Test status
Simulation time 59777059 ps
CPU time 0.71 seconds
Started Jun 10 07:46:42 PM PDT 24
Finished Jun 10 07:46:55 PM PDT 24
Peak memory 200804 kb
Host smart-15f76a7c-2643-4476-abd5-238402c208d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967102321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.1967102321
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.2479785054
Short name T207
Test name
Test status
Simulation time 424755957 ps
CPU time 0.78 seconds
Started Jun 10 07:46:41 PM PDT 24
Finished Jun 10 07:46:54 PM PDT 24
Peak memory 199176 kb
Host smart-4ad59412-78f1-4402-82bb-de6199e07f0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479785054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_w
akeup_race.2479785054
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.164305739
Short name T665
Test name
Test status
Simulation time 77663103 ps
CPU time 0.95 seconds
Started Jun 10 07:46:34 PM PDT 24
Finished Jun 10 07:46:46 PM PDT 24
Peak memory 199460 kb
Host smart-abf0b538-8b1e-44ea-a094-1b388046f87e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164305739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.164305739
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.3745991462
Short name T33
Test name
Test status
Simulation time 186568086 ps
CPU time 0.74 seconds
Started Jun 10 07:46:44 PM PDT 24
Finished Jun 10 07:46:56 PM PDT 24
Peak memory 208960 kb
Host smart-c437ff2d-84fc-455a-afea-db3c384cad40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745991462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.3745991462
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.1612078049
Short name T797
Test name
Test status
Simulation time 410178606 ps
CPU time 0.8 seconds
Started Jun 10 07:46:41 PM PDT 24
Finished Jun 10 07:46:54 PM PDT 24
Peak memory 199460 kb
Host smart-bacd14be-d4e3-49df-b21f-5bcdbfc07b2d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612078049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_
cm_ctrl_config_regwen.1612078049
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2976854859
Short name T331
Test name
Test status
Simulation time 780563554 ps
CPU time 3.17 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:53 PM PDT 24
Peak memory 200516 kb
Host smart-1280207f-d602-4770-8377-068529d5a2c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976854859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2976854859
Directory /workspace/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3104593696
Short name T264
Test name
Test status
Simulation time 1088077455 ps
CPU time 2.16 seconds
Started Jun 10 07:46:34 PM PDT 24
Finished Jun 10 07:46:47 PM PDT 24
Peak memory 200600 kb
Host smart-24ece3df-2084-4430-81e5-fd3de5a6d5bc
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104593696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3104593696
Directory /workspace/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.4167929740
Short name T590
Test name
Test status
Simulation time 70877791 ps
CPU time 0.96 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:53 PM PDT 24
Peak memory 199184 kb
Host smart-118dbd66-91a8-4e5a-8776-e176ac5509fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167929740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4167929740
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.13258735
Short name T756
Test name
Test status
Simulation time 156196357 ps
CPU time 0.62 seconds
Started Jun 10 07:46:42 PM PDT 24
Finished Jun 10 07:46:54 PM PDT 24
Peak memory 198128 kb
Host smart-a8aaaa3b-cc32-4357-8b21-dc84d94a0fea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13258735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.13258735
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all.3686569876
Short name T636
Test name
Test status
Simulation time 81568987 ps
CPU time 0.67 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 198456 kb
Host smart-2b4a3575-d90a-4ab6-9109-d938a365b1b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686569876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.3686569876
Directory /workspace/39.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all_with_rand_reset.4000017949
Short name T915
Test name
Test status
Simulation time 3733330231 ps
CPU time 15.56 seconds
Started Jun 10 07:46:35 PM PDT 24
Finished Jun 10 07:47:01 PM PDT 24
Peak memory 200852 kb
Host smart-953e75fd-9731-44ce-990d-288f00390032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000017949 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all_with_rand_reset.4000017949
Directory /workspace/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup.1575226746
Short name T359
Test name
Test status
Simulation time 110824162 ps
CPU time 0.88 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 197904 kb
Host smart-52b496be-06ca-4397-a4da-f924d7e578e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575226746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.1575226746
Directory /workspace/39.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup_reset.3113933157
Short name T79
Test name
Test status
Simulation time 296182876 ps
CPU time 1.32 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 200584 kb
Host smart-90b3dfe7-9599-4495-8a42-e672bf57c9e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113933157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.3113933157
Directory /workspace/39.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.560490301
Short name T511
Test name
Test status
Simulation time 62457779 ps
CPU time 0.7 seconds
Started Jun 10 07:44:50 PM PDT 24
Finished Jun 10 07:44:57 PM PDT 24
Peak memory 198688 kb
Host smart-1694c429-f84d-46db-a767-1b86c6eb2c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560490301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.560490301
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.248492329
Short name T774
Test name
Test status
Simulation time 125947852 ps
CPU time 0.68 seconds
Started Jun 10 07:44:47 PM PDT 24
Finished Jun 10 07:44:54 PM PDT 24
Peak memory 198660 kb
Host smart-fcaeb755-d380-4aae-85df-94a290329899
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248492329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disab
le_rom_integrity_check.248492329
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1319287154
Short name T287
Test name
Test status
Simulation time 30697926 ps
CPU time 0.61 seconds
Started Jun 10 07:44:50 PM PDT 24
Finished Jun 10 07:44:58 PM PDT 24
Peak memory 197468 kb
Host smart-4ee67ece-199d-40e2-8597-52f46670ad6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319287154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.1319287154
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.2453661075
Short name T297
Test name
Test status
Simulation time 565921022 ps
CPU time 0.96 seconds
Started Jun 10 07:44:50 PM PDT 24
Finished Jun 10 07:44:57 PM PDT 24
Peak memory 197372 kb
Host smart-62373108-f0f0-4928-bf1a-e931b45958dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453661075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.2453661075
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.4272019334
Short name T560
Test name
Test status
Simulation time 50223546 ps
CPU time 0.61 seconds
Started Jun 10 07:44:53 PM PDT 24
Finished Jun 10 07:45:00 PM PDT 24
Peak memory 197760 kb
Host smart-2721472f-d7ab-4ef3-86c0-ca0906efac26
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272019334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.4272019334
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.4290162209
Short name T355
Test name
Test status
Simulation time 66907733 ps
CPU time 0.58 seconds
Started Jun 10 07:44:50 PM PDT 24
Finished Jun 10 07:44:57 PM PDT 24
Peak memory 197536 kb
Host smart-19339c3f-4aa8-4a1e-a608-23f344707855
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290162209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.4290162209
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.3010565293
Short name T192
Test name
Test status
Simulation time 51629921 ps
CPU time 0.71 seconds
Started Jun 10 07:44:48 PM PDT 24
Finished Jun 10 07:44:56 PM PDT 24
Peak memory 200824 kb
Host smart-01e6dce6-0232-414c-a996-5751a736f46a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010565293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.3010565293
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.3819445375
Short name T981
Test name
Test status
Simulation time 63058760 ps
CPU time 0.73 seconds
Started Jun 10 07:44:48 PM PDT 24
Finished Jun 10 07:44:56 PM PDT 24
Peak memory 198128 kb
Host smart-b66257f3-8444-4b93-a8e6-afe62865d783
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819445375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa
keup_race.3819445375
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.133399469
Short name T899
Test name
Test status
Simulation time 56470984 ps
CPU time 0.84 seconds
Started Jun 10 07:44:49 PM PDT 24
Finished Jun 10 07:44:57 PM PDT 24
Peak memory 198644 kb
Host smart-e1a79018-1aac-4674-b989-d45454466678
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133399469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.133399469
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.1062793809
Short name T919
Test name
Test status
Simulation time 153222811 ps
CPU time 0.8 seconds
Started Jun 10 07:44:50 PM PDT 24
Finished Jun 10 07:44:58 PM PDT 24
Peak memory 208808 kb
Host smart-b8dea5f9-0e3d-4300-8fff-43a796ac6196
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062793809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1062793809
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.1119083087
Short name T29
Test name
Test status
Simulation time 1547435222 ps
CPU time 1.36 seconds
Started Jun 10 07:44:50 PM PDT 24
Finished Jun 10 07:44:58 PM PDT 24
Peak memory 217292 kb
Host smart-3148e8ae-402c-4b4c-9ec9-733f8ac88ab2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119083087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.1119083087
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.964611240
Short name T469
Test name
Test status
Simulation time 150254093 ps
CPU time 0.91 seconds
Started Jun 10 07:44:48 PM PDT 24
Finished Jun 10 07:44:56 PM PDT 24
Peak memory 199620 kb
Host smart-610d4d6a-e052-4ca0-b757-2adebdec6448
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964611240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm
_ctrl_config_regwen.964611240
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1487926435
Short name T456
Test name
Test status
Simulation time 838090148 ps
CPU time 2.99 seconds
Started Jun 10 07:44:48 PM PDT 24
Finished Jun 10 07:44:57 PM PDT 24
Peak memory 200520 kb
Host smart-8cf6b4cb-f699-4f69-8f6f-98032222bcdc
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487926435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1487926435
Directory /workspace/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1619547821
Short name T158
Test name
Test status
Simulation time 980289415 ps
CPU time 2.33 seconds
Started Jun 10 07:44:53 PM PDT 24
Finished Jun 10 07:45:01 PM PDT 24
Peak memory 200732 kb
Host smart-f4489ac8-52d3-457b-bdb2-e473820adcb3
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619547821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1619547821
Directory /workspace/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.2590491971
Short name T598
Test name
Test status
Simulation time 95626917 ps
CPU time 0.91 seconds
Started Jun 10 07:44:53 PM PDT 24
Finished Jun 10 07:45:00 PM PDT 24
Peak memory 199012 kb
Host smart-470287fc-7022-41e6-aaa2-f6b2472b0afe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590491971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2590491971
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.3040910065
Short name T635
Test name
Test status
Simulation time 29840774 ps
CPU time 0.68 seconds
Started Jun 10 07:44:46 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 198924 kb
Host smart-09876e16-64c2-49ec-b28e-90b7af1bbad1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040910065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.3040910065
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all.502713002
Short name T457
Test name
Test status
Simulation time 1038849336 ps
CPU time 3.87 seconds
Started Jun 10 07:44:49 PM PDT 24
Finished Jun 10 07:44:59 PM PDT 24
Peak memory 200664 kb
Host smart-ae290ec2-9bea-4518-9f66-9d35808af6c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502713002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.502713002
Directory /workspace/4.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all_with_rand_reset.3366525106
Short name T634
Test name
Test status
Simulation time 8069435343 ps
CPU time 16.07 seconds
Started Jun 10 07:44:50 PM PDT 24
Finished Jun 10 07:45:13 PM PDT 24
Peak memory 200828 kb
Host smart-9163dd40-e115-4f00-9605-40d688761008
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366525106 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all_with_rand_reset.3366525106
Directory /workspace/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup.695186982
Short name T394
Test name
Test status
Simulation time 299959173 ps
CPU time 1.27 seconds
Started Jun 10 07:44:49 PM PDT 24
Finished Jun 10 07:44:57 PM PDT 24
Peak memory 199080 kb
Host smart-6efc85f0-9e7b-4f48-a56d-b836a657bc60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695186982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.695186982
Directory /workspace/4.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.804807892
Short name T809
Test name
Test status
Simulation time 237055816 ps
CPU time 1.15 seconds
Started Jun 10 07:44:48 PM PDT 24
Finished Jun 10 07:44:56 PM PDT 24
Peak memory 199708 kb
Host smart-551d08fc-2b8b-4e57-8011-0ff11070e27a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804807892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.804807892
Directory /workspace/4.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.2626212712
Short name T554
Test name
Test status
Simulation time 31119217 ps
CPU time 1.01 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 200392 kb
Host smart-c5b25adb-a934-40ea-a2d2-975055479e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626212712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.2626212712
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.3854670615
Short name T184
Test name
Test status
Simulation time 71180837 ps
CPU time 0.74 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 198364 kb
Host smart-89078cef-0675-4fa6-82cb-b6b22fbea491
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854670615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.3854670615
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.3042253977
Short name T553
Test name
Test status
Simulation time 30771798 ps
CPU time 0.64 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:53 PM PDT 24
Peak memory 197544 kb
Host smart-58ffbeda-0dee-4c0b-afa5-e108f5a4cfbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042253977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.3042253977
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.3254544267
Short name T318
Test name
Test status
Simulation time 324207907 ps
CPU time 0.93 seconds
Started Jun 10 07:46:50 PM PDT 24
Finished Jun 10 07:47:00 PM PDT 24
Peak memory 197640 kb
Host smart-d53e4b0c-2acf-4697-ac80-da6a58416231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254544267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.3254544267
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.3535752290
Short name T272
Test name
Test status
Simulation time 71461873 ps
CPU time 0.59 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 197692 kb
Host smart-f8f3f457-e8b8-4349-a80b-b768672c3645
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535752290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.3535752290
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.3808846095
Short name T464
Test name
Test status
Simulation time 86690370 ps
CPU time 0.58 seconds
Started Jun 10 07:46:45 PM PDT 24
Finished Jun 10 07:46:57 PM PDT 24
Peak memory 197628 kb
Host smart-a2934af7-07fb-4b15-9cb5-537ca3eb79ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808846095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.3808846095
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.2994018001
Short name T205
Test name
Test status
Simulation time 66933767 ps
CPU time 0.71 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:53 PM PDT 24
Peak memory 200836 kb
Host smart-de071788-a969-4f4c-8606-ee6bdafeb22d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994018001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.2994018001
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.2832030060
Short name T235
Test name
Test status
Simulation time 148009499 ps
CPU time 0.61 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 197836 kb
Host smart-35ec0970-1386-45df-b159-e913e00f6f7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832030060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_w
akeup_race.2832030060
Directory /workspace/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.3715517068
Short name T718
Test name
Test status
Simulation time 69151387 ps
CPU time 0.7 seconds
Started Jun 10 07:46:54 PM PDT 24
Finished Jun 10 07:47:03 PM PDT 24
Peak memory 199028 kb
Host smart-031d3365-bd09-464d-83a6-16ebf090f072
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715517068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.3715517068
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.1385787755
Short name T897
Test name
Test status
Simulation time 106382480 ps
CPU time 0.89 seconds
Started Jun 10 07:46:41 PM PDT 24
Finished Jun 10 07:46:53 PM PDT 24
Peak memory 209000 kb
Host smart-4fd0ade6-25e4-4c9a-b8e0-28e681d4d636
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385787755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.1385787755
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.746553700
Short name T821
Test name
Test status
Simulation time 270130994 ps
CPU time 1.24 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 200460 kb
Host smart-28fb69ad-5306-4c4a-883e-932e54dc53f5
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746553700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_c
m_ctrl_config_regwen.746553700
Directory /workspace/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3284543861
Short name T539
Test name
Test status
Simulation time 1006930730 ps
CPU time 2.6 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:55 PM PDT 24
Peak memory 200456 kb
Host smart-fe100e8a-4619-4451-8834-ecc963fdcf96
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284543861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3284543861
Directory /workspace/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1183987905
Short name T442
Test name
Test status
Simulation time 1003149206 ps
CPU time 2.02 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 200536 kb
Host smart-8ede8fb7-caf0-47e1-951a-0f2e43d4e53d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183987905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1183987905
Directory /workspace/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.3100020593
Short name T828
Test name
Test status
Simulation time 223167131 ps
CPU time 0.85 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 199128 kb
Host smart-0516ed5c-71ab-458f-82e2-8b4d2eba3b06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100020593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3100020593
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.834879500
Short name T935
Test name
Test status
Simulation time 47235617 ps
CPU time 0.63 seconds
Started Jun 10 07:46:45 PM PDT 24
Finished Jun 10 07:46:57 PM PDT 24
Peak memory 198888 kb
Host smart-e0087e6c-564f-41cc-a708-b6faec4028f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834879500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.834879500
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all.234386195
Short name T956
Test name
Test status
Simulation time 1514869702 ps
CPU time 4.53 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:46:54 PM PDT 24
Peak memory 200748 kb
Host smart-4edd6632-f74e-4376-9c49-99fcad24e3b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234386195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.234386195
Directory /workspace/40.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup.1505755775
Short name T963
Test name
Test status
Simulation time 98268380 ps
CPU time 0.68 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 198632 kb
Host smart-a42054d5-e08a-4c27-b62a-93e4c234456d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505755775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.1505755775
Directory /workspace/40.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup_reset.2328760093
Short name T846
Test name
Test status
Simulation time 242947641 ps
CPU time 0.88 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:46:50 PM PDT 24
Peak memory 199564 kb
Host smart-6a660731-9f42-43bf-8aca-e8da2a5d55fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328760093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.2328760093
Directory /workspace/40.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.1214120646
Short name T672
Test name
Test status
Simulation time 39936174 ps
CPU time 0.88 seconds
Started Jun 10 07:46:36 PM PDT 24
Finished Jun 10 07:46:47 PM PDT 24
Peak memory 199824 kb
Host smart-7ae1d6d0-4a5b-498b-bb11-2eba7f971b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214120646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.1214120646
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3871621089
Short name T311
Test name
Test status
Simulation time 39074428 ps
CPU time 0.63 seconds
Started Jun 10 07:46:44 PM PDT 24
Finished Jun 10 07:46:56 PM PDT 24
Peak memory 196832 kb
Host smart-b24e85cf-3cfa-4a1b-8f46-1993e3c90eb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871621089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.3871621089
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.1260209058
Short name T169
Test name
Test status
Simulation time 602707000 ps
CPU time 0.97 seconds
Started Jun 10 07:46:43 PM PDT 24
Finished Jun 10 07:46:56 PM PDT 24
Peak memory 197656 kb
Host smart-b749353b-8f1d-45ab-b7cc-ae90bc3f5b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260209058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.1260209058
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.74223346
Short name T543
Test name
Test status
Simulation time 59460994 ps
CPU time 0.6 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:53 PM PDT 24
Peak memory 197664 kb
Host smart-210abd8d-6d6c-4bd5-9c0f-2c9f29f0d21e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74223346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.74223346
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.2311838843
Short name T44
Test name
Test status
Simulation time 86639444 ps
CPU time 0.6 seconds
Started Jun 10 07:46:37 PM PDT 24
Finished Jun 10 07:46:49 PM PDT 24
Peak memory 197620 kb
Host smart-c0dee9cd-58df-444e-aab4-f76eb7a4a637
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311838843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.2311838843
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.3734042635
Short name T606
Test name
Test status
Simulation time 232849309 ps
CPU time 0.7 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:53 PM PDT 24
Peak memory 200844 kb
Host smart-2e49d960-ff16-4800-8fb7-4e9ef70937f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734042635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.3734042635
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.2515300335
Short name T938
Test name
Test status
Simulation time 211752758 ps
CPU time 0.87 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 198656 kb
Host smart-63e1a1f8-7e60-44ec-a45e-8397a744366d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515300335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_w
akeup_race.2515300335
Directory /workspace/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.878851922
Short name T889
Test name
Test status
Simulation time 55386193 ps
CPU time 0.95 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 199404 kb
Host smart-817ab1fd-85a5-4369-a3e4-9edb7e658746
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878851922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.878851922
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1725159490
Short name T778
Test name
Test status
Simulation time 108667541 ps
CPU time 0.92 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 208876 kb
Host smart-0bef453b-0a85-4113-b410-ec4462d0bfb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725159490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1725159490
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.3383981347
Short name T736
Test name
Test status
Simulation time 56561530 ps
CPU time 0.73 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:46:50 PM PDT 24
Peak memory 198672 kb
Host smart-3a1a8bb4-037c-4d0a-84b6-ea5c71f85440
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383981347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_
cm_ctrl_config_regwen.3383981347
Directory /workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1596925146
Short name T906
Test name
Test status
Simulation time 791623300 ps
CPU time 3.34 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:46:53 PM PDT 24
Peak memory 200608 kb
Host smart-7638fd0f-40d9-48f3-81f9-cce9db17a0a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596925146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1596925146
Directory /workspace/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3278533305
Short name T400
Test name
Test status
Simulation time 1035732025 ps
CPU time 1.99 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:53 PM PDT 24
Peak memory 200524 kb
Host smart-838f97c6-ae63-46a3-9b3c-e80d447f4e47
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278533305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3278533305
Directory /workspace/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2157952572
Short name T789
Test name
Test status
Simulation time 133716768 ps
CPU time 0.87 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 199048 kb
Host smart-e484fa98-a215-4b4c-b238-25dc6b225f64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157952572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2157952572
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.3833068875
Short name T344
Test name
Test status
Simulation time 52764533 ps
CPU time 0.63 seconds
Started Jun 10 07:46:45 PM PDT 24
Finished Jun 10 07:46:57 PM PDT 24
Peak memory 198896 kb
Host smart-f8e7bf23-e40c-416c-8338-31ae528dd81c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833068875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.3833068875
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all.1928060529
Short name T943
Test name
Test status
Simulation time 1055854793 ps
CPU time 2.47 seconds
Started Jun 10 07:46:42 PM PDT 24
Finished Jun 10 07:46:56 PM PDT 24
Peak memory 200480 kb
Host smart-defb0a0e-9f5e-495a-9b02-4f700b466856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928060529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.1928060529
Directory /workspace/41.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all_with_rand_reset.3967356419
Short name T52
Test name
Test status
Simulation time 6556563571 ps
CPU time 22.44 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:47:13 PM PDT 24
Peak memory 200808 kb
Host smart-54eeb98a-3e46-49dc-ac2d-bf6f40a8f5e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967356419 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all_with_rand_reset.3967356419
Directory /workspace/41.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup.909839518
Short name T201
Test name
Test status
Simulation time 160505716 ps
CPU time 1.01 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 199228 kb
Host smart-4de9d652-f0a0-4afe-bbd8-3e44c3aa45cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909839518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.909839518
Directory /workspace/41.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup_reset.2003429232
Short name T208
Test name
Test status
Simulation time 279470709 ps
CPU time 0.74 seconds
Started Jun 10 07:46:39 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 198816 kb
Host smart-b467804c-c51d-4db0-be87-4d004c917d1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003429232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.2003429232
Directory /workspace/41.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.1208950581
Short name T15
Test name
Test status
Simulation time 22603304 ps
CPU time 0.74 seconds
Started Jun 10 07:46:40 PM PDT 24
Finished Jun 10 07:46:53 PM PDT 24
Peak memory 198676 kb
Host smart-2b9eda50-ac71-473b-b2bd-fbcafc55b2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208950581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.1208950581
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.1666012953
Short name T747
Test name
Test status
Simulation time 53470002 ps
CPU time 0.73 seconds
Started Jun 10 07:46:50 PM PDT 24
Finished Jun 10 07:47:00 PM PDT 24
Peak memory 198064 kb
Host smart-888aaea4-c359-4fd7-af9e-2404ccd99052
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666012953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.1666012953
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.3694905730
Short name T644
Test name
Test status
Simulation time 34005345 ps
CPU time 0.62 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:04 PM PDT 24
Peak memory 197560 kb
Host smart-b82f161e-b333-4009-8434-60e2f3f8afcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694905730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.3694905730
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.618180636
Short name T526
Test name
Test status
Simulation time 157703717 ps
CPU time 1.02 seconds
Started Jun 10 07:46:55 PM PDT 24
Finished Jun 10 07:47:03 PM PDT 24
Peak memory 197680 kb
Host smart-b502e80e-ee9c-4cd2-9416-2cb240e65d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618180636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.618180636
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.934260442
Short name T549
Test name
Test status
Simulation time 49129386 ps
CPU time 0.68 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:04 PM PDT 24
Peak memory 197556 kb
Host smart-4e7c6565-5201-4972-ad05-14dc70eaeafb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934260442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.934260442
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.1975027923
Short name T255
Test name
Test status
Simulation time 59684686 ps
CPU time 0.65 seconds
Started Jun 10 07:46:51 PM PDT 24
Finished Jun 10 07:47:00 PM PDT 24
Peak memory 197644 kb
Host smart-58c69147-032a-41b4-9ae4-eac65b0d9038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975027923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.1975027923
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.3513266694
Short name T872
Test name
Test status
Simulation time 67181059 ps
CPU time 0.72 seconds
Started Jun 10 07:46:51 PM PDT 24
Finished Jun 10 07:47:01 PM PDT 24
Peak memory 200828 kb
Host smart-2800b3ce-a19a-4e85-97d1-8872648d86d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513266694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.3513266694
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.2028235041
Short name T698
Test name
Test status
Simulation time 76039418 ps
CPU time 0.64 seconds
Started Jun 10 07:46:42 PM PDT 24
Finished Jun 10 07:46:55 PM PDT 24
Peak memory 198056 kb
Host smart-6af385c8-1f22-4463-af2b-f43a003e2d53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028235041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_w
akeup_race.2028235041
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.3024427011
Short name T659
Test name
Test status
Simulation time 45173767 ps
CPU time 0.7 seconds
Started Jun 10 07:46:36 PM PDT 24
Finished Jun 10 07:46:47 PM PDT 24
Peak memory 198596 kb
Host smart-7374bae6-0e21-4c03-8311-7a605959ed20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024427011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.3024427011
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.1229526115
Short name T195
Test name
Test status
Simulation time 159447852 ps
CPU time 0.78 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:06 PM PDT 24
Peak memory 208904 kb
Host smart-ae0c98bc-ef1d-4a2b-8946-5d1355f18694
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229526115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.1229526115
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.2874675955
Short name T547
Test name
Test status
Simulation time 220172459 ps
CPU time 0.84 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:08 PM PDT 24
Peak memory 198428 kb
Host smart-a2b9b17d-2c1d-48e0-9d93-3efaaa600646
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874675955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_
cm_ctrl_config_regwen.2874675955
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3224472891
Short name T800
Test name
Test status
Simulation time 796854916 ps
CPU time 3.08 seconds
Started Jun 10 07:46:46 PM PDT 24
Finished Jun 10 07:47:00 PM PDT 24
Peak memory 200448 kb
Host smart-cc646f37-c3cc-4fba-a05a-0382866f72bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224472891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3224472891
Directory /workspace/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1187553964
Short name T712
Test name
Test status
Simulation time 876001717 ps
CPU time 3.3 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:10 PM PDT 24
Peak memory 200744 kb
Host smart-6f5bb0aa-70de-4370-969f-de33c743206e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187553964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1187553964
Directory /workspace/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.2595911580
Short name T818
Test name
Test status
Simulation time 51302194 ps
CPU time 0.9 seconds
Started Jun 10 07:46:52 PM PDT 24
Finished Jun 10 07:47:01 PM PDT 24
Peak memory 198712 kb
Host smart-3431e4d2-53b4-478a-9a3d-30ffb4c202dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595911580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2595911580
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.2076183875
Short name T461
Test name
Test status
Simulation time 53353170 ps
CPU time 0.68 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:46:50 PM PDT 24
Peak memory 198080 kb
Host smart-230f72c7-cd22-402e-a616-8e5ad875df39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076183875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.2076183875
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all.1492186981
Short name T112
Test name
Test status
Simulation time 4658244578 ps
CPU time 2.5 seconds
Started Jun 10 07:46:52 PM PDT 24
Finished Jun 10 07:47:03 PM PDT 24
Peak memory 200680 kb
Host smart-3829f188-1e15-40c4-80d1-049f91e729ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492186981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.1492186981
Directory /workspace/42.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all_with_rand_reset.2121845549
Short name T140
Test name
Test status
Simulation time 16700085569 ps
CPU time 21.37 seconds
Started Jun 10 07:46:47 PM PDT 24
Finished Jun 10 07:47:19 PM PDT 24
Peak memory 200852 kb
Host smart-b192d21d-d4ce-43a2-8d54-6cdca3416289
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121845549 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all_with_rand_reset.2121845549
Directory /workspace/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup.3835132974
Short name T494
Test name
Test status
Simulation time 306910780 ps
CPU time 0.88 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:46:51 PM PDT 24
Peak memory 199360 kb
Host smart-bbecd527-4b40-4041-b836-465cafa212b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835132974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.3835132974
Directory /workspace/42.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup_reset.3318897384
Short name T893
Test name
Test status
Simulation time 293949753 ps
CPU time 1.5 seconds
Started Jun 10 07:46:38 PM PDT 24
Finished Jun 10 07:46:52 PM PDT 24
Peak memory 200568 kb
Host smart-82d012c7-93fa-4aa2-b9e3-80b0772b4736
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318897384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.3318897384
Directory /workspace/42.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.2512582308
Short name T993
Test name
Test status
Simulation time 47052411 ps
CPU time 0.78 seconds
Started Jun 10 07:46:55 PM PDT 24
Finished Jun 10 07:47:03 PM PDT 24
Peak memory 198364 kb
Host smart-d477ac0d-1c83-4404-9002-8ea8edac504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512582308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.2512582308
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.612056857
Short name T694
Test name
Test status
Simulation time 80158232 ps
CPU time 0.69 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 198660 kb
Host smart-15d1b965-c4b1-4746-b6df-bf4d979e0ef2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612056857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disa
ble_rom_integrity_check.612056857
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3940214049
Short name T719
Test name
Test status
Simulation time 29447962 ps
CPU time 0.66 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 196864 kb
Host smart-a5b06d17-cf07-4c6c-a2c1-a0b18d92ab33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940214049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.3940214049
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.3834547597
Short name T830
Test name
Test status
Simulation time 330323238 ps
CPU time 0.93 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 197544 kb
Host smart-c86a8f0e-cd37-4284-a97c-3986710c2d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834547597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.3834547597
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.2474729517
Short name T924
Test name
Test status
Simulation time 62447706 ps
CPU time 0.69 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:06 PM PDT 24
Peak memory 197484 kb
Host smart-680c3e27-e997-4add-81ba-6c6afed069e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474729517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.2474729517
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.1659048486
Short name T376
Test name
Test status
Simulation time 44191293 ps
CPU time 0.64 seconds
Started Jun 10 07:46:47 PM PDT 24
Finished Jun 10 07:46:58 PM PDT 24
Peak memory 197612 kb
Host smart-e3e594ed-beb7-4e3c-8343-f76b8e4cd284
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659048486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.1659048486
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.1487956382
Short name T329
Test name
Test status
Simulation time 39272587 ps
CPU time 0.68 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 200796 kb
Host smart-af6186ba-65f7-4f3c-a4e4-ef99e9144b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487956382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.1487956382
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.4292933941
Short name T537
Test name
Test status
Simulation time 324303633 ps
CPU time 1.05 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 199080 kb
Host smart-69a765ee-f915-4d0b-ae1c-10587d25b60f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292933941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_w
akeup_race.4292933941
Directory /workspace/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.4054102403
Short name T243
Test name
Test status
Simulation time 65633716 ps
CPU time 0.73 seconds
Started Jun 10 07:46:54 PM PDT 24
Finished Jun 10 07:47:02 PM PDT 24
Peak memory 198648 kb
Host smart-26532385-73c0-4464-a46d-4593e8fcf9b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054102403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.4054102403
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.1502634896
Short name T209
Test name
Test status
Simulation time 109886371 ps
CPU time 1.03 seconds
Started Jun 10 07:46:49 PM PDT 24
Finished Jun 10 07:47:00 PM PDT 24
Peak memory 208924 kb
Host smart-9b135a6b-5d96-4697-bb62-7243334e2c70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502634896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.1502634896
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.1448086285
Short name T159
Test name
Test status
Simulation time 287037873 ps
CPU time 1.06 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 199572 kb
Host smart-4285eab6-490b-40f3-aad0-ea13de1b3067
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448086285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_
cm_ctrl_config_regwen.1448086285
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1441525636
Short name T668
Test name
Test status
Simulation time 811295053 ps
CPU time 2.99 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 200564 kb
Host smart-c9d5e343-d80a-43be-8fdb-01ae0ebd78cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441525636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1441525636
Directory /workspace/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1896813753
Short name T369
Test name
Test status
Simulation time 918197346 ps
CPU time 3.23 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:08 PM PDT 24
Peak memory 200576 kb
Host smart-7538398f-7408-4b83-b103-cd8f5244e132
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896813753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1896813753
Directory /workspace/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.3450366892
Short name T377
Test name
Test status
Simulation time 158792324 ps
CPU time 0.91 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 198924 kb
Host smart-c44b8532-52c4-49a9-8bf1-a3a4efeefc1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450366892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3450366892
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.3741048542
Short name T353
Test name
Test status
Simulation time 34215135 ps
CPU time 0.68 seconds
Started Jun 10 07:46:52 PM PDT 24
Finished Jun 10 07:47:01 PM PDT 24
Peak memory 198884 kb
Host smart-3346ca6f-7b0b-4569-b8fb-a6fd68f06581
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741048542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.3741048542
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all.2309661151
Short name T746
Test name
Test status
Simulation time 1108230175 ps
CPU time 3.15 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:06 PM PDT 24
Peak memory 200636 kb
Host smart-49b4206e-f3c5-4865-94e1-f6fc4edb0dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309661151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.2309661151
Directory /workspace/43.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all_with_rand_reset.3034348691
Short name T277
Test name
Test status
Simulation time 4517426361 ps
CPU time 6.11 seconds
Started Jun 10 07:46:51 PM PDT 24
Finished Jun 10 07:47:06 PM PDT 24
Peak memory 200852 kb
Host smart-29e56363-2ae2-44e7-8b89-d403e333686a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034348691 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all_with_rand_reset.3034348691
Directory /workspace/43.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup.1100966292
Short name T955
Test name
Test status
Simulation time 394703110 ps
CPU time 1.01 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 199184 kb
Host smart-00a8906a-ea66-4a3c-a0ef-b04b5cf053c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100966292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.1100966292
Directory /workspace/43.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.3449055682
Short name T759
Test name
Test status
Simulation time 249463906 ps
CPU time 1.06 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 200516 kb
Host smart-660807a7-d97f-4449-a477-dcdc2028f562
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449055682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.3449055682
Directory /workspace/43.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.59034242
Short name T545
Test name
Test status
Simulation time 118607631 ps
CPU time 0.82 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:08 PM PDT 24
Peak memory 199596 kb
Host smart-5de934ea-c416-4c8a-8e40-7ad8a032c08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59034242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.59034242
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.241751392
Short name T628
Test name
Test status
Simulation time 74864150 ps
CPU time 0.69 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 198560 kb
Host smart-2886194c-25f9-4ab1-a0d7-6ac7bebfe4b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241751392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disa
ble_rom_integrity_check.241751392
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.74115913
Short name T979
Test name
Test status
Simulation time 32425677 ps
CPU time 0.65 seconds
Started Jun 10 07:46:53 PM PDT 24
Finished Jun 10 07:47:02 PM PDT 24
Peak memory 197512 kb
Host smart-1092c8ed-6f26-47ae-bcc8-abb5cdc10dcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74115913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_m
alfunc.74115913
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.3548542702
Short name T288
Test name
Test status
Simulation time 160032308 ps
CPU time 0.97 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 197552 kb
Host smart-63f9773e-b33f-4f29-9a3d-c5c6bc704285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548542702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.3548542702
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.843225260
Short name T267
Test name
Test status
Simulation time 34552220 ps
CPU time 0.64 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 197584 kb
Host smart-04803ee1-25d9-4a08-af45-bb38e76d1211
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843225260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.843225260
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.3280325470
Short name T739
Test name
Test status
Simulation time 44158136 ps
CPU time 0.59 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:04 PM PDT 24
Peak memory 197648 kb
Host smart-5f1871fb-f207-4d8c-8432-43b40be0d8f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280325470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.3280325470
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.1835244642
Short name T241
Test name
Test status
Simulation time 40225833 ps
CPU time 0.72 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 200716 kb
Host smart-8c66c1c4-0b29-47e0-b251-51a623f5e08a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835244642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.1835244642
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_wakeup_race.3587856636
Short name T379
Test name
Test status
Simulation time 236255760 ps
CPU time 1 seconds
Started Jun 10 07:46:53 PM PDT 24
Finished Jun 10 07:47:02 PM PDT 24
Peak memory 199088 kb
Host smart-96f1bb6a-e0ef-42d0-b17b-2b711e0b7f03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587856636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_w
akeup_race.3587856636
Directory /workspace/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.3583122809
Short name T448
Test name
Test status
Simulation time 154015832 ps
CPU time 0.76 seconds
Started Jun 10 07:47:02 PM PDT 24
Finished Jun 10 07:47:11 PM PDT 24
Peak memory 198244 kb
Host smart-717f1415-7d99-45e6-970d-36c5ff63e826
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583122809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.3583122809
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.1473980960
Short name T775
Test name
Test status
Simulation time 100199044 ps
CPU time 0.99 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 208908 kb
Host smart-6cd80775-c7d4-43e9-a098-29b22127e551
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473980960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.1473980960
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2130713837
Short name T230
Test name
Test status
Simulation time 103502672 ps
CPU time 0.92 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 198648 kb
Host smart-772f2926-bf43-4c7e-8846-c62ec0b30e8c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130713837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_
cm_ctrl_config_regwen.2130713837
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2819490861
Short name T256
Test name
Test status
Simulation time 1312436479 ps
CPU time 2.15 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:10 PM PDT 24
Peak memory 200508 kb
Host smart-1ea90be0-0baa-459c-9f07-781d6ddb1370
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819490861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2819490861
Directory /workspace/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1591387369
Short name T755
Test name
Test status
Simulation time 2096862940 ps
CPU time 2.14 seconds
Started Jun 10 07:46:50 PM PDT 24
Finished Jun 10 07:47:01 PM PDT 24
Peak memory 200376 kb
Host smart-dcf7f63e-2e94-4b8c-b045-80280d3fba23
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591387369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1591387369
Directory /workspace/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1746805155
Short name T599
Test name
Test status
Simulation time 67405801 ps
CPU time 0.99 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 199092 kb
Host smart-512c4b7f-0231-48ba-9beb-4b046306b435
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746805155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1746805155
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1750036585
Short name T380
Test name
Test status
Simulation time 37498788 ps
CPU time 0.71 seconds
Started Jun 10 07:46:54 PM PDT 24
Finished Jun 10 07:47:02 PM PDT 24
Peak memory 198124 kb
Host smart-95c141be-5ea8-4736-9191-87bc69a093da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750036585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1750036585
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all.179700411
Short name T246
Test name
Test status
Simulation time 2968963140 ps
CPU time 2.36 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:08 PM PDT 24
Peak memory 200564 kb
Host smart-ed443284-960b-4d81-8d35-f54ac33eb88b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179700411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.179700411
Directory /workspace/44.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all_with_rand_reset.3755117098
Short name T815
Test name
Test status
Simulation time 13124782019 ps
CPU time 39.63 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:44 PM PDT 24
Peak memory 200864 kb
Host smart-b832335e-9169-4975-9739-7af7b3d6b77e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755117098 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all_with_rand_reset.3755117098
Directory /workspace/44.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup.3586701257
Short name T715
Test name
Test status
Simulation time 259967294 ps
CPU time 0.75 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 198060 kb
Host smart-8cf8401d-1540-46fc-8e42-bced8b62e23a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586701257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.3586701257
Directory /workspace/44.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup_reset.2529018846
Short name T971
Test name
Test status
Simulation time 143955819 ps
CPU time 1.2 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:06 PM PDT 24
Peak memory 199892 kb
Host smart-74f0ec3c-f12f-4244-94c4-94b37861a62e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529018846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.2529018846
Directory /workspace/44.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.443469143
Short name T99
Test name
Test status
Simulation time 270623073 ps
CPU time 0.8 seconds
Started Jun 10 07:46:45 PM PDT 24
Finished Jun 10 07:46:57 PM PDT 24
Peak memory 199568 kb
Host smart-c557c280-e89f-4395-9fec-47fcfeb45acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443469143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.443469143
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.2605652550
Short name T187
Test name
Test status
Simulation time 119369660 ps
CPU time 0.69 seconds
Started Jun 10 07:47:01 PM PDT 24
Finished Jun 10 07:47:10 PM PDT 24
Peak memory 198740 kb
Host smart-b48af404-506d-472c-9c15-c26ee50cc7e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605652550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.2605652550
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2097911955
Short name T87
Test name
Test status
Simulation time 29500945 ps
CPU time 0.63 seconds
Started Jun 10 07:46:55 PM PDT 24
Finished Jun 10 07:47:03 PM PDT 24
Peak memory 196808 kb
Host smart-90ba327c-89af-4dd0-b1fa-a108af86509c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097911955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.2097911955
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.3812687646
Short name T300
Test name
Test status
Simulation time 319796214 ps
CPU time 1 seconds
Started Jun 10 07:47:03 PM PDT 24
Finished Jun 10 07:47:11 PM PDT 24
Peak memory 197620 kb
Host smart-a003e383-78bb-4106-9b3a-0527be950625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812687646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.3812687646
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.1208900604
Short name T944
Test name
Test status
Simulation time 60623599 ps
CPU time 0.61 seconds
Started Jun 10 07:47:02 PM PDT 24
Finished Jun 10 07:47:11 PM PDT 24
Peak memory 197652 kb
Host smart-5bfd7ba5-19db-4a4c-bbae-89e929072ab5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208900604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.1208900604
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.2749948568
Short name T751
Test name
Test status
Simulation time 68950376 ps
CPU time 0.68 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 197580 kb
Host smart-5bd77f34-c8de-4191-9b4a-36830985317d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749948568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.2749948568
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2790155913
Short name T940
Test name
Test status
Simulation time 132634113 ps
CPU time 0.67 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 200776 kb
Host smart-c8e392aa-303d-49a0-adfd-c8f9f1943963
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790155913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.2790155913
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_wakeup_race.3684182452
Short name T212
Test name
Test status
Simulation time 199279651 ps
CPU time 1.1 seconds
Started Jun 10 07:46:46 PM PDT 24
Finished Jun 10 07:46:58 PM PDT 24
Peak memory 199220 kb
Host smart-be39742e-2e92-47c9-8583-b1b0dd5f6ea7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684182452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_w
akeup_race.3684182452
Directory /workspace/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.2342137336
Short name T260
Test name
Test status
Simulation time 123054337 ps
CPU time 0.77 seconds
Started Jun 10 07:46:55 PM PDT 24
Finished Jun 10 07:47:03 PM PDT 24
Peak memory 198684 kb
Host smart-6266347c-c164-468f-b404-915196d90d75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342137336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2342137336
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.3175422151
Short name T200
Test name
Test status
Simulation time 153870935 ps
CPU time 0.78 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:06 PM PDT 24
Peak memory 208900 kb
Host smart-fdaff528-c721-4acb-be87-84e517e957ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175422151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.3175422151
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.1355391530
Short name T706
Test name
Test status
Simulation time 198495891 ps
CPU time 1.06 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 199340 kb
Host smart-4f633e79-84a4-41c2-94a6-d123e00975ea
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355391530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_
cm_ctrl_config_regwen.1355391530
Directory /workspace/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4035047043
Short name T877
Test name
Test status
Simulation time 992468742 ps
CPU time 1.94 seconds
Started Jun 10 07:47:01 PM PDT 24
Finished Jun 10 07:47:11 PM PDT 24
Peak memory 200524 kb
Host smart-c50f1299-04bb-4a74-877d-555c00991b9f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035047043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4035047043
Directory /workspace/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.247022050
Short name T282
Test name
Test status
Simulation time 1090573481 ps
CPU time 2.47 seconds
Started Jun 10 07:47:02 PM PDT 24
Finished Jun 10 07:47:12 PM PDT 24
Peak memory 200440 kb
Host smart-bd0f320f-459b-47ce-8ed0-0e83892639cd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247022050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.247022050
Directory /workspace/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.4160941621
Short name T508
Test name
Test status
Simulation time 219681782 ps
CPU time 0.87 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 198784 kb
Host smart-462aac6e-79f8-4dc9-b77c-c9049e23377c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160941621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4160941621
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.3953066494
Short name T988
Test name
Test status
Simulation time 27892255 ps
CPU time 0.69 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:06 PM PDT 24
Peak memory 198884 kb
Host smart-80ecdd49-5ffb-47c9-a3dc-2ddf60ddb204
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953066494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.3953066494
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all.1719401499
Short name T639
Test name
Test status
Simulation time 1516683570 ps
CPU time 2.62 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 200672 kb
Host smart-b83d73ed-5ab7-4f7a-b25c-a0a05f3c4ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719401499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.1719401499
Directory /workspace/45.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all_with_rand_reset.3610459420
Short name T137
Test name
Test status
Simulation time 7915070886 ps
CPU time 12.33 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:20 PM PDT 24
Peak memory 200836 kb
Host smart-efbadbe5-074f-46d5-9630-90d561d5c00e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610459420 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all_with_rand_reset.3610459420
Directory /workspace/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup.1761677805
Short name T761
Test name
Test status
Simulation time 199175704 ps
CPU time 1.13 seconds
Started Jun 10 07:47:03 PM PDT 24
Finished Jun 10 07:47:12 PM PDT 24
Peak memory 199268 kb
Host smart-ac9c8c18-ddf9-4578-b772-2d6d37e045c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761677805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.1761677805
Directory /workspace/45.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup_reset.1813066457
Short name T848
Test name
Test status
Simulation time 121720358 ps
CPU time 0.76 seconds
Started Jun 10 07:46:54 PM PDT 24
Finished Jun 10 07:47:02 PM PDT 24
Peak memory 198736 kb
Host smart-0b076c23-97a2-4565-bd1b-ae649423318b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813066457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.1813066457
Directory /workspace/45.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.2369966327
Short name T564
Test name
Test status
Simulation time 73653106 ps
CPU time 0.67 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 198080 kb
Host smart-4c272dec-54b2-4e27-aac1-243ee3be1807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369966327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.2369966327
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.1841967148
Short name T271
Test name
Test status
Simulation time 52410383 ps
CPU time 0.87 seconds
Started Jun 10 07:47:01 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 198308 kb
Host smart-9accacd8-c6d1-44a3-9bca-6b01df97063a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841967148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.1841967148
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.4064061361
Short name T276
Test name
Test status
Simulation time 39807195 ps
CPU time 0.66 seconds
Started Jun 10 07:46:55 PM PDT 24
Finished Jun 10 07:47:03 PM PDT 24
Peak memory 197576 kb
Host smart-42c01cb7-f5a2-4cfc-a12e-616a7b679877
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064061361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.4064061361
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.2140981694
Short name T973
Test name
Test status
Simulation time 604163403 ps
CPU time 0.93 seconds
Started Jun 10 07:47:01 PM PDT 24
Finished Jun 10 07:47:10 PM PDT 24
Peak memory 197668 kb
Host smart-eac07bf2-8f85-41ea-996d-7ad9d89d6aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140981694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.2140981694
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.766181
Short name T781
Test name
Test status
Simulation time 57330904 ps
CPU time 0.63 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 197548 kb
Host smart-d2be0728-4cfb-4df8-818c-99bf28b34c27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.766181
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.1073211387
Short name T191
Test name
Test status
Simulation time 50010646 ps
CPU time 0.59 seconds
Started Jun 10 07:47:05 PM PDT 24
Finished Jun 10 07:47:13 PM PDT 24
Peak memory 197600 kb
Host smart-c5f54f1a-29a5-4179-a5b8-248e29b68065
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073211387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.1073211387
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.27495293
Short name T279
Test name
Test status
Simulation time 71787633 ps
CPU time 0.66 seconds
Started Jun 10 07:47:03 PM PDT 24
Finished Jun 10 07:47:11 PM PDT 24
Peak memory 200860 kb
Host smart-001322c8-ef09-4fc1-9223-692d52b2e2c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27495293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invalid
.27495293
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.2579290080
Short name T203
Test name
Test status
Simulation time 86377569 ps
CPU time 0.86 seconds
Started Jun 10 07:46:54 PM PDT 24
Finished Jun 10 07:47:02 PM PDT 24
Peak memory 198712 kb
Host smart-b02979c3-ac88-4cdd-9531-2938202bf403
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579290080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.2579290080
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.3916644551
Short name T100
Test name
Test status
Simulation time 119698299 ps
CPU time 0.89 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 208908 kb
Host smart-9339d626-78f9-49f4-941a-3d1e82a78c19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916644551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.3916644551
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.1585250407
Short name T976
Test name
Test status
Simulation time 166995721 ps
CPU time 0.81 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 198188 kb
Host smart-b2eea04a-3f7c-4b9a-95e2-f3a45f0435b2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585250407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_
cm_ctrl_config_regwen.1585250407
Directory /workspace/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1039711988
Short name T731
Test name
Test status
Simulation time 803046415 ps
CPU time 2.94 seconds
Started Jun 10 07:47:01 PM PDT 24
Finished Jun 10 07:47:12 PM PDT 24
Peak memory 200560 kb
Host smart-4a82b133-8308-4c0b-a482-af3608332eb1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039711988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1039711988
Directory /workspace/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2653902373
Short name T305
Test name
Test status
Simulation time 736918741 ps
CPU time 2.95 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 200524 kb
Host smart-6632db0b-5fac-49ff-9460-ef575bd4688c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653902373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2653902373
Directory /workspace/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2062652332
Short name T408
Test name
Test status
Simulation time 54054098 ps
CPU time 0.85 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:06 PM PDT 24
Peak memory 199280 kb
Host smart-47e8c40b-ac60-4054-afab-a951d704ab9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062652332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2062652332
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.1721339997
Short name T824
Test name
Test status
Simulation time 53057316 ps
CPU time 0.63 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 198872 kb
Host smart-25b06a9f-d7e1-4160-b22a-adc221ad1d61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721339997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.1721339997
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all.1698247429
Short name T804
Test name
Test status
Simulation time 1274326886 ps
CPU time 3.1 seconds
Started Jun 10 07:46:53 PM PDT 24
Finished Jun 10 07:47:04 PM PDT 24
Peak memory 200644 kb
Host smart-12b3eb0b-8884-4f6a-bb94-18a7382dd5cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698247429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.1698247429
Directory /workspace/46.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all_with_rand_reset.1780777277
Short name T84
Test name
Test status
Simulation time 2034102909 ps
CPU time 6.47 seconds
Started Jun 10 07:47:02 PM PDT 24
Finished Jun 10 07:47:16 PM PDT 24
Peak memory 200784 kb
Host smart-e444c7f3-f89e-43e6-9293-1adf5a95d766
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780777277 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all_with_rand_reset.1780777277
Directory /workspace/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup.1805506367
Short name T247
Test name
Test status
Simulation time 82603667 ps
CPU time 0.76 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 198104 kb
Host smart-51ff6ba8-27c4-4404-a9be-c493b3e07bfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805506367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.1805506367
Directory /workspace/46.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup_reset.1199002093
Short name T333
Test name
Test status
Simulation time 216964865 ps
CPU time 1.11 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:10 PM PDT 24
Peak memory 199496 kb
Host smart-c40a393f-e261-4caa-8267-dc361bde4764
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199002093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.1199002093
Directory /workspace/46.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.4003265157
Short name T452
Test name
Test status
Simulation time 57511138 ps
CPU time 0.91 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 199908 kb
Host smart-41b93bcf-94ee-4cea-9da1-8648d3c7afdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003265157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.4003265157
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.1354875463
Short name T219
Test name
Test status
Simulation time 28842992 ps
CPU time 0.65 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:08 PM PDT 24
Peak memory 197568 kb
Host smart-48a98f4b-0f58-4011-9c5a-ea80857e11d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354875463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.1354875463
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.2599323277
Short name T629
Test name
Test status
Simulation time 162923667 ps
CPU time 0.99 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:08 PM PDT 24
Peak memory 197888 kb
Host smart-d8edaff2-8825-4124-93ae-d4f423f03a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599323277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.2599323277
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.862708788
Short name T903
Test name
Test status
Simulation time 66048184 ps
CPU time 0.62 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:08 PM PDT 24
Peak memory 197628 kb
Host smart-a56eff07-d43d-424f-8a25-bb57608f0662
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862708788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.862708788
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.296035199
Short name T703
Test name
Test status
Simulation time 78839970 ps
CPU time 0.61 seconds
Started Jun 10 07:47:02 PM PDT 24
Finished Jun 10 07:47:10 PM PDT 24
Peak memory 197580 kb
Host smart-a0d01522-0eaa-488c-b01a-c6feefac867a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296035199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.296035199
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.2490571160
Short name T533
Test name
Test status
Simulation time 67943334 ps
CPU time 0.7 seconds
Started Jun 10 07:46:59 PM PDT 24
Finished Jun 10 07:47:08 PM PDT 24
Peak memory 200848 kb
Host smart-3d6c672d-f349-4613-a633-57bff17ba261
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490571160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.2490571160
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.3138551685
Short name T375
Test name
Test status
Simulation time 84339526 ps
CPU time 0.69 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 197876 kb
Host smart-ae8d0baa-acca-48f3-989b-983e49d78f12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138551685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_w
akeup_race.3138551685
Directory /workspace/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.2496684200
Short name T395
Test name
Test status
Simulation time 77108904 ps
CPU time 0.99 seconds
Started Jun 10 07:47:01 PM PDT 24
Finished Jun 10 07:47:10 PM PDT 24
Peak memory 199652 kb
Host smart-0978f8f0-970e-4657-8c5f-6bd3ad9160f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496684200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.2496684200
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.756350813
Short name T317
Test name
Test status
Simulation time 279156831 ps
CPU time 0.95 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 199532 kb
Host smart-22f2339e-149e-4fec-bdda-6aa258a42fab
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756350813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_c
m_ctrl_config_regwen.756350813
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.166332136
Short name T280
Test name
Test status
Simulation time 2834692447 ps
CPU time 1.94 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:06 PM PDT 24
Peak memory 200480 kb
Host smart-b5d54e2f-615c-40d2-b4f5-452644f2c88b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166332136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.166332136
Directory /workspace/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1253176689
Short name T257
Test name
Test status
Simulation time 1097708569 ps
CPU time 2.51 seconds
Started Jun 10 07:47:01 PM PDT 24
Finished Jun 10 07:47:11 PM PDT 24
Peak memory 200644 kb
Host smart-1b53cbdc-c000-4d8a-a896-ea565b5126d9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253176689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1253176689
Directory /workspace/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3113895335
Short name T771
Test name
Test status
Simulation time 113615402 ps
CPU time 0.93 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 198764 kb
Host smart-a088709a-6c9e-41fa-9a83-4636f468e83f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113895335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3113895335
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.2823115559
Short name T691
Test name
Test status
Simulation time 173280522 ps
CPU time 0.66 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:04 PM PDT 24
Peak memory 198036 kb
Host smart-fb2ecb4f-4495-4282-9e98-b8b965b7d4a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823115559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.2823115559
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all.2738241051
Short name T650
Test name
Test status
Simulation time 1340907845 ps
CPU time 3.42 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 200420 kb
Host smart-fa41dd9c-b71a-4380-a4c3-e8f8039eb152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738241051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.2738241051
Directory /workspace/47.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all_with_rand_reset.1583119083
Short name T552
Test name
Test status
Simulation time 5824017637 ps
CPU time 7.95 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:13 PM PDT 24
Peak memory 200868 kb
Host smart-c2925c0a-bdea-42a4-a622-163600930a3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583119083 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all_with_rand_reset.1583119083
Directory /workspace/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup.3561470874
Short name T330
Test name
Test status
Simulation time 260967642 ps
CPU time 0.95 seconds
Started Jun 10 07:46:54 PM PDT 24
Finished Jun 10 07:47:03 PM PDT 24
Peak memory 199112 kb
Host smart-019a2505-ff09-485d-ab0a-2ca7592d33c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561470874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.3561470874
Directory /workspace/47.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup_reset.1763529706
Short name T960
Test name
Test status
Simulation time 275989696 ps
CPU time 0.97 seconds
Started Jun 10 07:47:03 PM PDT 24
Finished Jun 10 07:47:11 PM PDT 24
Peak memory 200524 kb
Host smart-7efe36e6-eae8-466e-ab7e-f2534a91cbd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763529706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.1763529706
Directory /workspace/47.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.303812900
Short name T110
Test name
Test status
Simulation time 42522144 ps
CPU time 0.89 seconds
Started Jun 10 07:47:03 PM PDT 24
Finished Jun 10 07:47:12 PM PDT 24
Peak memory 199736 kb
Host smart-779a7695-9527-4b63-afef-eab852b68aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303812900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.303812900
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.1277895574
Short name T558
Test name
Test status
Simulation time 75680847 ps
CPU time 0.69 seconds
Started Jun 10 07:47:08 PM PDT 24
Finished Jun 10 07:47:14 PM PDT 24
Peak memory 198096 kb
Host smart-a8aa069c-4c75-444b-a698-85183bf18108
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277895574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.1277895574
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.4219516161
Short name T722
Test name
Test status
Simulation time 30230145 ps
CPU time 0.63 seconds
Started Jun 10 07:47:05 PM PDT 24
Finished Jun 10 07:47:13 PM PDT 24
Peak memory 196868 kb
Host smart-252c7e43-cec7-4919-a11c-b60d83b3bd46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219516161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.4219516161
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.1630601268
Short name T506
Test name
Test status
Simulation time 161259211 ps
CPU time 0.98 seconds
Started Jun 10 07:47:07 PM PDT 24
Finished Jun 10 07:47:14 PM PDT 24
Peak memory 197588 kb
Host smart-90ea0440-2c9e-47c3-8784-9c9b49e12142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630601268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.1630601268
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.1612099182
Short name T569
Test name
Test status
Simulation time 66265207 ps
CPU time 0.65 seconds
Started Jun 10 07:47:03 PM PDT 24
Finished Jun 10 07:47:11 PM PDT 24
Peak memory 197624 kb
Host smart-3921b11a-55b0-43d8-9a43-1719ceaeccd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612099182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.1612099182
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.2658598065
Short name T325
Test name
Test status
Simulation time 91898026 ps
CPU time 0.65 seconds
Started Jun 10 07:47:10 PM PDT 24
Finished Jun 10 07:47:16 PM PDT 24
Peak memory 197880 kb
Host smart-1bf11271-bd0e-4534-8516-ff360044056d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658598065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.2658598065
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.3374432251
Short name T895
Test name
Test status
Simulation time 56390452 ps
CPU time 0.67 seconds
Started Jun 10 07:47:10 PM PDT 24
Finished Jun 10 07:47:16 PM PDT 24
Peak memory 200736 kb
Host smart-14cd0e9d-cd79-4c8f-85bc-8323fdd70322
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374432251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.3374432251
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.1131597999
Short name T748
Test name
Test status
Simulation time 270417951 ps
CPU time 1.04 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 199172 kb
Host smart-3649f548-163e-44fa-8c81-58ae812b192d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131597999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_w
akeup_race.1131597999
Directory /workspace/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.4165078404
Short name T218
Test name
Test status
Simulation time 125866842 ps
CPU time 0.85 seconds
Started Jun 10 07:46:58 PM PDT 24
Finished Jun 10 07:47:07 PM PDT 24
Peak memory 199464 kb
Host smart-b278de80-4842-4647-a26d-05a2185fafac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165078404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.4165078404
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.1317229803
Short name T557
Test name
Test status
Simulation time 113370045 ps
CPU time 0.89 seconds
Started Jun 10 07:47:06 PM PDT 24
Finished Jun 10 07:47:14 PM PDT 24
Peak memory 208916 kb
Host smart-3f9f60f3-a4e9-4ef6-b914-09f9578dea9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317229803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.1317229803
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.136348528
Short name T229
Test name
Test status
Simulation time 43300085 ps
CPU time 0.63 seconds
Started Jun 10 07:47:07 PM PDT 24
Finished Jun 10 07:47:13 PM PDT 24
Peak memory 198092 kb
Host smart-90448b6c-b45b-4ad6-b5f4-da9339bfd15d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136348528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_c
m_ctrl_config_regwen.136348528
Directory /workspace/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3156038942
Short name T225
Test name
Test status
Simulation time 928038409 ps
CPU time 3.05 seconds
Started Jun 10 07:47:01 PM PDT 24
Finished Jun 10 07:47:12 PM PDT 24
Peak memory 200584 kb
Host smart-acb4bb30-6cc4-41ca-ab4a-9a656f67a008
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156038942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3156038942
Directory /workspace/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1379957680
Short name T758
Test name
Test status
Simulation time 1322764647 ps
CPU time 2.21 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:11 PM PDT 24
Peak memory 200712 kb
Host smart-dc3adce4-8a85-4eef-8575-e3636ec0b737
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379957680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1379957680
Directory /workspace/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.2730972832
Short name T154
Test name
Test status
Simulation time 240083760 ps
CPU time 0.9 seconds
Started Jun 10 07:47:10 PM PDT 24
Finished Jun 10 07:47:16 PM PDT 24
Peak memory 199156 kb
Host smart-89dea028-93ba-456e-8b1f-01226083474d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730972832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2730972832
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.339027530
Short name T870
Test name
Test status
Simulation time 53748834 ps
CPU time 0.64 seconds
Started Jun 10 07:46:56 PM PDT 24
Finished Jun 10 07:47:05 PM PDT 24
Peak memory 198132 kb
Host smart-501c94a6-3a80-486a-8903-e92053d7dafe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339027530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.339027530
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all.1278026769
Short name T437
Test name
Test status
Simulation time 860542051 ps
CPU time 2.79 seconds
Started Jun 10 07:47:04 PM PDT 24
Finished Jun 10 07:47:14 PM PDT 24
Peak memory 200656 kb
Host smart-da2523a0-4264-4465-90d1-22833c826f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278026769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.1278026769
Directory /workspace/48.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all_with_rand_reset.296924197
Short name T153
Test name
Test status
Simulation time 9553565094 ps
CPU time 12.83 seconds
Started Jun 10 07:47:08 PM PDT 24
Finished Jun 10 07:47:27 PM PDT 24
Peak memory 200816 kb
Host smart-d70e3ba2-3935-430b-83a9-969b1b1d5ad9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296924197 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all_with_rand_reset.296924197
Directory /workspace/48.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup.128694845
Short name T497
Test name
Test status
Simulation time 222858740 ps
CPU time 1.12 seconds
Started Jun 10 07:46:57 PM PDT 24
Finished Jun 10 07:47:06 PM PDT 24
Peak memory 199084 kb
Host smart-da9e4d86-1ae8-42cf-870b-b53e96754d95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128694845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.128694845
Directory /workspace/48.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup_reset.327065121
Short name T713
Test name
Test status
Simulation time 248503288 ps
CPU time 0.8 seconds
Started Jun 10 07:47:00 PM PDT 24
Finished Jun 10 07:47:09 PM PDT 24
Peak memory 198840 kb
Host smart-7aac9006-4da8-47a2-8647-0178d815baa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327065121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.327065121
Directory /workspace/48.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.2678360393
Short name T135
Test name
Test status
Simulation time 46456556 ps
CPU time 0.82 seconds
Started Jun 10 07:47:10 PM PDT 24
Finished Jun 10 07:47:16 PM PDT 24
Peak memory 198448 kb
Host smart-da949619-df89-4492-9ba5-fb08f1024d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678360393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.2678360393
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.2881270833
Short name T315
Test name
Test status
Simulation time 98272587 ps
CPU time 0.72 seconds
Started Jun 10 07:47:10 PM PDT 24
Finished Jun 10 07:47:16 PM PDT 24
Peak memory 198708 kb
Host smart-66ec04a2-87e9-46ae-a3ce-16157f210516
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881270833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.2881270833
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3853369499
Short name T633
Test name
Test status
Simulation time 69277862 ps
CPU time 0.57 seconds
Started Jun 10 07:47:07 PM PDT 24
Finished Jun 10 07:47:14 PM PDT 24
Peak memory 196868 kb
Host smart-202ad6a5-657d-4a47-8489-7094249a8812
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853369499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.3853369499
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.1666618728
Short name T868
Test name
Test status
Simulation time 557365495 ps
CPU time 0.98 seconds
Started Jun 10 07:47:08 PM PDT 24
Finished Jun 10 07:47:15 PM PDT 24
Peak memory 197620 kb
Host smart-74365f5a-9205-4cec-abd4-b24ef994a021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666618728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.1666618728
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.3927453522
Short name T954
Test name
Test status
Simulation time 67125916 ps
CPU time 0.63 seconds
Started Jun 10 07:47:10 PM PDT 24
Finished Jun 10 07:47:16 PM PDT 24
Peak memory 197680 kb
Host smart-878694e7-5cd7-40d0-8ef5-f42b491ffdab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927453522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.3927453522
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.1389213305
Short name T777
Test name
Test status
Simulation time 89768336 ps
CPU time 0.63 seconds
Started Jun 10 07:47:03 PM PDT 24
Finished Jun 10 07:47:11 PM PDT 24
Peak memory 197728 kb
Host smart-6150f3e4-8752-4ad2-a1a0-dc3a3427079a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389213305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.1389213305
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.3052660804
Short name T231
Test name
Test status
Simulation time 94445190 ps
CPU time 0.67 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:47:35 PM PDT 24
Peak memory 200812 kb
Host smart-e528d001-10bb-451b-b3d3-e35f0b379d12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052660804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.3052660804
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.3443765151
Short name T855
Test name
Test status
Simulation time 265141628 ps
CPU time 0.93 seconds
Started Jun 10 07:47:11 PM PDT 24
Finished Jun 10 07:47:16 PM PDT 24
Peak memory 197852 kb
Host smart-7c3b356e-1d29-42ab-8fef-596e584c4bf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443765151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_w
akeup_race.3443765151
Directory /workspace/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.1979127390
Short name T367
Test name
Test status
Simulation time 66024120 ps
CPU time 0.7 seconds
Started Jun 10 07:47:12 PM PDT 24
Finished Jun 10 07:47:17 PM PDT 24
Peak memory 198728 kb
Host smart-6dd1983e-ef4d-425e-be51-fe1287a3fd95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979127390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.1979127390
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.2923335482
Short name T226
Test name
Test status
Simulation time 197071163 ps
CPU time 0.84 seconds
Started Jun 10 07:47:14 PM PDT 24
Finished Jun 10 07:47:18 PM PDT 24
Peak memory 208996 kb
Host smart-682c2294-f618-4d45-afb2-32ac62463b25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923335482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.2923335482
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2338800154
Short name T323
Test name
Test status
Simulation time 236040345 ps
CPU time 0.88 seconds
Started Jun 10 07:47:05 PM PDT 24
Finished Jun 10 07:47:13 PM PDT 24
Peak memory 199456 kb
Host smart-7d4d0e52-6433-480d-a905-9effafd29e10
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338800154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_
cm_ctrl_config_regwen.2338800154
Directory /workspace/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.488284080
Short name T794
Test name
Test status
Simulation time 802007579 ps
CPU time 3.14 seconds
Started Jun 10 07:47:02 PM PDT 24
Finished Jun 10 07:47:13 PM PDT 24
Peak memory 200524 kb
Host smart-42ee51eb-8158-456e-8dcb-090c239efe88
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488284080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.488284080
Directory /workspace/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3579943540
Short name T310
Test name
Test status
Simulation time 952305101 ps
CPU time 2.66 seconds
Started Jun 10 07:47:07 PM PDT 24
Finished Jun 10 07:47:16 PM PDT 24
Peak memory 200632 kb
Host smart-1931d8d0-0bee-4971-9ba6-d6f404198042
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579943540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3579943540
Directory /workspace/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.2427393553
Short name T724
Test name
Test status
Simulation time 162242292 ps
CPU time 0.91 seconds
Started Jun 10 07:47:07 PM PDT 24
Finished Jun 10 07:47:14 PM PDT 24
Peak memory 198912 kb
Host smart-400f7b5a-c86f-4071-bc18-6e531460bfd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427393553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2427393553
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.3047410095
Short name T866
Test name
Test status
Simulation time 55614312 ps
CPU time 0.65 seconds
Started Jun 10 07:47:09 PM PDT 24
Finished Jun 10 07:47:15 PM PDT 24
Peak memory 198072 kb
Host smart-cf36e421-cfa8-4a71-81a6-de0dfbf0efab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047410095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.3047410095
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all.4024534781
Short name T989
Test name
Test status
Simulation time 1731476671 ps
CPU time 4.33 seconds
Started Jun 10 07:47:15 PM PDT 24
Finished Jun 10 07:47:23 PM PDT 24
Peak memory 200652 kb
Host smart-bbc87da5-531f-4297-913d-b80d2878c5ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024534781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.4024534781
Directory /workspace/49.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all_with_rand_reset.837579623
Short name T77
Test name
Test status
Simulation time 7331898288 ps
CPU time 10.49 seconds
Started Jun 10 07:47:25 PM PDT 24
Finished Jun 10 07:47:38 PM PDT 24
Peak memory 200892 kb
Host smart-7aca7628-ae30-44bd-be23-6a62fc2ec0af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837579623 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all_with_rand_reset.837579623
Directory /workspace/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup.567287746
Short name T816
Test name
Test status
Simulation time 75560351 ps
CPU time 0.7 seconds
Started Jun 10 07:47:06 PM PDT 24
Finished Jun 10 07:47:13 PM PDT 24
Peak memory 197892 kb
Host smart-551bcdc5-574e-4ec3-ba06-4e056590a735
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567287746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.567287746
Directory /workspace/49.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup_reset.962415372
Short name T432
Test name
Test status
Simulation time 284532678 ps
CPU time 0.92 seconds
Started Jun 10 07:47:06 PM PDT 24
Finished Jun 10 07:47:14 PM PDT 24
Peak memory 199736 kb
Host smart-d79bc049-89de-42bf-913d-69d3fe17150e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962415372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.962415372
Directory /workspace/49.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.995234765
Short name T374
Test name
Test status
Simulation time 69415135 ps
CPU time 0.8 seconds
Started Jun 10 07:44:51 PM PDT 24
Finished Jun 10 07:44:58 PM PDT 24
Peak memory 199488 kb
Host smart-c5a8df43-d47f-4c49-9b24-c6e27b7d8a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995234765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.995234765
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.716037580
Short name T577
Test name
Test status
Simulation time 31167883 ps
CPU time 0.62 seconds
Started Jun 10 07:44:51 PM PDT 24
Finished Jun 10 07:44:59 PM PDT 24
Peak memory 196848 kb
Host smart-d08baf6f-04d1-4dc3-8b08-b2bbbf7d9b6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716037580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_m
alfunc.716037580
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.629425756
Short name T332
Test name
Test status
Simulation time 409169836 ps
CPU time 0.96 seconds
Started Jun 10 07:44:54 PM PDT 24
Finished Jun 10 07:45:01 PM PDT 24
Peak memory 197656 kb
Host smart-aa687c64-b13f-43c5-86fd-2dcd6a98bab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629425756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.629425756
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.2753874508
Short name T502
Test name
Test status
Simulation time 39761557 ps
CPU time 0.66 seconds
Started Jun 10 07:44:55 PM PDT 24
Finished Jun 10 07:45:01 PM PDT 24
Peak memory 197696 kb
Host smart-9fe4a1fb-8f2e-40b8-8d97-0f377ca0e585
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753874508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.2753874508
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.843209306
Short name T717
Test name
Test status
Simulation time 41454234 ps
CPU time 0.64 seconds
Started Jun 10 07:44:51 PM PDT 24
Finished Jun 10 07:44:59 PM PDT 24
Peak memory 198024 kb
Host smart-36e3a163-7067-4ac2-84fe-b1bffbb21009
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843209306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.843209306
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.1406622234
Short name T340
Test name
Test status
Simulation time 42658917 ps
CPU time 0.71 seconds
Started Jun 10 07:44:48 PM PDT 24
Finished Jun 10 07:44:55 PM PDT 24
Peak memory 200748 kb
Host smart-ec895b6f-976a-488b-a42d-92aeab822907
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406622234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.1406622234
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.1263054699
Short name T779
Test name
Test status
Simulation time 79940884 ps
CPU time 0.67 seconds
Started Jun 10 07:44:49 PM PDT 24
Finished Jun 10 07:44:56 PM PDT 24
Peak memory 197796 kb
Host smart-b6eeeef8-f299-4419-8dec-ce87e3c29191
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263054699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wa
keup_race.1263054699
Directory /workspace/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.2881206839
Short name T6
Test name
Test status
Simulation time 80573835 ps
CPU time 0.74 seconds
Started Jun 10 07:44:49 PM PDT 24
Finished Jun 10 07:44:56 PM PDT 24
Peak memory 198148 kb
Host smart-e3b796fd-4f91-4412-b5f5-1bad7cdd1d6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881206839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.2881206839
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.170966219
Short name T341
Test name
Test status
Simulation time 97226874 ps
CPU time 0.95 seconds
Started Jun 10 07:44:46 PM PDT 24
Finished Jun 10 07:44:53 PM PDT 24
Peak memory 208992 kb
Host smart-4a806803-c48a-489b-b5d3-046b8e7f1baf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170966219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.170966219
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3766428452
Short name T88
Test name
Test status
Simulation time 98353696 ps
CPU time 0.75 seconds
Started Jun 10 07:44:51 PM PDT 24
Finished Jun 10 07:44:58 PM PDT 24
Peak memory 198216 kb
Host smart-eb2fa6a2-fd0d-4981-98cb-fa36776da2de
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766428452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_c
m_ctrl_config_regwen.3766428452
Directory /workspace/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1456295358
Short name T368
Test name
Test status
Simulation time 823436952 ps
CPU time 2.98 seconds
Started Jun 10 07:44:51 PM PDT 24
Finished Jun 10 07:45:01 PM PDT 24
Peak memory 200564 kb
Host smart-2ceecc62-17ba-4202-9e8f-0325a9164800
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456295358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1456295358
Directory /workspace/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2141583910
Short name T262
Test name
Test status
Simulation time 915778653 ps
CPU time 2.91 seconds
Started Jun 10 07:44:51 PM PDT 24
Finished Jun 10 07:45:00 PM PDT 24
Peak memory 200612 kb
Host smart-7f427ec0-5790-495c-9450-a4327fe1a974
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141583910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2141583910
Directory /workspace/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1040392204
Short name T438
Test name
Test status
Simulation time 175863958 ps
CPU time 0.85 seconds
Started Jun 10 07:44:52 PM PDT 24
Finished Jun 10 07:44:59 PM PDT 24
Peak memory 199308 kb
Host smart-cad1668b-7b23-4ba6-bc45-372f1fc5f148
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040392204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1040392204
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.1874731641
Short name T876
Test name
Test status
Simulation time 119898051 ps
CPU time 0.65 seconds
Started Jun 10 07:44:49 PM PDT 24
Finished Jun 10 07:44:56 PM PDT 24
Peak memory 198052 kb
Host smart-29f63c08-6972-47cf-986b-809f81aab169
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874731641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.1874731641
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all.680366180
Short name T106
Test name
Test status
Simulation time 575518087 ps
CPU time 1.7 seconds
Started Jun 10 07:44:48 PM PDT 24
Finished Jun 10 07:44:56 PM PDT 24
Peak memory 200516 kb
Host smart-ca5d5042-5c73-45ce-aeff-3b9a87acc5fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680366180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.680366180
Directory /workspace/5.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all_with_rand_reset.438369992
Short name T150
Test name
Test status
Simulation time 6111297682 ps
CPU time 11.01 seconds
Started Jun 10 07:44:48 PM PDT 24
Finished Jun 10 07:45:06 PM PDT 24
Peak memory 200892 kb
Host smart-737b3850-8d4e-4cab-a618-169c4707cea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438369992 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all_with_rand_reset.438369992
Directory /workspace/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.3003250496
Short name T823
Test name
Test status
Simulation time 246800999 ps
CPU time 0.85 seconds
Started Jun 10 07:44:51 PM PDT 24
Finished Jun 10 07:44:58 PM PDT 24
Peak memory 199156 kb
Host smart-0dab205b-5578-41b0-9591-0e6ecf2283b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003250496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.3003250496
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup_reset.2851924337
Short name T302
Test name
Test status
Simulation time 59388832 ps
CPU time 0.78 seconds
Started Jun 10 07:44:50 PM PDT 24
Finished Jun 10 07:44:57 PM PDT 24
Peak memory 198592 kb
Host smart-466ee1b0-7077-4596-a468-a648c8e06ced
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851924337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.2851924337
Directory /workspace/5.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.1441117513
Short name T326
Test name
Test status
Simulation time 142059140 ps
CPU time 0.9 seconds
Started Jun 10 07:45:00 PM PDT 24
Finished Jun 10 07:45:05 PM PDT 24
Peak memory 199684 kb
Host smart-decd420f-6f7f-44ef-9e99-7b45e692be2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441117513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.1441117513
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.2570041978
Short name T970
Test name
Test status
Simulation time 66420406 ps
CPU time 0.72 seconds
Started Jun 10 07:44:57 PM PDT 24
Finished Jun 10 07:45:02 PM PDT 24
Peak memory 198624 kb
Host smart-9c3e96cf-3ffe-4542-94f2-01315c75cdc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570041978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.2570041978
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.913987788
Short name T664
Test name
Test status
Simulation time 36763816 ps
CPU time 0.58 seconds
Started Jun 10 07:44:59 PM PDT 24
Finished Jun 10 07:45:04 PM PDT 24
Peak memory 197536 kb
Host smart-c075c8f2-b71e-48bc-bcfe-cd2b6dea58e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913987788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_m
alfunc.913987788
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.2835905957
Short name T299
Test name
Test status
Simulation time 158406084 ps
CPU time 1.03 seconds
Started Jun 10 07:45:00 PM PDT 24
Finished Jun 10 07:45:05 PM PDT 24
Peak memory 197952 kb
Host smart-089e1bf3-cb63-4038-84dd-11d8fc3c9ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835905957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.2835905957
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.3521027441
Short name T603
Test name
Test status
Simulation time 42848922 ps
CPU time 0.65 seconds
Started Jun 10 07:44:55 PM PDT 24
Finished Jun 10 07:45:01 PM PDT 24
Peak memory 197628 kb
Host smart-4d72a189-7b20-4157-985a-41974cf0c365
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521027441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3521027441
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.3085816201
Short name T2
Test name
Test status
Simulation time 40703887 ps
CPU time 0.56 seconds
Started Jun 10 07:44:53 PM PDT 24
Finished Jun 10 07:45:00 PM PDT 24
Peak memory 198040 kb
Host smart-26da1a4e-70ef-4e6f-9067-3b4bb7e52b65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085816201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.3085816201
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2365537807
Short name T163
Test name
Test status
Simulation time 79513317 ps
CPU time 0.72 seconds
Started Jun 10 07:44:55 PM PDT 24
Finished Jun 10 07:45:01 PM PDT 24
Peak memory 200792 kb
Host smart-e528aa90-87c3-46b4-a8d2-d505b234f7f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365537807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.2365537807
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.1391922719
Short name T284
Test name
Test status
Simulation time 82997103 ps
CPU time 0.74 seconds
Started Jun 10 07:44:54 PM PDT 24
Finished Jun 10 07:45:01 PM PDT 24
Peak memory 197856 kb
Host smart-005c6534-7da0-4560-b44c-84588ab1527d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391922719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wa
keup_race.1391922719
Directory /workspace/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.1446511506
Short name T773
Test name
Test status
Simulation time 71265142 ps
CPU time 0.66 seconds
Started Jun 10 07:44:54 PM PDT 24
Finished Jun 10 07:45:00 PM PDT 24
Peak memory 197848 kb
Host smart-3c13c336-1b4d-47a3-b67c-b46d8f3185a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446511506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1446511506
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.1892968257
Short name T223
Test name
Test status
Simulation time 168196001 ps
CPU time 0.83 seconds
Started Jun 10 07:45:01 PM PDT 24
Finished Jun 10 07:45:06 PM PDT 24
Peak memory 209064 kb
Host smart-c6929b7a-1c02-41c4-ad84-7ab817ba5b9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892968257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1892968257
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1387061487
Short name T58
Test name
Test status
Simulation time 521087956 ps
CPU time 0.96 seconds
Started Jun 10 07:44:57 PM PDT 24
Finished Jun 10 07:45:03 PM PDT 24
Peak memory 199752 kb
Host smart-81934508-fd8a-49a4-b25d-2facc7bcaab2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387061487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_c
m_ctrl_config_regwen.1387061487
Directory /workspace/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.585240420
Short name T929
Test name
Test status
Simulation time 1322900257 ps
CPU time 2.19 seconds
Started Jun 10 07:44:58 PM PDT 24
Finished Jun 10 07:45:04 PM PDT 24
Peak memory 200528 kb
Host smart-e9fc62ba-99e6-4823-9306-d1eeaa42bfc6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585240420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.585240420
Directory /workspace/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.773343178
Short name T679
Test name
Test status
Simulation time 1472667291 ps
CPU time 1.98 seconds
Started Jun 10 07:44:57 PM PDT 24
Finished Jun 10 07:45:04 PM PDT 24
Peak memory 200260 kb
Host smart-7d551e28-b857-4777-b5ae-1a3c66d09237
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773343178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.773343178
Directory /workspace/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.1451806808
Short name T782
Test name
Test status
Simulation time 54186662 ps
CPU time 0.9 seconds
Started Jun 10 07:44:55 PM PDT 24
Finished Jun 10 07:45:01 PM PDT 24
Peak memory 199172 kb
Host smart-25a5a510-b8e3-4927-8a7c-7929af7c9178
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451806808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1451806808
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.3413652775
Short name T501
Test name
Test status
Simulation time 63312477 ps
CPU time 0.71 seconds
Started Jun 10 07:44:50 PM PDT 24
Finished Jun 10 07:44:57 PM PDT 24
Peak memory 198056 kb
Host smart-fae4185c-b32d-41c3-83b1-82852a5c17cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413652775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.3413652775
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all.244647392
Short name T787
Test name
Test status
Simulation time 299476970 ps
CPU time 1.78 seconds
Started Jun 10 07:45:01 PM PDT 24
Finished Jun 10 07:45:07 PM PDT 24
Peak memory 200760 kb
Host smart-bf085cee-4c71-4cf7-adb2-698dd2e4698c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244647392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.244647392
Directory /workspace/6.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all_with_rand_reset.2390679222
Short name T147
Test name
Test status
Simulation time 6917939624 ps
CPU time 23.63 seconds
Started Jun 10 07:45:00 PM PDT 24
Finished Jun 10 07:45:27 PM PDT 24
Peak memory 200892 kb
Host smart-bfc445a5-b5c1-4296-9bad-e061ebe3c79c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390679222 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all_with_rand_reset.2390679222
Directory /workspace/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup.3423555725
Short name T798
Test name
Test status
Simulation time 34944955 ps
CPU time 0.76 seconds
Started Jun 10 07:44:54 PM PDT 24
Finished Jun 10 07:45:01 PM PDT 24
Peak memory 197896 kb
Host smart-a2b9d62c-2522-45c2-a991-6eb9f0130992
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423555725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.3423555725
Directory /workspace/6.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup_reset.1513289995
Short name T873
Test name
Test status
Simulation time 111045950 ps
CPU time 0.97 seconds
Started Jun 10 07:44:55 PM PDT 24
Finished Jun 10 07:45:01 PM PDT 24
Peak memory 198832 kb
Host smart-4192f1c2-edee-4e61-a903-59107ff96018
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513289995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.1513289995
Directory /workspace/6.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.3752251681
Short name T927
Test name
Test status
Simulation time 33737430 ps
CPU time 1.1 seconds
Started Jun 10 07:45:00 PM PDT 24
Finished Jun 10 07:45:06 PM PDT 24
Peak memory 200552 kb
Host smart-de9d97a0-94eb-47e9-8152-a8153122da38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752251681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.3752251681
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.2196921198
Short name T631
Test name
Test status
Simulation time 61364491 ps
CPU time 0.75 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:11 PM PDT 24
Peak memory 198708 kb
Host smart-615515b9-a53b-45d8-8946-36cbf3ac0d06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196921198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.2196921198
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2051862276
Short name T281
Test name
Test status
Simulation time 28884226 ps
CPU time 0.67 seconds
Started Jun 10 07:44:56 PM PDT 24
Finished Jun 10 07:45:02 PM PDT 24
Peak memory 197536 kb
Host smart-26e06c42-8a67-4e07-a3c1-e367a031b1ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051862276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.2051862276
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.2105854311
Short name T594
Test name
Test status
Simulation time 689102694 ps
CPU time 0.95 seconds
Started Jun 10 07:44:57 PM PDT 24
Finished Jun 10 07:45:03 PM PDT 24
Peak memory 197668 kb
Host smart-54aea614-f9b4-4152-946d-708566ac5895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105854311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.2105854311
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.2632529918
Short name T354
Test name
Test status
Simulation time 54335356 ps
CPU time 0.7 seconds
Started Jun 10 07:44:57 PM PDT 24
Finished Jun 10 07:45:03 PM PDT 24
Peak memory 196968 kb
Host smart-f2d1209b-09c0-4c4e-9a82-a1ca6726800c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632529918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.2632529918
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.1589062484
Short name T869
Test name
Test status
Simulation time 49038055 ps
CPU time 0.7 seconds
Started Jun 10 07:44:58 PM PDT 24
Finished Jun 10 07:45:03 PM PDT 24
Peak memory 197652 kb
Host smart-36b96378-958d-4c00-ba3e-97a77ebb70a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589062484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.1589062484
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.1548879906
Short name T320
Test name
Test status
Simulation time 130324559 ps
CPU time 0.67 seconds
Started Jun 10 07:45:03 PM PDT 24
Finished Jun 10 07:45:08 PM PDT 24
Peak memory 200760 kb
Host smart-4d86f4ac-9f1f-4a97-95ab-9938f3251bb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548879906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.1548879906
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.2917354654
Short name T656
Test name
Test status
Simulation time 174220308 ps
CPU time 0.74 seconds
Started Jun 10 07:44:56 PM PDT 24
Finished Jun 10 07:45:02 PM PDT 24
Peak memory 197848 kb
Host smart-0d530eaf-ee61-4109-8e1c-fe6e41b39b5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917354654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wa
keup_race.2917354654
Directory /workspace/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.4247007330
Short name T509
Test name
Test status
Simulation time 161055027 ps
CPU time 0.74 seconds
Started Jun 10 07:45:00 PM PDT 24
Finished Jun 10 07:45:05 PM PDT 24
Peak memory 198172 kb
Host smart-73c89311-01c2-4d36-a10f-513688acf98d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247007330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.4247007330
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.3722926224
Short name T708
Test name
Test status
Simulation time 103665580 ps
CPU time 0.88 seconds
Started Jun 10 07:44:58 PM PDT 24
Finished Jun 10 07:45:04 PM PDT 24
Peak memory 208948 kb
Host smart-2ff1e25c-d24f-4864-9dae-c5a380264de3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722926224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.3722926224
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.3149867620
Short name T783
Test name
Test status
Simulation time 152250405 ps
CPU time 1.06 seconds
Started Jun 10 07:44:57 PM PDT 24
Finished Jun 10 07:45:03 PM PDT 24
Peak memory 199556 kb
Host smart-acabcb14-d9be-4899-9d54-b7fa21524e28
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149867620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_c
m_ctrl_config_regwen.3149867620
Directory /workspace/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.390034063
Short name T409
Test name
Test status
Simulation time 2286070962 ps
CPU time 2.05 seconds
Started Jun 10 07:44:56 PM PDT 24
Finished Jun 10 07:45:03 PM PDT 24
Peak memory 200684 kb
Host smart-d23d9710-743a-4378-965c-b34ce7c248e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390034063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.390034063
Directory /workspace/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3064285838
Short name T183
Test name
Test status
Simulation time 881560650 ps
CPU time 3.06 seconds
Started Jun 10 07:44:58 PM PDT 24
Finished Jun 10 07:45:06 PM PDT 24
Peak memory 200520 kb
Host smart-a21533c6-651f-4920-b4a9-cafbf9f8be46
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064285838 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3064285838
Directory /workspace/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1380452731
Short name T799
Test name
Test status
Simulation time 74870200 ps
CPU time 0.85 seconds
Started Jun 10 07:45:01 PM PDT 24
Finished Jun 10 07:45:06 PM PDT 24
Peak memory 198920 kb
Host smart-fb2816ab-d8fc-4450-8530-e6600652e38d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380452731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1380452731
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.571866028
Short name T597
Test name
Test status
Simulation time 32109371 ps
CPU time 0.68 seconds
Started Jun 10 07:44:58 PM PDT 24
Finished Jun 10 07:45:03 PM PDT 24
Peak memory 198852 kb
Host smart-cc8f1396-ef0c-487a-9c32-88e3ee21d678
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571866028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.571866028
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all.3678424341
Short name T470
Test name
Test status
Simulation time 575566402 ps
CPU time 1.48 seconds
Started Jun 10 07:45:03 PM PDT 24
Finished Jun 10 07:45:08 PM PDT 24
Peak memory 200664 kb
Host smart-215191b7-26ef-456e-a6af-a59a52d1b63a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678424341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.3678424341
Directory /workspace/7.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all_with_rand_reset.3565284532
Short name T66
Test name
Test status
Simulation time 2010942587 ps
CPU time 8.04 seconds
Started Jun 10 07:45:05 PM PDT 24
Finished Jun 10 07:45:17 PM PDT 24
Peak memory 200756 kb
Host smart-219cc6c2-cd21-427f-a742-c311a4dbec13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565284532 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all_with_rand_reset.3565284532
Directory /workspace/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup.1769449138
Short name T420
Test name
Test status
Simulation time 176675078 ps
CPU time 0.96 seconds
Started Jun 10 07:45:01 PM PDT 24
Finished Jun 10 07:45:06 PM PDT 24
Peak memory 199188 kb
Host smart-37891218-3d1a-4068-a95f-450b0a7534e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769449138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.1769449138
Directory /workspace/7.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup_reset.2474959115
Short name T686
Test name
Test status
Simulation time 359656234 ps
CPU time 1 seconds
Started Jun 10 07:45:00 PM PDT 24
Finished Jun 10 07:45:05 PM PDT 24
Peak memory 199804 kb
Host smart-693235fa-b5e2-4def-8ce7-1dfa97c59c79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474959115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.2474959115
Directory /workspace/7.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.3749133644
Short name T108
Test name
Test status
Simulation time 45442829 ps
CPU time 0.95 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:11 PM PDT 24
Peak memory 200292 kb
Host smart-9fa5bb5b-7ca6-4c08-b22d-931ea45c7e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749133644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.3749133644
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.865477383
Short name T173
Test name
Test status
Simulation time 65075005 ps
CPU time 0.78 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:11 PM PDT 24
Peak memory 198616 kb
Host smart-6fcd4764-94c3-429b-8706-ce053488fce4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865477383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disab
le_rom_integrity_check.865477383
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3149679142
Short name T172
Test name
Test status
Simulation time 41524761 ps
CPU time 0.61 seconds
Started Jun 10 07:45:08 PM PDT 24
Finished Jun 10 07:45:13 PM PDT 24
Peak memory 197576 kb
Host smart-eaf786ec-b398-4e7a-a943-eef03b1cf094
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149679142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.3149679142
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.235089681
Short name T5
Test name
Test status
Simulation time 317373754 ps
CPU time 1 seconds
Started Jun 10 07:45:05 PM PDT 24
Finished Jun 10 07:45:10 PM PDT 24
Peak memory 197616 kb
Host smart-8afa005f-dd6f-4b8a-932c-4bb8f91f3d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235089681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.235089681
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.4016608975
Short name T892
Test name
Test status
Simulation time 46738617 ps
CPU time 0.65 seconds
Started Jun 10 07:45:05 PM PDT 24
Finished Jun 10 07:45:10 PM PDT 24
Peak memory 197588 kb
Host smart-dca02f72-c8e2-4ef5-9fbf-92d9795b4fc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016608975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.4016608975
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.1947499019
Short name T436
Test name
Test status
Simulation time 47720136 ps
CPU time 0.62 seconds
Started Jun 10 07:45:02 PM PDT 24
Finished Jun 10 07:45:06 PM PDT 24
Peak memory 197652 kb
Host smart-2a5c9c39-778e-43ba-ac37-fd8cc5358bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947499019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.1947499019
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.1735888070
Short name T357
Test name
Test status
Simulation time 42915519 ps
CPU time 0.71 seconds
Started Jun 10 07:45:01 PM PDT 24
Finished Jun 10 07:45:06 PM PDT 24
Peak memory 200792 kb
Host smart-70255f6e-cb63-441c-bb87-ee893cefa92b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735888070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.1735888070
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.4107854353
Short name T378
Test name
Test status
Simulation time 278988427 ps
CPU time 0.88 seconds
Started Jun 10 07:45:04 PM PDT 24
Finished Jun 10 07:45:09 PM PDT 24
Peak memory 198108 kb
Host smart-167eeb7f-1ae3-4e5f-8600-0862584024d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107854353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wa
keup_race.4107854353
Directory /workspace/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.1527764490
Short name T213
Test name
Test status
Simulation time 138755240 ps
CPU time 0.89 seconds
Started Jun 10 07:45:03 PM PDT 24
Finished Jun 10 07:45:08 PM PDT 24
Peak memory 199444 kb
Host smart-2c81a398-0fa2-4513-98f9-2887c926b0a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527764490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.1527764490
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.2769504222
Short name T534
Test name
Test status
Simulation time 111602938 ps
CPU time 0.92 seconds
Started Jun 10 07:45:04 PM PDT 24
Finished Jun 10 07:45:08 PM PDT 24
Peak memory 209036 kb
Host smart-c20d5b97-ea45-4328-b55e-b283ecacbb59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769504222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.2769504222
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.2628187810
Short name T920
Test name
Test status
Simulation time 216984641 ps
CPU time 1.28 seconds
Started Jun 10 07:45:04 PM PDT 24
Finished Jun 10 07:45:09 PM PDT 24
Peak memory 200440 kb
Host smart-9a9514c0-0520-46ce-8af6-2e8ce4cf4188
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628187810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_c
m_ctrl_config_regwen.2628187810
Directory /workspace/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1239821206
Short name T146
Test name
Test status
Simulation time 1199679864 ps
CPU time 2.4 seconds
Started Jun 10 07:45:04 PM PDT 24
Finished Jun 10 07:45:11 PM PDT 24
Peak memory 200432 kb
Host smart-b0f13df3-d2ae-4910-8ade-abb879742a8f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239821206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1239821206
Directory /workspace/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3311521164
Short name T608
Test name
Test status
Simulation time 858074955 ps
CPU time 3.47 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:14 PM PDT 24
Peak memory 200584 kb
Host smart-84f56e21-9c35-444b-a886-3c0a781d05d1
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311521164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3311521164
Directory /workspace/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3942684981
Short name T459
Test name
Test status
Simulation time 95702832 ps
CPU time 0.85 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:11 PM PDT 24
Peak memory 198904 kb
Host smart-3c41b182-a275-4ae4-9580-f7cea5a43979
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942684981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3942684981
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.200894300
Short name T473
Test name
Test status
Simulation time 40289079 ps
CPU time 0.67 seconds
Started Jun 10 07:45:05 PM PDT 24
Finished Jun 10 07:45:10 PM PDT 24
Peak memory 198904 kb
Host smart-b5d66c99-14a2-492d-9a9f-18a22ca173c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200894300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.200894300
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all.3720761194
Short name T841
Test name
Test status
Simulation time 1438731267 ps
CPU time 2.61 seconds
Started Jun 10 07:45:10 PM PDT 24
Finished Jun 10 07:45:17 PM PDT 24
Peak memory 200644 kb
Host smart-1150fb23-b309-4f90-9a58-5408ccfb391a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720761194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.3720761194
Directory /workspace/8.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all_with_rand_reset.2069912184
Short name T152
Test name
Test status
Simulation time 9830910849 ps
CPU time 29.46 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:40 PM PDT 24
Peak memory 200828 kb
Host smart-c3391b4f-ee9b-4087-ac42-db88f87e24ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069912184 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all_with_rand_reset.2069912184
Directory /workspace/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup.3516313301
Short name T80
Test name
Test status
Simulation time 44575653 ps
CPU time 0.63 seconds
Started Jun 10 07:45:07 PM PDT 24
Finished Jun 10 07:45:12 PM PDT 24
Peak memory 197764 kb
Host smart-fedb25e3-bbd7-4f0b-8c06-27b82db14a90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516313301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.3516313301
Directory /workspace/8.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup_reset.3342349179
Short name T864
Test name
Test status
Simulation time 102753586 ps
CPU time 0.81 seconds
Started Jun 10 07:45:02 PM PDT 24
Finished Jun 10 07:45:07 PM PDT 24
Peak memory 198140 kb
Host smart-7d7902ab-6946-4f23-9bf1-86de32a4ef31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342349179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.3342349179
Directory /workspace/8.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.1091579346
Short name T891
Test name
Test status
Simulation time 276994468 ps
CPU time 0.7 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:11 PM PDT 24
Peak memory 198136 kb
Host smart-d4209afb-18e7-4cfe-9997-45a73fe0a2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091579346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.1091579346
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.2801459891
Short name T165
Test name
Test status
Simulation time 44201953 ps
CPU time 0.73 seconds
Started Jun 10 07:45:04 PM PDT 24
Finished Jun 10 07:45:09 PM PDT 24
Peak memory 198588 kb
Host smart-79ecd327-0519-4381-9131-5934cfffc11d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801459891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.2801459891
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1958087458
Short name T640
Test name
Test status
Simulation time 30911199 ps
CPU time 0.6 seconds
Started Jun 10 07:45:08 PM PDT 24
Finished Jun 10 07:45:13 PM PDT 24
Peak memory 196872 kb
Host smart-9e0e9624-f722-4618-a09e-26efcbdf2f30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958087458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.1958087458
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.2169397839
Short name T986
Test name
Test status
Simulation time 566667181 ps
CPU time 1.01 seconds
Started Jun 10 07:45:09 PM PDT 24
Finished Jun 10 07:45:14 PM PDT 24
Peak memory 197648 kb
Host smart-e609119e-68b0-4d24-aeb2-9a108d039181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169397839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.2169397839
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.539511748
Short name T734
Test name
Test status
Simulation time 87767542 ps
CPU time 0.64 seconds
Started Jun 10 07:45:04 PM PDT 24
Finished Jun 10 07:45:08 PM PDT 24
Peak memory 196924 kb
Host smart-4799366f-075b-48c6-ae55-4cfc37abe043
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539511748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.539511748
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.3166473583
Short name T415
Test name
Test status
Simulation time 36365583 ps
CPU time 0.62 seconds
Started Jun 10 07:45:10 PM PDT 24
Finished Jun 10 07:45:15 PM PDT 24
Peak memory 197568 kb
Host smart-441bb880-9550-4515-8fd4-365fd6ddbf24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166473583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.3166473583
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.1727247494
Short name T860
Test name
Test status
Simulation time 47670280 ps
CPU time 0.69 seconds
Started Jun 10 07:45:10 PM PDT 24
Finished Jun 10 07:45:15 PM PDT 24
Peak memory 200668 kb
Host smart-e99bd177-e2d6-4401-958a-37917e8bc6ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727247494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.1727247494
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.1239571112
Short name T455
Test name
Test status
Simulation time 171800939 ps
CPU time 0.97 seconds
Started Jun 10 07:45:08 PM PDT 24
Finished Jun 10 07:45:13 PM PDT 24
Peak memory 197912 kb
Host smart-692365ab-8edb-41f1-be2f-e89744689855
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239571112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wa
keup_race.1239571112
Directory /workspace/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.768990904
Short name T156
Test name
Test status
Simulation time 465501767 ps
CPU time 0.83 seconds
Started Jun 10 07:45:09 PM PDT 24
Finished Jun 10 07:45:14 PM PDT 24
Peak memory 199232 kb
Host smart-acce91d1-6d2b-4563-90a4-5dbfaad0cec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768990904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.768990904
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.2122791078
Short name T662
Test name
Test status
Simulation time 106890843 ps
CPU time 1.14 seconds
Started Jun 10 07:45:04 PM PDT 24
Finished Jun 10 07:45:09 PM PDT 24
Peak memory 200696 kb
Host smart-9acdba88-455e-4919-938e-e71060707ea6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122791078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.2122791078
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.2718641160
Short name T671
Test name
Test status
Simulation time 283655263 ps
CPU time 1.25 seconds
Started Jun 10 07:45:09 PM PDT 24
Finished Jun 10 07:45:15 PM PDT 24
Peak memory 200364 kb
Host smart-5de5469a-3ab5-4e1e-9f38-50e3b7aada2f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718641160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_c
m_ctrl_config_regwen.2718641160
Directory /workspace/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1073775023
Short name T521
Test name
Test status
Simulation time 1179047382 ps
CPU time 2.43 seconds
Started Jun 10 07:45:09 PM PDT 24
Finished Jun 10 07:45:16 PM PDT 24
Peak memory 200660 kb
Host smart-1c55b5e5-beb6-4c3d-8541-adf213429ddf
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073775023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1073775023
Directory /workspace/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.921250967
Short name T844
Test name
Test status
Simulation time 1015884201 ps
CPU time 2.23 seconds
Started Jun 10 07:45:06 PM PDT 24
Finished Jun 10 07:45:12 PM PDT 24
Peak memory 200564 kb
Host smart-4324dab9-1353-4f5b-b07a-f0ef4190ce6d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921250967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.921250967
Directory /workspace/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3114736679
Short name T349
Test name
Test status
Simulation time 106773431 ps
CPU time 0.82 seconds
Started Jun 10 07:45:05 PM PDT 24
Finished Jun 10 07:45:10 PM PDT 24
Peak memory 198916 kb
Host smart-a06fda88-5b0d-481b-9cc6-2c05f150a118
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114736679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3114736679
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.1057429274
Short name T987
Test name
Test status
Simulation time 29679838 ps
CPU time 0.68 seconds
Started Jun 10 07:45:01 PM PDT 24
Finished Jun 10 07:45:06 PM PDT 24
Peak memory 198888 kb
Host smart-3c675987-b483-4b99-b605-aa61d2d3f570
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057429274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.1057429274
Directory /workspace/9.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all.3146112628
Short name T964
Test name
Test status
Simulation time 2083049905 ps
CPU time 6.88 seconds
Started Jun 10 07:45:07 PM PDT 24
Finished Jun 10 07:45:19 PM PDT 24
Peak memory 200680 kb
Host smart-ad6e6fc0-3cf1-46cc-b663-72224c4c0cdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146112628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.3146112628
Directory /workspace/9.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all_with_rand_reset.993909214
Short name T487
Test name
Test status
Simulation time 10466712421 ps
CPU time 17.93 seconds
Started Jun 10 07:45:03 PM PDT 24
Finished Jun 10 07:45:25 PM PDT 24
Peak memory 200844 kb
Host smart-7d9569c1-81d8-451f-86a6-5a0b70603f0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993909214 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all_with_rand_reset.993909214
Directory /workspace/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup.3876364454
Short name T249
Test name
Test status
Simulation time 30920325 ps
CPU time 0.71 seconds
Started Jun 10 07:45:10 PM PDT 24
Finished Jun 10 07:45:15 PM PDT 24
Peak memory 197780 kb
Host smart-138627df-6689-4820-aeee-61cc2c62ea07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876364454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.3876364454
Directory /workspace/9.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup_reset.1918288785
Short name T638
Test name
Test status
Simulation time 510072073 ps
CPU time 1.23 seconds
Started Jun 10 07:45:07 PM PDT 24
Finished Jun 10 07:45:12 PM PDT 24
Peak memory 200432 kb
Host smart-09dbed8f-8162-420e-9f42-fa2bb0dc61a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918288785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.1918288785
Directory /workspace/9.pwrmgr_wakeup_reset/latest
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