Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34795 1 T1 60 T2 541 T5 52
auto[1] 32515 1 T1 40 T2 554 T5 48


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34368 1 T1 52 T2 574 T5 50
auto[1] 32942 1 T1 48 T2 521 T5 50


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32662 1 T1 50 T2 515 T5 56
auto[1] 34648 1 T1 50 T2 580 T5 44


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 37951 1 T1 50 T2 639 T5 50
auto[1] 29359 1 T1 50 T2 456 T5 50


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33163 1 T1 44 T2 563 T5 46
auto[1] 34147 1 T1 56 T2 532 T5 54


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34331 1 T1 48 T2 558 T5 44
auto[1] 32979 1 T1 52 T2 537 T5 56


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1220 1 T1 1 T2 15 T5 3
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 942 1 T1 1 T2 11 T5 3
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1136 1 T1 3 T2 19 T5 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 914 1 T1 3 T2 16 T5 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1172 1 T1 1 T2 9 T7 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 915 1 T1 1 T2 5 T7 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1980 1 T1 3 T2 25 T7 3
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1714 1 T1 3 T2 25 T7 3
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1193 1 T1 2 T2 20 T5 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 929 1 T1 2 T2 14 T5 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1156 1 T2 25 T5 2 T7 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 880 1 T2 18 T5 2 T7 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1086 1 T1 3 T2 20 T5 3
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 843 1 T1 3 T2 12 T5 3
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1197 1 T1 1 T2 14 T5 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 959 1 T1 1 T2 10 T5 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1144 1 T1 1 T2 23 T5 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 889 1 T1 1 T2 15 T5 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1187 1 T1 4 T2 25 T5 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 894 1 T1 4 T2 21 T5 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1157 1 T2 17 T5 3 T32 3
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 867 1 T2 8 T5 3 T32 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1135 1 T1 4 T2 20 T5 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 860 1 T1 4 T2 15 T5 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1201 1 T1 2 T2 22 T5 4
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 908 1 T1 2 T2 14 T5 4
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1242 1 T1 2 T2 15 T5 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 934 1 T1 2 T2 10 T5 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1141 1 T1 2 T2 29 T5 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 867 1 T1 2 T2 16 T5 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1207 1 T1 1 T2 21 T5 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 926 1 T1 1 T2 12 T5 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1172 1 T1 2 T2 20 T5 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 884 1 T1 2 T2 16 T5 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1148 1 T2 30 T33 3 T60 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 885 1 T2 21 T33 3 T11 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1131 1 T1 1 T2 17 T5 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 882 1 T1 1 T2 10 T5 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1129 1 T2 22 T5 1 T7 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 863 1 T2 16 T5 1 T7 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1158 1 T1 1 T2 24 T5 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 884 1 T1 1 T2 19 T5 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1154 1 T1 2 T2 19 T5 3
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 910 1 T1 2 T2 15 T5 3
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1099 1 T1 2 T2 27 T5 3
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 841 1 T1 2 T2 20 T5 3
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1133 1 T1 4 T2 22 T5 3
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 859 1 T1 4 T2 18 T5 3
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1137 1 T1 2 T2 20 T5 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 890 1 T1 2 T2 11 T5 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1173 1 T2 18 T32 1 T33 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 866 1 T2 13 T32 1 T33 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1142 1 T1 2 T2 20 T5 3
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 893 1 T1 2 T2 11 T5 3
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1142 1 T2 23 T5 3 T7 4
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 868 1 T2 21 T5 3 T7 4
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1152 1 T2 15 T7 2 T32 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 893 1 T2 9 T7 2 T32 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1183 1 T2 18 T5 2 T7 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 905 1 T2 12 T5 2 T7 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1158 1 T1 3 T2 14 T5 2
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 872 1 T1 3 T2 12 T5 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1186 1 T1 1 T2 11 T7 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 923 1 T1 1 T2 10 T7 1

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