Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
debug_cp	2	0	2	100.00	100	1	1	0
dft_cp	2	0	2	100.00	100	1	1	0
done_cp	2	0	2	100.00	100	1	1	0
good_cp	2	0	2	100.00	100	1	1	0

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
blockers_cross	16	1	15	93.75	100	1	1	0

Summary for Variable debug_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for debug_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44119	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

off

174687

1

T1

786

T2

881

T3

1

on

19236

1

T1

283

T19

5

T20

62

---

Summary for Variable dft_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for dft_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44414	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

off

170934

1

T1

429

T2

881

T3

1

on

22694

1

T1

841

T19

2

T20

1358

---

Summary for Variable done_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for done_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	182854	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

35502

1

T1

50

T2

704

T5

50

true

19686

1

T1

107

T2

177

T3

1

---

Summary for Variable good_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for good_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	175368	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

20566

1

T1

50

T2

352

T5

50

true

42108

1

T1

158

T2

529

T3

1

---

Summary for Cross blockers_cross

Samples crossed: done_cp good_cp dft_cp debug_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for blockers_cross

Uncovered bins

done_cp	good_cp	dft_cp	debug_cp	COUNT	AT LEAST	NUMBER	STATUS
[false]	[true]	[on]	[on]	0	1	1

Covered bins

done_cp

good_cp

dft_cp

debug_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

false

off

off

17873

1

T1

2

T2

352

T5

50

false

false

off

on

145

1

T1

4

T46

1

T163

1

false

false

on

off

174

1

T1

19

T20

39

T162

1

false

false

on

on

243

1

T1

2

T46

1

T167

2

false

true

off

off

15133

1

T2

352

T7

30

T11

26

false

true

off

on

3

1

T171

1

T172

1

T173

1

false

true

on

off

4

1

T102

1

T174

1

T175

1

true

false

off

off

59

1

T19

1

T47

1

T161

2

true

false

off

on

23

1

T19

1

T163

1

T166

2

true

false

on

off

19

1

T161

1

T162

1

T163

1

true

false

on

on

75

1

T19

1

T102

2

T161

2

true

true

off

off

14098

1

T1

3

T2

177

T3

1

true

true

off

on

317

1

T1

8

T19

1

T20

2

true

true

on

off

336

1

T1

23

T20

41

T46

4

true

true

on

on

409

1

T1

4

T20

4

T46

9