Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33690 1 T1 52 T3 200 T4 28
auto[1] 32016 1 T1 48 T3 172 T4 13


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33662 1 T1 46 T3 187 T4 23
auto[1] 32044 1 T1 54 T3 185 T4 18


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32134 1 T1 46 T3 160 T4 21
auto[1] 33572 1 T1 54 T3 212 T4 20


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36755 1 T1 50 T3 216 T4 26
auto[1] 28951 1 T1 50 T3 156 T4 15


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32284 1 T1 44 T3 198 T4 23
auto[1] 33422 1 T1 56 T3 174 T4 18


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33623 1 T1 58 T3 186 T4 20
auto[1] 32083 1 T1 42 T3 186 T4 21


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1159 1 T1 1 T3 8 T4 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 926 1 T1 1 T3 6 T4 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1141 1 T1 1 T3 5 T4 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 901 1 T1 1 T3 3 T4 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1061 1 T1 2 T3 7 T4 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 828 1 T1 2 T3 3 T4 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1868 1 T1 2 T3 10 T4 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1621 1 T1 2 T3 9 T4 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1104 1 T1 2 T3 7 T10 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 868 1 T1 2 T3 5 T10 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1181 1 T1 2 T3 10 T4 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 921 1 T1 2 T3 7 T4 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1114 1 T1 1 T3 11 T4 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 876 1 T1 1 T3 9 T4 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1135 1 T3 7 T4 1 T10 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 896 1 T3 6 T10 2 T27 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1175 1 T1 1 T3 6 T4 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 935 1 T1 1 T3 2 T4 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1132 1 T1 1 T3 9 T10 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 905 1 T1 1 T3 6 T10 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1110 1 T1 4 T3 6 T6 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 872 1 T1 4 T3 5 T10 4
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1112 1 T1 1 T3 12 T10 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 858 1 T1 1 T3 9 T10 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1091 1 T1 1 T3 2 T4 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 856 1 T1 1 T3 2 T4 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1188 1 T1 2 T3 7 T4 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 905 1 T1 2 T3 4 T10 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1111 1 T1 1 T3 5 T4 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 877 1 T1 1 T3 4 T4 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1110 1 T1 4 T3 5 T4 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 853 1 T1 4 T3 3 T27 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1124 1 T3 10 T4 2 T10 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 854 1 T3 6 T4 1 T10 2
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1121 1 T1 3 T3 8 T10 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 886 1 T1 3 T3 6 T10 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1158 1 T1 4 T3 2 T10 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 903 1 T1 4 T3 1 T10 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1100 1 T1 1 T3 3 T10 4
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 889 1 T1 1 T3 2 T10 4
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1109 1 T3 5 T4 1 T10 4
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 868 1 T3 3 T10 4 T24 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1124 1 T1 1 T3 9 T10 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 876 1 T1 1 T3 9 T10 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1141 1 T1 1 T10 1 T13 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 907 1 T1 1 T10 1 T14 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1122 1 T1 2 T3 6 T13 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 880 1 T1 2 T3 4 T27 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1119 1 T1 3 T3 8 T4 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 864 1 T1 3 T3 5 T4 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1155 1 T1 3 T3 7 T4 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 895 1 T1 3 T3 6 T10 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1128 1 T3 6 T10 3 T27 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 889 1 T3 5 T10 3 T27 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1095 1 T1 2 T3 3 T6 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 839 1 T1 2 T3 2 T6 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1123 1 T1 1 T3 6 T4 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 875 1 T1 1 T3 4 T6 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1073 1 T3 10 T10 1 T13 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 830 1 T3 7 T10 1 T14 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1164 1 T1 1 T3 7 T4 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 945 1 T1 1 T3 4 T4 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1107 1 T1 2 T3 9 T4 3
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 853 1 T1 2 T3 9 T10 1

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