Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31534

1

T1

5

T2

8

T3

4

auto[1]

29678

1

T1

1

T2

6

T3

2

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31436

1

T1

2

T2

6

T3

2

auto[1]

29776

1

T1

4

T2

8

T3

4

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29895

1

T1

3

T2

8

T3

1

auto[1]

31317

1

T1

3

T2

6

T3

5

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34247

1

T1

4

T2

7

T3

4

auto[1]

26965

1

T1

2

T2

7

T3

2

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29870

1

T1

2

T2

8

T3

3

auto[1]

31342

1

T1

4

T2

6

T3

3

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31308

1

T1

1

T2

10

T3

3

auto[1]

29904

1

T1

5

T2

4

T3

3

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1061

1

T6

2

T10

2

T51

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

855

1

T6

2

T10

2

T51

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1049

1

T10

2

T51

2

T14

17

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

835

1

T10

2

T51

1

T14

16

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1028

1

T2

1

T51

2

T14

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

797

1

T2

1

T51

2

T14

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1749

1

T2

1

T6

2

T41

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1511

1

T2

1

T6

2

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1067

1

T10

4

T56

1

T83

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

839

1

T10

4

T83

1

T14

21

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1094

1

T14

20

T16

6

T84

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

849

1

T14

17

T16

4

T84

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1060

1

T6

2

T10

1

T14

16

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

818

1

T6

1

T10

1

T14

15

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1108

1

T1

1

T10

1

T83

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

867

1

T1

1

T10

1

T83

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1081

1

T2

1

T10

2

T51

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

867

1

T2

1

T10

2

T51

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1071

1

T2

1

T3

1

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

819

1

T2

1

T10

4

T51

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

988

1

T1

1

T6

1

T10

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

770

1

T6

1

T10

2

T83

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1034

1

T10

1

T51

1

T14

19

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

802

1

T10

1

T14

15

T16

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

988

1

T1

1

T10

6

T51

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

785

1

T1

1

T10

6

T51

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1101

1

T3

1

T83

1

T14

21

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

843

1

T3

1

T83

1

T14

17

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1057

1

T3

1

T51

2

T83

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

840

1

T51

2

T83

2

T14

12

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1069

1

T10

3

T56

1

T14

17

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

832

1

T10

3

T14

16

T16

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1036

1

T6

1

T10

2

T51

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

829

1

T6

1

T10

2

T51

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1047

1

T6

1

T10

1

T51

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

808

1

T6

1

T10

1

T51

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1068

1

T6

1

T10

1

T51

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

838

1

T6

1

T10

1

T51

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1011

1

T3

1

T10

2

T83

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

802

1

T3

1

T10

2

T83

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1036

1

T6

2

T83

1

T14

18

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

820

1

T6

1

T83

1

T14

17

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

989

1

T6

1

T10

1

T83

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

771

1

T6

1

T10

1

T83

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1061

1

T2

1

T51

3

T83

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

841

1

T2

1

T51

2

T83

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1067

1

T51

3

T56

1

T14

12

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

825

1

T51

3

T56

1

T14

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1018

1

T2

1

T10

2

T14

15

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

811

1

T2

1

T10

2

T14

14

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1060

1

T10

3

T56

1

T14

13

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

808

1

T10

3

T14

11

T16

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1087

1

T10

2

T51

1

T14

18

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

850

1

T10

2

T14

18

T60

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1067

1

T10

3

T51

2

T56

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

851

1

T10

3

T51

1

T83

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1023

1

T10

1

T83

1

T14

24

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

810

1

T10

1

T83

1

T14

21

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1022

1

T2

1

T14

12

T15

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

778

1

T2

1

T14

12

T16

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1046

1

T10

2

T51

1

T56

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

820

1

T10

2

T56

1

T14

14

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1004

1

T1

1

T10

2

T83

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

774

1

T10

2

T83

1

T14

10