Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31609

1

T1

15

T2

24

T4

48

auto[1]

30065

1

T1

8

T2

10

T4

52

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31619

1

T1

17

T2

23

T4

50

auto[1]

30055

1

T1

6

T2

11

T4

50

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30267

1

T1

13

T2

16

T4

54

auto[1]

31407

1

T1

10

T2

18

T4

46

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34894

1

T1

21

T2

23

T4

50

auto[1]

26780

1

T1

2

T2

11

T4

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30394

1

T1

10

T2

14

T4

50

auto[1]

31280

1

T1

13

T2

20

T4

50

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31777

1

T1

13

T2

29

T4

70

auto[1]

29897

1

T1

10

T2

5

T4

30

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1146

1

T1

1

T2

2

T4

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

905

1

T2

1

T4

2

T5

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1089

1

T2

2

T4

2

T6

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

837

1

T2

1

T4

2

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1077

1

T1

3

T2

1

T4

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

833

1

T2

1

T4

4

T5

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1761

1

T1

2

T2

3

T4

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1485

1

T1

2

T2

3

T4

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1032

1

T2

1

T6

4

T7

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

781

1

T2

1

T6

2

T7

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1078

1

T5

1

T6

5

T7

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

837

1

T5

1

T6

3

T7

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1081

1

T1

1

T2

1

T6

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

832

1

T6

1

T7

1

T55

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1054

1

T1

1

T4

2

T5

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

818

1

T4

2

T5

2

T6

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1095

1

T2

1

T4

3

T5

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

831

1

T2

1

T4

3

T5

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1061

1

T2

1

T4

1

T5

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

802

1

T4

1

T5

2

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

995

1

T1

1

T4

3

T6

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

761

1

T4

3

T6

2

T7

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1099

1

T2

3

T4

1

T6

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

825

1

T2

1

T4

1

T7

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1041

1

T1

2

T4

1

T5

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

773

1

T4

1

T5

1

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1092

1

T1

1

T4

2

T5

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

818

1

T4

2

T5

3

T6

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1096

1

T1

1

T5

2

T6

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

861

1

T5

2

T6

1

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1044

1

T4

1

T5

1

T6

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

769

1

T4

1

T5

1

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1038

1

T1

1

T2

1

T4

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

782

1

T4

1

T5

2

T6

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1117

1

T1

2

T2

1

T4

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

853

1

T4

3

T5

1

T6

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1053

1

T1

1

T2

2

T4

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

806

1

T4

3

T5

2

T6

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1058

1

T2

1

T4

1

T5

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

811

1

T2

1

T4

1

T5

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1051

1

T1

1

T4

1

T6

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

812

1

T4

1

T6

2

T7

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1038

1

T1

1

T4

1

T5

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

806

1

T4

1

T5

2

T6

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1092

1

T1

1

T4

2

T6

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

836

1

T4

2

T6

3

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1033

1

T4

1

T5

1

T6

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

787

1

T4

1

T5

1

T6

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1099

1

T2

1

T4

3

T5

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

863

1

T4

3

T5

4

T6

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1089

1

T4

3

T9

1

T36

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

818

1

T4

3

T9

1

T36

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1127

1

T4

1

T5

2

T6

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

882

1

T4

1

T5

2

T6

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1021

1

T2

1

T4

2

T5

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

758

1

T4

2

T5

3

T6

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1072

1

T4

1

T5

3

T6

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

819

1

T4

1

T5

3

T6

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1090

1

T1

1

T4

1

T5

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

829

1

T4

1

T5

3

T6

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1027

1

T2

1

T4

2

T5

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

768

1

T2

1

T4

2

T5

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1048

1

T5

1

T6

3

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

782

1

T5

1

T6

1

T9

1