Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30101

1

T3

12

T6

5

T9

2

auto[1]

28904

1

T3

6

T6

1

T8

6

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30013

1

T3

14

T6

3

T8

2

auto[1]

28992

1

T3

4

T6

3

T8

4

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29005

1

T3

14

T6

4

T8

4

auto[1]

30000

1

T3

4

T6

2

T8

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33229

1

T3

9

T6

4

T8

4

auto[1]

25776

1

T3

9

T6

2

T8

2

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28682

1

T3

10

T6

2

T8

4

auto[1]

30323

1

T3

8

T6

4

T8

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30168

1

T3

10

T6

5

T9

2

auto[1]

28837

1

T3

8

T6

1

T8

6

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

977

1

T3

1

T6

1

T26

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

769

1

T3

1

T6

1

T26

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1029

1

T14

1

T26

1

T54

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

798

1

T14

1

T26

1

T55

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1059

1

T14

2

T26

1

T55

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

818

1

T14

2

T26

1

T55

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1644

1

T3

1

T9

1

T14

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1418

1

T3

1

T9

1

T14

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1053

1

T3

2

T14

2

T15

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

810

1

T3

2

T14

2

T26

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

958

1

T14

3

T15

1

T55

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

718

1

T14

3

T55

1

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1013

1

T3

1

T26

2

T54

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

765

1

T3

1

T26

2

T54

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1048

1

T6

1

T14

3

T26

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

805

1

T14

3

T26

3

T54

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1042

1

T14

1

T26

1

T54

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

807

1

T14

1

T26

1

T54

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

994

1

T14

3

T26

2

T54

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

756

1

T14

3

T26

2

T54

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1038

1

T6

1

T14

3

T26

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

808

1

T6

1

T14

3

T26

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1054

1

T14

1

T26

1

T16

11

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

798

1

T14

1

T26

1

T16

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

952

1

T14

1

T26

3

T54

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

731

1

T14

1

T26

3

T54

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1033

1

T14

1

T54

1

T39

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

791

1

T14

1

T39

1

T16

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1014

1

T3

1

T14

2

T26

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

814

1

T3

1

T14

2

T26

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1017

1

T14

3

T26

3

T54

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

770

1

T14

3

T26

3

T39

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1022

1

T15

4

T26

2

T39

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

777

1

T26

2

T39

2

T60

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1034

1

T3

1

T26

1

T54

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

794

1

T3

1

T26

1

T54

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

971

1

T3

1

T14

3

T15

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

769

1

T3

1

T14

3

T26

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

960

1

T14

1

T15

1

T26

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

734

1

T14

1

T26

1

T55

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1005

1

T8

2

T26

2

T54

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

786

1

T26

2

T54

1

T16

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1004

1

T14

4

T26

1

T55

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

767

1

T14

4

T26

1

T55

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1035

1

T15

1

T26

1

T54

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

802

1

T26

1

T54

2

T55

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1046

1

T14

1

T26

3

T44

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

825

1

T14

1

T26

3

T55

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

994

1

T3

1

T14

2

T26

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

767

1

T3

1

T14

2

T26

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1020

1

T14

2

T26

2

T54

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

784

1

T14

2

T26

2

T78

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1048

1

T14

2

T55

1

T16

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

816

1

T14

2

T55

1

T16

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1064

1

T6

1

T14

2

T44

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

805

1

T14

2

T44

1

T78

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1039

1

T8

1

T14

3

T15

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

813

1

T8

1

T14

3

T26

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1056

1

T14

1

T26

3

T44

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

802

1

T14

1

T26

3

T55

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1064

1

T14

1

T26

1

T54

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

827

1

T14

1

T26

1

T54

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

942

1

T8

1

T26

2

T39

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

732

1

T8

1

T26

2

T39

1