Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30387 1 T1 2 T2 58 T4 310
auto[1] 29935 1 T2 42 T4 310 T10 14


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30742 1 T1 2 T2 48 T4 349
auto[1] 29580 1 T2 52 T4 271 T10 12


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29724 1 T1 1 T2 56 T4 276
auto[1] 30598 1 T1 1 T2 44 T4 344


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33579 1 T1 2 T2 50 T4 358
auto[1] 26743 1 T2 50 T4 262 T10 10


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29593 1 T1 1 T2 38 T4 285
auto[1] 30729 1 T1 1 T2 62 T4 335


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31157 1 T1 2 T2 42 T4 271
auto[1] 29165 1 T2 58 T4 349 T10 10


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1006 1 T2 2 T4 6 T14 17
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 821 1 T2 2 T4 4 T14 13
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1041 1 T1 1 T2 1 T4 12
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 832 1 T2 1 T4 8 T14 8
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1003 1 T1 1 T2 2 T4 12
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 808 1 T2 2 T4 9 T14 15
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1744 1 T4 17 T14 30 T62 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1536 1 T4 15 T14 28 T62 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 994 1 T2 1 T4 19 T14 12
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 791 1 T2 1 T4 13 T14 8
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 949 1 T2 1 T4 14 T14 18
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 750 1 T2 1 T4 13 T14 14
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 973 1 T2 3 T4 12 T14 14
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 756 1 T2 3 T4 9 T14 9
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 977 1 T2 3 T4 16 T14 13
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 773 1 T2 3 T4 14 T14 11
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1039 1 T2 2 T4 4 T10 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 798 1 T2 2 T4 2 T10 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1005 1 T2 1 T4 8 T14 17
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 797 1 T2 1 T4 5 T14 15
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1020 1 T2 1 T4 8 T14 15
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 829 1 T2 1 T4 7 T14 11
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 996 1 T2 1 T4 8 T14 17
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 785 1 T2 1 T4 6 T14 14
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1056 1 T2 1 T4 9 T10 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 831 1 T2 1 T4 6 T10 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1028 1 T2 4 T4 10 T37 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 818 1 T2 4 T4 6 T37 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1031 1 T2 3 T4 7 T10 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 812 1 T2 3 T4 4 T10 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1011 1 T2 3 T4 15 T14 13
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 777 1 T2 3 T4 12 T14 10
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1054 1 T2 2 T4 14 T10 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 837 1 T2 2 T4 12 T10 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1090 1 T4 16 T41 1 T14 24
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 891 1 T4 9 T41 1 T14 17
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1031 1 T2 2 T4 9 T14 21
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 816 1 T2 2 T4 5 T14 15
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1024 1 T4 5 T10 2 T14 19
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 825 1 T4 3 T10 2 T14 14
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1014 1 T2 1 T4 8 T14 10
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 800 1 T2 1 T4 6 T14 8
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1008 1 T2 2 T4 9 T41 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 803 1 T2 2 T4 7 T41 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1076 1 T2 1 T4 13 T10 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 872 1 T2 1 T4 11 T10 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1042 1 T2 3 T4 18 T14 17
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 805 1 T2 3 T4 11 T14 11
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1067 1 T2 1 T4 8 T37 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 852 1 T2 1 T4 4 T14 5
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1031 1 T4 10 T14 17 T22 3
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 814 1 T4 9 T14 14 T22 3
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1115 1 T2 3 T4 10 T10 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 886 1 T2 3 T4 6 T10 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 995 1 T2 3 T4 13 T14 22
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 769 1 T2 3 T4 7 T14 16
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1050 1 T4 9 T14 9 T33 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 810 1 T4 7 T14 6 T33 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1076 1 T4 10 T14 14 T22 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 840 1 T4 8 T14 8 T22 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1042 1 T2 3 T4 12 T10 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 834 1 T2 3 T4 11 T10 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 991 1 T4 17 T10 1 T37 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 775 1 T4 13 T10 1 T14 7

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