Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34621

1

T1

60

T2

388

T3

2

auto[1]

33558

1

T1

40

T2

355

T4

46

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34838

1

T1

52

T2

367

T3

2

auto[1]

33341

1

T1

48

T2

376

T4

48

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33255

1

T1

40

T2

341

T4

40

auto[1]

34924

1

T1

60

T2

402

T3

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38378

1

T1

50

T2

382

T3

1

auto[1]

29801

1

T1

50

T2

361

T3

1

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33359

1

T1

52

T2

373

T4

48

auto[1]

34820

1

T1

48

T2

370

T3

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34907

1

T1

48

T2

407

T3

2

auto[1]

33272

1

T1

52

T2

336

T4

54

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1179

1

T1

5

T2

16

T4

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

911

1

T1

5

T2

14

T4

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1165

1

T1

3

T2

9

T4

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

896

1

T1

3

T2

7

T4

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1159

1

T1

2

T2

18

T15

30

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

883

1

T1

2

T2

16

T15

24

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1877

1

T1

1

T2

17

T3

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1613

1

T1

1

T2

17

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1130

1

T1

2

T2

8

T15

18

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

896

1

T1

2

T2

8

T15

14

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1139

1

T2

11

T4

2

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

872

1

T2

11

T4

2

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1212

1

T1

2

T2

11

T4

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

925

1

T1

2

T2

11

T4

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1176

1

T1

3

T2

8

T4

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

913

1

T1

3

T2

6

T4

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1188

1

T1

1

T2

16

T4

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

919

1

T1

1

T2

15

T4

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1203

1

T1

3

T2

14

T15

24

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

918

1

T1

3

T2

12

T15

19

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1149

1

T2

11

T4

1

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

893

1

T2

11

T4

1

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1224

1

T1

2

T2

15

T4

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

924

1

T1

2

T2

14

T4

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1104

1

T2

10

T4

3

T15

30

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

861

1

T2

10

T4

3

T15

19

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1202

1

T2

11

T4

2

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

917

1

T2

10

T4

2

T15

12

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1153

1

T1

2

T2

8

T4

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

901

1

T1

2

T2

7

T4

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1187

1

T1

4

T2

18

T4

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

932

1

T1

4

T2

18

T4

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1190

1

T2

9

T4

2

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

908

1

T2

7

T4

2

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1179

1

T2

12

T4

4

T15

23

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

900

1

T2

12

T4

4

T15

14

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1177

1

T1

1

T2

7

T4

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

916

1

T1

1

T2

7

T4

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1207

1

T2

17

T6

1

T15

21

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

941

1

T2

17

T15

15

T37

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1210

1

T1

1

T2

12

T6

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

965

1

T1

1

T2

12

T6

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1146

1

T1

4

T2

15

T61

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

860

1

T1

4

T2

15

T61

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1200

1

T2

6

T4

3

T6

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

934

1

T2

5

T4

3

T6

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1211

1

T1

2

T2

13

T4

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

948

1

T1

2

T2

13

T4

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1226

1

T1

3

T2

13

T4

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

949

1

T1

3

T2

13

T4

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1214

1

T1

1

T2

15

T4

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

951

1

T1

1

T2

15

T4

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1156

1

T2

10

T6

3

T15

25

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

890

1

T2

9

T6

3

T15

17

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1142

1

T1

2

T2

12

T4

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

860

1

T1

2

T2

10

T4

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1161

1

T2

10

T4

1

T15

25

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

888

1

T2

9

T4

1

T15

16

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1190

1

T1

3

T2

11

T4

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

922

1

T1

3

T2

11

T4

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1146

1

T1

1

T2

11

T4

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

876

1

T1

1

T2

11

T4

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1176

1

T1

2

T2

8

T4

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

919

1

T1

2

T2

8

T4

1