Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31853

1

T2

40

T3

42

T4

155

auto[1]

30827

1

T2

60

T3

58

T4

113

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32422

1

T2

62

T3

50

T4

134

auto[1]

30258

1

T2

38

T3

50

T4

134

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30727

1

T2

52

T3

56

T4

138

auto[1]

31953

1

T2

48

T3

44

T4

130

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35465

1

T2

50

T3

50

T4

153

auto[1]

27215

1

T2

50

T3

50

T4

115

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30925

1

T2

48

T3

66

T4

131

auto[1]

31755

1

T2

52

T3

34

T4

137

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31746

1

T2

46

T3

54

T4

152

auto[1]

30934

1

T2

54

T3

46

T4

116

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1112

1

T2

2

T3

3

T4

8

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

857

1

T2

2

T3

3

T4

6

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1085

1

T4

5

T6

2

T8

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

830

1

T4

2

T6

2

T8

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1132

1

T2

1

T3

1

T4

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

876

1

T2

1

T3

1

T4

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1779

1

T2

1

T3

2

T4

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1528

1

T2

1

T3

2

T4

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1090

1

T2

3

T3

2

T4

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

851

1

T2

3

T3

2

T4

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1094

1

T3

3

T4

5

T6

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

835

1

T3

3

T4

2

T6

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1050

1

T2

2

T4

5

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

836

1

T2

2

T4

5

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1079

1

T4

2

T8

2

T52

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

840

1

T4

2

T8

2

T52

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1057

1

T3

2

T4

8

T8

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

818

1

T3

2

T4

6

T8

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1071

1

T2

1

T3

1

T4

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

830

1

T2

1

T3

1

T4

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1058

1

T2

2

T4

4

T6

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

800

1

T2

2

T4

3

T6

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1022

1

T2

1

T4

2

T6

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

764

1

T2

1

T4

1

T6

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1076

1

T2

2

T3

2

T4

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

813

1

T2

2

T3

2

T4

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1071

1

T2

1

T3

3

T4

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

798

1

T2

1

T3

3

T4

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1114

1

T3

2

T4

7

T6

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

843

1

T3

2

T4

6

T6

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1047

1

T2

4

T4

7

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

797

1

T2

4

T4

6

T8

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1082

1

T2

1

T3

2

T4

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

817

1

T2

1

T3

2

T4

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1124

1

T2

4

T3

2

T4

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

873

1

T2

4

T3

2

T4

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1024

1

T2

4

T3

1

T4

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

761

1

T2

4

T3

1

T4

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1083

1

T2

4

T3

2

T4

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

838

1

T2

4

T3

2

T4

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1168

1

T2

3

T3

3

T4

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

890

1

T2

3

T3

3

T4

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1142

1

T2

2

T3

1

T4

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

867

1

T2

2

T3

1

T4

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1095

1

T2

3

T3

1

T4

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

829

1

T2

3

T3

1

T4

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1104

1

T2

1

T3

2

T4

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

851

1

T2

1

T3

2

T4

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1066

1

T3

4

T4

3

T6

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

795

1

T3

4

T4

1

T6

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1083

1

T2

1

T3

3

T4

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

793

1

T2

1

T3

3

T4

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1100

1

T3

3

T4

6

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

822

1

T3

3

T4

5

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1063

1

T2

1

T3

1

T4

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

803

1

T2

1

T3

1

T4

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1104

1

T2

2

T3

2

T4

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

850

1

T2

2

T3

2

T4

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1125

1

T2

2

T4

4

T52

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

858

1

T2

2

T4

3

T52

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1101

1

T2

1

T4

6

T6

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

840

1

T2

1

T4

2

T6

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1064

1

T2

1

T3

2

T4

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

812

1

T2

1

T3

2

T4

2