Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31283

1

T1

2

T2

2

T3

50

auto[1]

29973

1

T2

4

T3

50

T9

4

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31310

1

T1

2

T2

5

T3

48

auto[1]

29946

1

T2

1

T3

52

T9

3

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29765

1

T2

4

T3

40

T9

3

auto[1]

31491

1

T1

2

T2

2

T3

60

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34482

1

T1

1

T2

4

T3

50

auto[1]

26774

1

T1

1

T2

2

T3

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29675

1

T2

5

T3

46

T9

5

auto[1]

31581

1

T1

2

T2

1

T3

54

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31244

1

T1

2

T2

4

T3

42

auto[1]

30012

1

T2

2

T3

58

T9

3

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1079

1

T2

1

T3

2

T10

8

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

856

1

T2

1

T3

2

T10

8

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1077

1

T9

1

T10

12

T14

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

830

1

T10

8

T14

1

T37

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1006

1

T3

1

T10

10

T14

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

764

1

T3

1

T10

8

T14

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1795

1

T1

1

T3

1

T4

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1530

1

T1

1

T3

1

T4

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1004

1

T3

1

T10

6

T37

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

748

1

T3

1

T10

5

T37

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1038

1

T3

1

T10

15

T37

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

796

1

T3

1

T10

11

T37

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1061

1

T3

3

T10

15

T14

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

839

1

T3

3

T10

9

T14

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1092

1

T3

2

T10

10

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

855

1

T3

2

T10

8

T40

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1075

1

T3

1

T10

13

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

823

1

T3

1

T10

12

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1113

1

T3

2

T10

7

T39

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

864

1

T3

2

T10

7

T39

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1027

1

T3

1

T10

11

T15

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

794

1

T3

1

T10

7

T16

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1004

1

T3

1

T10

6

T40

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

792

1

T3

1

T10

4

T40

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1056

1

T3

1

T10

15

T40

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

817

1

T3

1

T10

13

T40

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1039

1

T3

3

T10

11

T40

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

784

1

T3

3

T10

9

T40

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1026

1

T9

1

T10

12

T14

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

821

1

T10

9

T14

1

T39

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1058

1

T3

5

T10

15

T14

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

820

1

T3

5

T10

14

T14

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

972

1

T3

1

T9

1

T10

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

742

1

T3

1

T9

1

T10

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1014

1

T3

2

T10

12

T16

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

782

1

T3

2

T10

10

T16

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1096

1

T2

1

T3

1

T10

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

870

1

T3

1

T10

6

T40

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1027

1

T3

2

T10

11

T14

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

791

1

T3

2

T10

8

T14

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1060

1

T3

1

T10

6

T37

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

808

1

T3

1

T10

6

T37

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1079

1

T2

1

T3

3

T10

9

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

835

1

T2

1

T3

3

T10

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1095

1

T10

9

T37

1

T40

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

829

1

T10

8

T37

1

T40

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1099

1

T3

3

T10

13

T14

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

841

1

T3

3

T10

8

T14

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1043

1

T2

1

T3

1

T10

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

820

1

T3

1

T10

6

T16

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1030

1

T3

2

T10

13

T15

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

776

1

T3

2

T10

8

T16

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1068

1

T3

2

T10

8

T14

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

822

1

T3

2

T10

6

T14

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1120

1

T3

1

T10

10

T40

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

842

1

T3

1

T10

6

T40

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1016

1

T3

1

T10

12

T37

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

795

1

T3

1

T10

11

T37

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1066

1

T3

1

T9

1

T10

11

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

838

1

T3

1

T9

1

T10

9

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1087

1

T3

3

T10

6

T37

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

846

1

T3

3

T10

5

T37

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1060

1

T3

1

T10

7

T37

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

804

1

T3

1

T10

6

T37

1