Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30402

1

T2

8

T5

2

T8

22

auto[1]

29236

1

T2

18

T8

12

T9

232

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30686

1

T2

16

T5

2

T8

14

auto[1]

28952

1

T2

10

T8

20

T9

239

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29091

1

T2

12

T8

14

T9

234

auto[1]

30547

1

T2

14

T5

2

T8

20

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33635

1

T2

13

T5

1

T8

17

auto[1]

26003

1

T2

13

T5

1

T8

17

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28885

1

T2

12

T8

16

T9

196

auto[1]

30753

1

T2

14

T5

2

T8

18

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30741

1

T2

16

T5

2

T8

14

auto[1]

28897

1

T2

10

T8

20

T9

219

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

999

1

T2

1

T9

11

T24

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

785

1

T2

1

T9

8

T24

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1037

1

T2

2

T8

1

T9

7

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

790

1

T2

2

T8

1

T9

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1056

1

T8

1

T9

7

T24

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

820

1

T8

1

T9

4

T24

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1774

1

T5

1

T9

17

T24

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1532

1

T5

1

T9

15

T24

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1007

1

T8

1

T9

4

T58

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

759

1

T8

1

T9

4

T58

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1032

1

T9

6

T24

2

T58

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

789

1

T9

5

T24

2

T58

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1047

1

T8

1

T9

9

T24

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

803

1

T8

1

T9

4

T24

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1041

1

T8

1

T9

6

T58

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

796

1

T8

1

T9

1

T58

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

988

1

T8

1

T9

5

T21

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

756

1

T8

1

T9

2

T21

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

948

1

T9

7

T24

1

T58

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

729

1

T9

5

T24

1

T21

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1046

1

T2

1

T8

2

T9

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

813

1

T2

1

T8

2

T9

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1038

1

T9

11

T24

4

T58

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

798

1

T9

8

T24

4

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1042

1

T9

13

T24

1

T14

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

775

1

T9

3

T24

1

T14

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1019

1

T8

1

T9

10

T58

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

802

1

T8

1

T9

5

T14

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1026

1

T9

11

T24

4

T21

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

786

1

T9

7

T24

4

T21

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

994

1

T8

2

T9

7

T24

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

775

1

T8

2

T9

4

T24

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1023

1

T9

4

T24

1

T58

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

790

1

T9

4

T24

1

T58

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1064

1

T9

9

T10

2

T24

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

812

1

T9

4

T10

2

T24

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1026

1

T2

1

T9

11

T10

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

815

1

T2

1

T9

5

T10

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1052

1

T9

3

T24

2

T58

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

797

1

T9

3

T24

2

T21

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1007

1

T9

8

T24

1

T14

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

787

1

T9

7

T24

1

T14

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1047

1

T2

1

T8

2

T9

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

806

1

T2

1

T8

2

T9

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

976

1

T2

2

T9

12

T24

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

730

1

T2

2

T9

9

T24

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1068

1

T2

1

T9

11

T24

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

819

1

T2

1

T9

6

T24

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1072

1

T2

1

T9

8

T24

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

833

1

T2

1

T9

5

T24

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1059

1

T2

1

T9

8

T24

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

805

1

T2

1

T9

5

T24

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1064

1

T8

1

T9

14

T58

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

827

1

T8

1

T9

10

T58

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1031

1

T2

1

T8

1

T9

13

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

762

1

T2

1

T8

1

T9

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1007

1

T9

7

T24

1

T58

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

779

1

T9

6

T24

1

T58

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

986

1

T8

2

T9

7

T24

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

751

1

T8

2

T9

6

T24

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1037

1

T9

12

T24

2

T80

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

810

1

T9

7

T24

2

T80

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1022

1

T2

1

T9

9

T24

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

772

1

T2

1

T9

5

T24

1