Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34378

1

T2

58

T3

20

T5

2

auto[1]

32600

1

T2

42

T3

20

T5

8

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34317

1

T2

58

T3

16

T5

4

auto[1]

32661

1

T2

42

T3

24

T5

6

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32938

1

T2

48

T3

20

T5

2

auto[1]

34040

1

T2

52

T3

20

T5

8

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37677

1

T2

50

T3

20

T5

5

auto[1]

29301

1

T2

50

T3

20

T5

5

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32710

1

T2

54

T3

22

T5

4

auto[1]

34268

1

T2

46

T3

18

T5

6

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34117

1

T2

52

T3

26

T5

2

auto[1]

32861

1

T2

48

T3

14

T5

8

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1188

1

T2

3

T3

1

T6

21

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

953

1

T2

3

T3

1

T6

15

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1236

1

T2

3

T3

1

T6

22

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

939

1

T2

3

T3

1

T6

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1245

1

T6

18

T7

3

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

943

1

T6

14

T7

3

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1879

1

T2

8

T3

2

T6

37

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1630

1

T2

8

T3

2

T6

29

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1092

1

T2

1

T6

24

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

861

1

T2

1

T6

22

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1159

1

T2

1

T6

16

T7

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

911

1

T2

1

T6

12

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1109

1

T2

1

T3

1

T6

14

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

857

1

T2

1

T3

1

T6

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1147

1

T6

19

T7

4

T8

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

894

1

T6

14

T7

2

T8

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1109

1

T2

1

T3

2

T6

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

861

1

T2

1

T3

2

T6

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1150

1

T5

1

T6

10

T7

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

888

1

T5

1

T6

6

T7

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1175

1

T6

18

T7

4

T8

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

916

1

T6

15

T7

3

T8

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1100

1

T2

2

T6

22

T7

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

852

1

T2

2

T6

14

T7

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1188

1

T2

5

T6

31

T7

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

935

1

T2

5

T6

23

T7

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1135

1

T2

2

T6

22

T7

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

837

1

T2

2

T6

15

T7

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1159

1

T2

1

T3

2

T6

17

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

894

1

T2

1

T3

2

T6

15

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1199

1

T2

1

T3

1

T6

25

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

937

1

T2

1

T3

1

T6

16

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1090

1

T2

1

T6

16

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

851

1

T2

1

T6

9

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1094

1

T2

2

T3

1

T6

14

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

846

1

T2

2

T3

1

T6

12

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1168

1

T2

3

T6

17

T7

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

898

1

T2

3

T6

11

T7

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1175

1

T6

19

T7

5

T8

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

907

1

T6

17

T7

4

T8

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1178

1

T2

2

T6

12

T7

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

900

1

T2

2

T6

8

T7

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1168

1

T2

1

T3

2

T6

23

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

900

1

T2

1

T3

2

T6

16

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1170

1

T6

16

T7

1

T8

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

891

1

T6

12

T8

2

T9

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1145

1

T2

3

T5

2

T6

14

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

893

1

T2

3

T5

2

T6

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1143

1

T3

2

T6

23

T7

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

896

1

T3

2

T6

15

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1144

1

T2

1

T3

1

T6

15

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

879

1

T2

1

T3

1

T6

10

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1087

1

T2

2

T3

1

T6

19

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

841

1

T2

2

T3

1

T6

14

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1147

1

T3

2

T6

25

T7

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

887

1

T3

2

T6

16

T7

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1251

1

T2

2

T3

1

T5

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

975

1

T2

2

T3

1

T5

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1109

1

T2

2

T6

15

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

844

1

T2

2

T6

11

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1185

1

T2

2

T6

23

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

929

1

T2

2

T6

18

T8

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1153

1

T5

1

T6

18

T7

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

856

1

T5

1

T6

15

T7

3