Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28998

1

T5

54

T8

58

T12

54

auto[1]

27878

1

T5

46

T8

42

T12

46

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29458

1

T5

56

T8

46

T12

48

auto[1]

27418

1

T5

44

T8

54

T12

52

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27988

1

T5

38

T8

40

T12

44

auto[1]

28888

1

T5

62

T8

60

T12

56

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32017

1

T5

50

T8

50

T12

50

auto[1]

24859

1

T5

50

T8

50

T12

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27980

1

T5

44

T8

50

T12

58

auto[1]

28896

1

T5

56

T8

50

T12

42

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29208

1

T5

48

T8

56

T12

50

auto[1]

27668

1

T5

52

T8

44

T12

50

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1015

1

T5

1

T12

1

T13

10

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

776

1

T5

1

T12

1

T13

6

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

968

1

T5

2

T8

3

T12

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

761

1

T5

2

T8

3

T12

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

998

1

T5

1

T8

1

T12

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

770

1

T5

1

T8

1

T12

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1631

1

T5

2

T12

1

T13

30

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1407

1

T5

2

T12

1

T13

29

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

979

1

T5

1

T12

1

T13

20

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

761

1

T5

1

T12

1

T13

14

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1035

1

T5

1

T8

4

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

779

1

T5

1

T8

4

T12

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

983

1

T5

1

T8

2

T12

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

743

1

T5

1

T8

2

T12

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

957

1

T5

5

T8

1

T12

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

739

1

T5

5

T8

1

T12

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

999

1

T5

1

T8

4

T12

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

794

1

T5

1

T8

4

T12

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

980

1

T5

1

T8

4

T12

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

748

1

T5

1

T8

4

T12

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

996

1

T5

2

T8

1

T12

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

778

1

T5

2

T8

1

T12

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

958

1

T5

2

T8

1

T12

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

720

1

T5

2

T8

1

T12

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

969

1

T13

18

T36

2

T14

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

748

1

T13

13

T36

2

T14

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

932

1

T5

1

T8

3

T12

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

715

1

T5

1

T8

3

T12

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

949

1

T5

1

T8

2

T12

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

719

1

T5

1

T8

2

T12

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

970

1

T5

5

T8

3

T12

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

721

1

T5

5

T8

3

T12

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

979

1

T5

2

T8

1

T12

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

756

1

T5

2

T8

1

T12

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1010

1

T5

3

T12

1

T13

17

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

785

1

T5

3

T12

1

T13

15

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

982

1

T5

1

T8

3

T12

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

761

1

T5

1

T8

3

T12

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

963

1

T5

1

T8

3

T13

15

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

754

1

T5

1

T8

3

T13

11

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1008

1

T5

3

T8

1

T12

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

787

1

T5

3

T8

1

T12

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

986

1

T5

1

T8

1

T12

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

781

1

T5

1

T8

1

T12

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1004

1

T5

1

T8

1

T13

17

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

792

1

T5

1

T8

1

T13

15

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1007

1

T5

2

T8

2

T12

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

801

1

T5

2

T8

2

T12

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1032

1

T8

3

T12

3

T13

13

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

803

1

T8

3

T12

3

T13

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1002

1

T5

3

T8

1

T12

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

755

1

T5

3

T8

1

T12

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

942

1

T5

1

T8

1

T12

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

734

1

T5

1

T8

1

T12

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

932

1

T5

1

T8

2

T13

24

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

719

1

T5

1

T8

2

T13

17

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

945

1

T5

2

T12

1

T13

13

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

741

1

T5

2

T12

1

T13

10

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

949

1

T12

1

T13

12

T36

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

702

1

T12

1

T13

9

T36

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

994

1

T5

1

T12

1

T13

17

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

751

1

T5

1

T12

1

T13

11

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

963

1

T5

1

T8

2

T13

11

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

758

1

T5

1

T8

2

T13

7