Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30498

1

T1

2

T3

10

T7

2

auto[1]

29228

1

T3

12

T9

20

T13

26

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30188

1

T1

2

T3

16

T7

2

auto[1]

29538

1

T3

6

T9

14

T13

30

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29560

1

T3

12

T9

20

T13

24

auto[1]

30166

1

T1

2

T3

10

T7

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33548

1

T1

1

T3

11

T7

1

auto[1]

26178

1

T1

1

T3

11

T7

1

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29073

1

T3

10

T9

22

T13

21

auto[1]

30653

1

T1

2

T3

12

T7

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30649

1

T1

2

T3

12

T7

2

auto[1]

29077

1

T3

10

T9

14

T13

23

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

966

1

T9

1

T13

1

T29

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

781

1

T9

1

T13

1

T29

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1022

1

T3

1

T29

3

T18

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

803

1

T3

1

T29

3

T18

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1097

1

T3

1

T13

2

T29

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

833

1

T3

1

T13

2

T29

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1584

1

T1

1

T7

1

T9

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1367

1

T1

1

T7

1

T9

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1041

1

T9

2

T29

2

T18

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

814

1

T9

2

T29

2

T18

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

989

1

T18

3

T19

2

T43

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

745

1

T18

3

T19

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1035

1

T3

1

T13

1

T18

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

810

1

T3

1

T13

1

T18

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

993

1

T29

4

T18

3

T19

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

786

1

T29

4

T18

1

T43

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

995

1

T9

1

T13

2

T29

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

768

1

T9

1

T13

2

T29

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

996

1

T13

2

T29

1

T18

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

768

1

T13

1

T29

1

T18

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1106

1

T3

1

T29

2

T18

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

867

1

T3

1

T29

2

T18

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1036

1

T29

1

T18

5

T19

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

813

1

T29

1

T18

3

T19

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1060

1

T13

1

T18

5

T19

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

820

1

T13

1

T18

3

T19

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1085

1

T3

1

T9

1

T13

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

852

1

T3

1

T9

1

T29

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1026

1

T29

3

T18

6

T19

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

780

1

T29

3

T18

5

T19

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1041

1

T13

1

T29

3

T18

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

819

1

T29

3

T18

7

T20

17

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1059

1

T9

1

T29

2

T18

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

823

1

T9

1

T29

2

T18

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

967

1

T9

1

T13

1

T29

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

735

1

T9

1

T13

1

T29

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1052

1

T3

2

T9

2

T18

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

845

1

T3

2

T9

2

T18

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1026

1

T3

1

T13

2

T29

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

803

1

T3

1

T29

2

T18

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

994

1

T3

1

T13

1

T18

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

775

1

T3

1

T18

3

T19

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1033

1

T3

1

T9

1

T29

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

786

1

T3

1

T9

1

T29

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1061

1

T13

1

T18

5

T19

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

820

1

T13

1

T18

4

T19

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

984

1

T29

1

T18

3

T19

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

759

1

T29

1

T19

1

T43

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1073

1

T9

1

T29

2

T18

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

824

1

T9

1

T29

2

T18

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1018

1

T13

1

T29

4

T18

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

791

1

T29

4

T18

2

T19

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1062

1

T13

1

T18

4

T19

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

823

1

T18

2

T19

2

T20

11

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1096

1

T9

1

T13

2

T29

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

850

1

T9

1

T13

1

T29

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1067

1

T9

2

T13

2

T29

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

813

1

T9

2

T29

3

T18

7

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1028

1

T3

1

T13

2

T18

9

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

782

1

T3

1

T13

1

T18

7

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

935

1

T13

2

T29

2

T18

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

735

1

T13

2

T29

2

T18

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1021

1

T9

1

T13

3

T29

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

788

1

T9

1

T13

2

T29

3