Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33561

1

T6

41

T10

2

T11

603

auto[1]

32886

1

T6

42

T11

696

T39

4

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34227

1

T6

47

T10

2

T11

655

auto[1]

32220

1

T6

36

T11

644

T39

5

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32565

1

T6

37

T11

654

T39

1

auto[1]

33882

1

T6

46

T10

2

T11

645

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37419

1

T6

49

T10

1

T11

684

auto[1]

29028

1

T6

34

T10

1

T11

615

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32806

1

T6

47

T11

643

T39

6

auto[1]

33641

1

T6

36

T10

2

T11

656

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34016

1

T6

38

T10

2

T11

650

auto[1]

32431

1

T6

45

T11

649

T39

4

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1168

1

T6

2

T11

20

T56

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

934

1

T6

1

T11

19

T56

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1133

1

T6

1

T11

13

T56

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

877

1

T6

1

T11

13

T56

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1122

1

T6

1

T11

20

T12

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

859

1

T11

18

T12

3

T21

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1865

1

T6

3

T10

1

T11

31

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1612

1

T6

2

T10

1

T11

29

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1153

1

T6

1

T11

18

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

895

1

T11

15

T12

1

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1150

1

T6

3

T11

19

T56

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

879

1

T6

1

T11

18

T56

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1153

1

T6

2

T11

17

T21

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

876

1

T6

2

T11

16

T21

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1126

1

T11

19

T12

1

T51

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

878

1

T11

18

T12

1

T51

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1107

1

T6

1

T11

21

T21

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

829

1

T11

17

T21

1

T38

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1166

1

T6

1

T11

18

T12

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

904

1

T6

1

T11

16

T38

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1114

1

T6

1

T11

19

T12

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

859

1

T11

16

T12

1

T21

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1136

1

T6

1

T11

24

T12

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

889

1

T6

1

T11

21

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1089

1

T6

2

T11

17

T12

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

852

1

T6

1

T11

14

T12

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1156

1

T6

2

T11

20

T39

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

883

1

T6

2

T11

19

T39

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1070

1

T6

2

T11

26

T12

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

821

1

T6

2

T11

25

T12

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1144

1

T6

2

T11

14

T12

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

862

1

T6

2

T11

13

T12

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1241

1

T6

4

T11

20

T56

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

946

1

T6

3

T11

16

T56

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1103

1

T6

3

T11

22

T39

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

842

1

T6

3

T11

21

T35

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1177

1

T6

1

T11

27

T12

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

883

1

T6

1

T11

21

T80

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1162

1

T6

1

T11

23

T35

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

924

1

T6

1

T11

22

T35

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1160

1

T11

25

T12

1

T35

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

917

1

T11

23

T35

2

T21

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1185

1

T6

3

T11

26

T12

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

911

1

T6

1

T11

21

T12

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1176

1

T6

1

T11

21

T12

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

915

1

T6

1

T11

19

T56

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1129

1

T6

2

T11

23

T12

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

876

1

T6

2

T11

22

T12

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1186

1

T11

23

T39

1

T80

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

930

1

T11

22

T80

1

T21

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1182

1

T6

1

T11

23

T35

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

900

1

T6

1

T11

19

T35

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1181

1

T6

1

T11

26

T56

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

904

1

T6

1

T11

26

T56

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1063

1

T11

12

T56

1

T35

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

818

1

T11

12

T35

3

T21

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1132

1

T6

2

T11

24

T12

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

872

1

T6

2

T11

23

T21

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1206

1

T6

3

T11

30

T39

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

918

1

T6

1

T11

28

T39

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1140

1

T6

1

T11

21

T56

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

904

1

T6

1

T11

19

T56

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1144

1

T6

1

T11

22

T12

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

859

1

T11

14

T12

1

T35

2