Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
reset_cross	6	0	6	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18467

1

T3

2

T6

61

T7

2

auto[1]

27865

1

T3

3

T6

46

T7

11

---

Summary for Variable reset_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for reset_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38839

1

T1

1

T2

1

T3

2

auto[1]

10278

1

T3

3

T6

37

T7

6

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20213

1

T1

1

T2

1

T3

5

auto[1]

28904

1

T6

34

T10

1

T11

615

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Summary for Cross reset_cross

Samples crossed: reset_cp enable_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for reset_cross

Bins

reset_cp

enable_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

4642

1

T6

19

T7

1

T9

1

auto[0]

auto[0]

auto[1]

10324

1

T6

24

T11

179

T35

13

auto[0]

auto[1]

auto[0]

4977

1

T3

2

T6

17

T7

6

auto[0]

auto[1]

auto[1]

16111

1

T6

10

T11

406

T35

7

auto[1]

auto[0]

auto[0]

3501

1

T3

2

T6

18

T7

1

auto[1]

auto[1]

auto[0]

6777

1

T3

1

T6

19

T7

5

User Defined Cross Bins for reset_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal	0	Illegal