Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32308 1 T3 2 T4 4 T5 54
auto[1] 31015 1 T4 4 T5 46 T6 2


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32401 1 T3 2 T4 2 T5 56
auto[1] 30922 1 T4 6 T5 44 T6 8


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30897 1 T5 48 T6 6 T7 48
auto[1] 32426 1 T3 2 T4 8 T5 52


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35692 1 T3 1 T4 4 T5 50
auto[1] 27631 1 T3 1 T4 4 T5 50


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31194 1 T4 4 T5 54 T6 6
auto[1] 32129 1 T3 2 T4 4 T5 46


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32797 1 T3 2 T4 6 T5 52
auto[1] 30526 1 T4 2 T5 48 T6 5


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1111 1 T5 3 T9 3 T36 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 882 1 T5 3 T36 2 T22 18
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1143 1 T5 4 T7 1 T39 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 913 1 T5 4 T7 1 T39 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1063 1 T5 3 T9 1 T43 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 825 1 T5 3 T9 1 T43 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1804 1 T3 1 T5 1 T9 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1559 1 T3 1 T5 1 T43 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1113 1 T6 1 T7 2 T9 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 844 1 T7 2 T9 1 T43 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1050 1 T5 3 T7 1 T9 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 823 1 T5 3 T7 1 T43 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1013 1 T5 3 T7 1 T21 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 770 1 T5 3 T7 1 T21 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1095 1 T5 2 T7 2 T9 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 849 1 T5 2 T7 2 T9 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1125 1 T5 1 T6 2 T7 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 877 1 T5 1 T7 1 T36 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1119 1 T4 1 T5 1 T7 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 855 1 T4 1 T5 1 T7 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1058 1 T6 1 T7 1 T9 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 805 1 T7 1 T36 1 T22 17
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1093 1 T4 1 T5 1 T7 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 831 1 T4 1 T5 1 T7 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1074 1 T5 2 T6 1 T7 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 831 1 T5 2 T7 2 T36 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1082 1 T5 1 T6 1 T7 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 845 1 T5 1 T7 1 T39 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1124 1 T5 1 T7 3 T36 4
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 849 1 T5 1 T7 3 T36 4
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1074 1 T5 1 T6 1 T7 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 809 1 T5 1 T7 2 T21 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1121 1 T5 1 T7 2 T43 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 865 1 T5 1 T7 2 T43 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1123 1 T5 2 T7 1 T9 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 875 1 T5 2 T7 1 T9 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1093 1 T5 2 T7 1 T9 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 845 1 T5 2 T7 1 T9 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1109 1 T4 1 T9 1 T36 4
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 868 1 T4 1 T9 1 T36 4
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1057 1 T5 1 T7 3 T36 2
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 798 1 T5 1 T7 3 T36 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1123 1 T5 1 T7 2 T9 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 864 1 T5 1 T7 2 T9 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1084 1 T5 2 T7 2 T9 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 851 1 T5 2 T7 2 T43 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1044 1 T7 4 T9 1 T43 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 824 1 T7 4 T43 1 T36 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1147 1 T5 1 T7 4 T9 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 873 1 T5 1 T7 4 T22 12
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1070 1 T5 3 T7 1 T9 2
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 812 1 T5 3 T7 1 T9 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1133 1 T5 1 T7 1 T9 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 863 1 T5 1 T7 1 T9 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1100 1 T5 2 T6 1 T7 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 837 1 T5 2 T7 2 T22 17
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1075 1 T6 1 T7 1 T9 3
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 815 1 T7 1 T9 2 T43 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1080 1 T4 1 T5 3 T7 5
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 809 1 T4 1 T5 3 T7 5
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1082 1 T5 3 T9 1 T21 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 831 1 T5 3 T9 1 T21 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1110 1 T5 1 T7 1 T9 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 834 1 T5 1 T7 1 T9 1

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