Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32129

1

T1

24

T3

2

T4

6

auto[1]

30767

1

T1

14

T4

3

T5

2

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31732

1

T1

22

T3

2

T4

5

auto[1]

31164

1

T1

16

T4

4

T5

4

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30577

1

T1

20

T4

4

T5

5

auto[1]

32319

1

T1

18

T3

2

T4

5

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35476

1

T1

19

T3

1

T4

9

auto[1]

27420

1

T1

19

T3

1

T5

2

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30540

1

T1

10

T4

4

T5

2

auto[1]

32356

1

T1

28

T3

2

T4

5

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32197

1

T1

20

T3

2

T4

3

auto[1]

30699

1

T1

18

T4

6

T5

1

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1041

1

T7

1

T9

4

T24

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

809

1

T7

1

T9

4

T24

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1043

1

T7

2

T9

2

T24

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

797

1

T7

2

T9

2

T24

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1103

1

T1

2

T4

1

T5

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

859

1

T1

2

T5

1

T7

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1759

1

T1

2

T3

1

T4

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1517

1

T1

2

T3

1

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1042

1

T7

2

T9

2

T13

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

813

1

T7

2

T9

2

T13

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1108

1

T1

1

T7

1

T9

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

826

1

T1

1

T7

1

T9

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1096

1

T1

3

T4

1

T9

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

832

1

T1

3

T9

1

T24

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1122

1

T7

3

T9

4

T24

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

886

1

T7

3

T9

4

T24

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1100

1

T1

1

T9

3

T24

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

840

1

T1

1

T9

3

T24

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1092

1

T4

1

T7

2

T9

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

842

1

T7

2

T9

4

T13

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1089

1

T1

1

T5

1

T24

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

849

1

T1

1

T5

1

T24

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1141

1

T7

2

T9

1

T24

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

850

1

T7

2

T9

1

T24

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1075

1

T1

1

T7

1

T9

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

826

1

T1

1

T7

1

T9

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1075

1

T7

5

T9

2

T24

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

853

1

T7

5

T9

2

T24

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1050

1

T4

1

T9

2

T24

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

806

1

T9

2

T24

2

T37

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1113

1

T1

1

T4

1

T7

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

875

1

T1

1

T7

2

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1101

1

T7

1

T9

2

T24

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

863

1

T7

1

T9

2

T24

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1073

1

T7

2

T9

2

T24

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

819

1

T7

2

T9

2

T24

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1042

1

T1

1

T7

2

T24

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

796

1

T1

1

T7

2

T24

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1061

1

T1

1

T24

3

T13

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

823

1

T1

1

T24

3

T13

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1013

1

T4

1

T7

2

T24

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

784

1

T7

2

T24

3

T37

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1100

1

T4

1

T9

2

T24

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

864

1

T9

2

T24

1

T37

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1046

1

T7

3

T9

1

T13

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

788

1

T7

3

T9

1

T13

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1088

1

T1

1

T7

2

T9

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

818

1

T1

1

T7

2

T9

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1131

1

T5

1

T7

1

T9

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

866

1

T7

1

T9

2

T24

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1150

1

T1

1

T7

2

T9

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

850

1

T1

1

T7

2

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1114

1

T7

3

T9

2

T13

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

859

1

T7

3

T9

2

T13

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1088

1

T1

1

T7

1

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

830

1

T1

1

T7

1

T9

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1076

1

T1

1

T7

2

T9

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

810

1

T1

1

T7

2

T9

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1052

1

T4

1

T5

1

T7

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

806

1

T7

3

T9

1

T24

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1148

1

T7

1

T9

1

T24

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

910

1

T7

1

T9

1

T24

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1144

1

T1

1

T7

1

T9

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

854

1

T1

1

T7

1

T9

2