Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32153

1

T2

155

T5

54

T6

50

auto[1]

30722

1

T2

179

T5

46

T6

50

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32005

1

T2

160

T5

56

T6

44

auto[1]

30870

1

T2

174

T5

44

T6

56

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31112

1

T2

171

T5

50

T6

46

auto[1]

31763

1

T2

163

T5

50

T6

54

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35565

1

T2

176

T5

50

T6

50

auto[1]

27310

1

T2

158

T5

50

T6

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30934

1

T2

162

T5

52

T6

52

auto[1]

31941

1

T2

172

T5

48

T6

48

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32127

1

T2

183

T5

42

T6

54

auto[1]

30748

1

T2

151

T5

58

T6

46

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1118

1

T2

5

T5

2

T6

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

875

1

T2

4

T5

2

T6

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1099

1

T2

3

T5

1

T6

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

840

1

T2

3

T5

1

T6

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1125

1

T2

2

T6

1

T7

20

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

839

1

T2

2

T6

1

T7

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1766

1

T2

10

T6

3

T7

53

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1506

1

T2

9

T6

3

T7

41

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1105

1

T2

5

T5

1

T7

27

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

836

1

T2

4

T5

1

T7

14

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1086

1

T2

4

T5

3

T6

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

822

1

T2

4

T5

3

T6

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1081

1

T2

3

T5

4

T7

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

811

1

T2

3

T5

4

T7

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1086

1

T2

5

T5

2

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

858

1

T2

5

T5

2

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1134

1

T2

5

T5

2

T6

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

859

1

T2

4

T5

2

T6

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1076

1

T2

7

T5

2

T6

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

821

1

T2

7

T5

2

T6

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1055

1

T2

9

T5

1

T6

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

826

1

T2

7

T5

1

T6

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1088

1

T2

3

T5

5

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

821

1

T2

3

T5

5

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1064

1

T2

3

T7

14

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

816

1

T2

3

T7

12

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1083

1

T2

6

T5

1

T6

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

810

1

T2

5

T5

1

T6

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1110

1

T2

6

T6

1

T7

22

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

849

1

T2

6

T6

1

T7

13

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1085

1

T2

5

T5

3

T6

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

803

1

T2

5

T5

3

T6

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1061

1

T2

5

T5

3

T7

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

817

1

T2

4

T5

3

T7

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1092

1

T2

8

T5

1

T6

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

836

1

T2

7

T5

1

T6

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1070

1

T2

9

T6

1

T7

19

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

836

1

T2

8

T6

1

T7

15

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1014

1

T2

5

T5

1

T6

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

770

1

T2

5

T5

1

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1135

1

T2

5

T5

5

T6

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

884

1

T2

4

T5

5

T6

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1086

1

T2

7

T5

2

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

826

1

T2

6

T5

2

T6

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1058

1

T2

6

T5

3

T6

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

800

1

T2

6

T5

3

T6

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1058

1

T2

2

T7

19

T8

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

809

1

T2

2

T7

12

T8

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1124

1

T2

8

T5

1

T6

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

854

1

T2

7

T5

1

T6

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1105

1

T2

5

T5

1

T6

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

809

1

T2

4

T5

1

T6

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1145

1

T2

7

T6

2

T7

23

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

888

1

T2

7

T6

2

T7

16

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1057

1

T2

6

T5

1

T6

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

801

1

T2

5

T5

1

T6

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1111

1

T2

5

T5

1

T6

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

862

1

T2

5

T5

1

T6

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1072

1

T2

6

T6

1

T7

12

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

816

1

T2

4

T6

1

T7

7

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1109

1

T2

7

T5

2

T6

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

855

1

T2

7

T5

2

T6

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1107

1

T2

4

T5

2

T6

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

855

1

T2

3

T5

2

T6

3