Summary for Variable core_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for core_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34149 |
1 |
|
|
T2 |
60 |
|
T4 |
40 |
|
T5 |
8 |
auto[1] |
32394 |
1 |
|
|
T2 |
40 |
|
T4 |
30 |
|
T5 |
6 |
Summary for Variable io_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for io_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34026 |
1 |
|
|
T2 |
44 |
|
T4 |
24 |
|
T5 |
2 |
auto[1] |
32517 |
1 |
|
|
T2 |
56 |
|
T4 |
46 |
|
T5 |
12 |
Summary for Variable main_pd_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for main_pd_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
32325 |
1 |
|
|
T2 |
48 |
|
T4 |
36 |
|
T5 |
6 |
auto[1] |
34218 |
1 |
|
|
T2 |
52 |
|
T4 |
34 |
|
T5 |
8 |
Summary for Variable sleep_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sleep_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37271 |
1 |
|
|
T2 |
50 |
|
T4 |
41 |
|
T5 |
7 |
auto[1] |
29272 |
1 |
|
|
T2 |
50 |
|
T4 |
29 |
|
T5 |
7 |
Summary for Variable usb_active_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for usb_active_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
32677 |
1 |
|
|
T2 |
48 |
|
T4 |
37 |
|
T5 |
10 |
auto[1] |
33866 |
1 |
|
|
T2 |
52 |
|
T4 |
33 |
|
T5 |
4 |
Summary for Variable usb_lp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for usb_lp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34317 |
1 |
|
|
T2 |
46 |
|
T4 |
44 |
|
T5 |
8 |
auto[1] |
32226 |
1 |
|
|
T2 |
54 |
|
T4 |
26 |
|
T5 |
6 |
Summary for Cross control_cross
Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
64 |
0 |
64 |
100.00 |
|
Automatically Generated Cross Bins for control_cross
Bins
core_cp | io_cp | usb_lp_cp | usb_active_cp | main_pd_n_cp | sleep_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
1145 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T7 |
1 |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
891 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T7 |
1 |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
1171 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T5 |
1 |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
920 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T5 |
1 |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
1182 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T6 |
2 |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
899 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T6 |
2 |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
1821 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T6 |
1 |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
1581 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T6 |
1 |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
1131 |
1 |
|
|
T4 |
1 |
|
T6 |
2 |
|
T10 |
1 |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
868 |
1 |
|
|
T6 |
2 |
|
T24 |
1 |
|
T83 |
1 |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
1172 |
1 |
|
|
T2 |
1 |
|
T7 |
4 |
|
T24 |
2 |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
917 |
1 |
|
|
T2 |
1 |
|
T7 |
4 |
|
T24 |
2 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
1088 |
1 |
|
|
T2 |
1 |
|
T6 |
2 |
|
T24 |
3 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
840 |
1 |
|
|
T2 |
1 |
|
T6 |
2 |
|
T24 |
3 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
1141 |
1 |
|
|
T2 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
904 |
1 |
|
|
T2 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
1125 |
1 |
|
|
T2 |
2 |
|
T4 |
6 |
|
T7 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
900 |
1 |
|
|
T2 |
2 |
|
T4 |
4 |
|
T7 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
1196 |
1 |
|
|
T2 |
3 |
|
T4 |
1 |
|
T6 |
1 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
934 |
1 |
|
|
T2 |
3 |
|
T6 |
1 |
|
T7 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
1176 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T6 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
921 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T6 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
1167 |
1 |
|
|
T2 |
3 |
|
T4 |
1 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
917 |
1 |
|
|
T2 |
3 |
|
T4 |
1 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
1144 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
898 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
1119 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T6 |
2 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
860 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T6 |
2 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
1115 |
1 |
|
|
T2 |
4 |
|
T4 |
2 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
860 |
1 |
|
|
T2 |
4 |
|
T4 |
1 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
1214 |
1 |
|
|
T2 |
2 |
|
T4 |
3 |
|
T6 |
2 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
932 |
1 |
|
|
T2 |
2 |
|
T4 |
3 |
|
T6 |
2 |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
1130 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T24 |
1 |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
893 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T24 |
1 |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
1157 |
1 |
|
|
T2 |
2 |
|
T6 |
4 |
|
T7 |
1 |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
947 |
1 |
|
|
T2 |
2 |
|
T6 |
4 |
|
T7 |
1 |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
1095 |
1 |
|
|
T6 |
2 |
|
T7 |
4 |
|
T24 |
4 |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
853 |
1 |
|
|
T6 |
2 |
|
T7 |
4 |
|
T24 |
4 |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
1203 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
1 |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
927 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
1 |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
1165 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
922 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
1113 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T6 |
3 |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
901 |
1 |
|
|
T2 |
2 |
|
T6 |
3 |
|
T38 |
1 |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
1132 |
1 |
|
|
T2 |
2 |
|
T6 |
1 |
|
T24 |
2 |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
870 |
1 |
|
|
T2 |
2 |
|
T6 |
1 |
|
T24 |
2 |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
1141 |
1 |
|
|
T2 |
4 |
|
T4 |
4 |
|
T6 |
3 |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
906 |
1 |
|
|
T2 |
4 |
|
T4 |
3 |
|
T6 |
3 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
1173 |
1 |
|
|
T2 |
1 |
|
T4 |
5 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
924 |
1 |
|
|
T2 |
1 |
|
T4 |
3 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
1159 |
1 |
|
|
T2 |
2 |
|
T4 |
3 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
876 |
1 |
|
|
T2 |
2 |
|
T4 |
2 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
1140 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
910 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
2 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
1122 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
2 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
862 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
2 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
1093 |
1 |
|
|
T2 |
2 |
|
T6 |
4 |
|
T7 |
2 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
858 |
1 |
|
|
T2 |
2 |
|
T6 |
4 |
|
T7 |
2 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
1109 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T7 |
1 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
866 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T7 |
1 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
1121 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T6 |
1 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
863 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T6 |
1 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
1111 |
1 |
|
|
T7 |
3 |
|
T24 |
3 |
|
T39 |
4 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
852 |
1 |
|
|
T7 |
3 |
|
T24 |
3 |
|
T39 |
2 |