Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02


Total test records in report: 1119
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T1014 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.4124506280 Jul 05 05:59:01 PM PDT 24 Jul 05 05:59:06 PM PDT 24 36356528 ps
T1015 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4052012557 Jul 05 05:59:22 PM PDT 24 Jul 05 05:59:23 PM PDT 24 18111558 ps
T1016 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.785170994 Jul 05 05:58:55 PM PDT 24 Jul 05 05:58:59 PM PDT 24 52662740 ps
T147 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.32766201 Jul 05 05:58:56 PM PDT 24 Jul 05 05:58:59 PM PDT 24 74947298 ps
T132 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2662574510 Jul 05 05:59:22 PM PDT 24 Jul 05 05:59:22 PM PDT 24 25934660 ps
T1017 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3378381467 Jul 05 05:59:11 PM PDT 24 Jul 05 05:59:12 PM PDT 24 23655212 ps
T1018 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2956534244 Jul 05 05:58:53 PM PDT 24 Jul 05 05:58:56 PM PDT 24 30765111 ps
T1019 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3755725195 Jul 05 05:59:17 PM PDT 24 Jul 05 05:59:18 PM PDT 24 23106820 ps
T1020 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1175601349 Jul 05 05:58:57 PM PDT 24 Jul 05 05:59:01 PM PDT 24 179834335 ps
T1021 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3379628288 Jul 05 05:59:10 PM PDT 24 Jul 05 05:59:11 PM PDT 24 27870654 ps
T1022 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3163250579 Jul 05 05:59:20 PM PDT 24 Jul 05 05:59:21 PM PDT 24 40683623 ps
T1023 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1452403505 Jul 05 05:59:05 PM PDT 24 Jul 05 05:59:07 PM PDT 24 34092006 ps
T1024 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.2263250452 Jul 05 05:58:50 PM PDT 24 Jul 05 05:58:53 PM PDT 24 111777850 ps
T133 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2575761369 Jul 05 05:58:55 PM PDT 24 Jul 05 05:58:58 PM PDT 24 41675870 ps
T134 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1118661599 Jul 05 05:58:52 PM PDT 24 Jul 05 05:58:53 PM PDT 24 161938500 ps
T1025 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1487939796 Jul 05 05:59:13 PM PDT 24 Jul 05 05:59:14 PM PDT 24 16792387 ps
T1026 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2948555415 Jul 05 05:59:09 PM PDT 24 Jul 05 05:59:10 PM PDT 24 26784053 ps
T1027 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.643254217 Jul 05 05:58:53 PM PDT 24 Jul 05 05:58:55 PM PDT 24 39888831 ps
T1028 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2881986547 Jul 05 05:58:55 PM PDT 24 Jul 05 05:58:58 PM PDT 24 211508586 ps
T1029 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.3705803232 Jul 05 05:59:03 PM PDT 24 Jul 05 05:59:06 PM PDT 24 78930049 ps
T1030 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.902986287 Jul 05 05:58:56 PM PDT 24 Jul 05 05:58:59 PM PDT 24 32006757 ps
T1031 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.3898484485 Jul 05 05:59:10 PM PDT 24 Jul 05 05:59:11 PM PDT 24 56074334 ps
T135 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1979539199 Jul 05 05:59:03 PM PDT 24 Jul 05 05:59:06 PM PDT 24 28215285 ps
T1032 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.727860275 Jul 05 05:58:56 PM PDT 24 Jul 05 05:59:00 PM PDT 24 23720446 ps
T1033 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2724818883 Jul 05 05:59:13 PM PDT 24 Jul 05 05:59:15 PM PDT 24 156580312 ps
T1034 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1880572357 Jul 05 05:59:04 PM PDT 24 Jul 05 05:59:08 PM PDT 24 360293898 ps
T1035 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.84084740 Jul 05 05:58:58 PM PDT 24 Jul 05 05:59:03 PM PDT 24 90897024 ps
T1036 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3888717197 Jul 05 05:58:57 PM PDT 24 Jul 05 05:59:02 PM PDT 24 28981945 ps
T1037 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.3612511251 Jul 05 05:59:12 PM PDT 24 Jul 05 05:59:13 PM PDT 24 17554783 ps
T1038 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.19794708 Jul 05 05:59:03 PM PDT 24 Jul 05 05:59:06 PM PDT 24 119059901 ps
T1039 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3306475654 Jul 05 05:59:15 PM PDT 24 Jul 05 05:59:16 PM PDT 24 41985572 ps
T1040 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1197052627 Jul 05 05:59:04 PM PDT 24 Jul 05 05:59:07 PM PDT 24 140408245 ps
T1041 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2064981994 Jul 05 05:59:20 PM PDT 24 Jul 05 05:59:26 PM PDT 24 20321392 ps
T1042 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.298063160 Jul 05 05:59:32 PM PDT 24 Jul 05 05:59:34 PM PDT 24 81316773 ps
T1043 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3094076199 Jul 05 05:59:24 PM PDT 24 Jul 05 05:59:26 PM PDT 24 211680436 ps
T1044 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1850876921 Jul 05 05:58:57 PM PDT 24 Jul 05 05:59:02 PM PDT 24 42259065 ps
T1045 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3935586952 Jul 05 05:58:59 PM PDT 24 Jul 05 05:59:04 PM PDT 24 162270477 ps
T1046 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.912653649 Jul 05 05:59:14 PM PDT 24 Jul 05 05:59:15 PM PDT 24 46951955 ps
T1047 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1120468693 Jul 05 05:59:04 PM PDT 24 Jul 05 05:59:07 PM PDT 24 156888812 ps
T1048 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1397193872 Jul 05 05:58:57 PM PDT 24 Jul 05 05:59:01 PM PDT 24 39569088 ps
T136 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2426756967 Jul 05 05:58:57 PM PDT 24 Jul 05 05:59:02 PM PDT 24 63631710 ps
T1049 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1679548620 Jul 05 05:59:25 PM PDT 24 Jul 05 05:59:26 PM PDT 24 66077656 ps
T1050 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1245315887 Jul 05 05:58:56 PM PDT 24 Jul 05 05:59:02 PM PDT 24 406187934 ps
T1051 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3335542581 Jul 05 05:59:19 PM PDT 24 Jul 05 05:59:21 PM PDT 24 28198110 ps
T1052 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3590573927 Jul 05 05:58:59 PM PDT 24 Jul 05 05:59:04 PM PDT 24 80025854 ps
T1053 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3588751830 Jul 05 05:59:01 PM PDT 24 Jul 05 05:59:05 PM PDT 24 49029631 ps
T1054 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3312969457 Jul 05 05:59:16 PM PDT 24 Jul 05 05:59:17 PM PDT 24 49485062 ps
T1055 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.4013783322 Jul 05 05:59:02 PM PDT 24 Jul 05 05:59:05 PM PDT 24 20717331 ps
T1056 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.376890998 Jul 05 05:59:24 PM PDT 24 Jul 05 05:59:25 PM PDT 24 19615257 ps
T1057 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3538293290 Jul 05 05:59:11 PM PDT 24 Jul 05 05:59:12 PM PDT 24 22904607 ps
T1058 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.252689095 Jul 05 05:58:59 PM PDT 24 Jul 05 05:59:05 PM PDT 24 308998672 ps
T1059 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.2566415327 Jul 05 05:59:01 PM PDT 24 Jul 05 05:59:05 PM PDT 24 22240123 ps
T1060 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3163870204 Jul 05 05:59:05 PM PDT 24 Jul 05 05:59:07 PM PDT 24 43871812 ps
T73 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3150860687 Jul 05 05:59:06 PM PDT 24 Jul 05 05:59:09 PM PDT 24 191132233 ps
T182 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2961732084 Jul 05 05:59:19 PM PDT 24 Jul 05 05:59:21 PM PDT 24 412897971 ps
T1061 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1289858556 Jul 05 05:59:14 PM PDT 24 Jul 05 05:59:15 PM PDT 24 17679803 ps
T1062 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.612359465 Jul 05 05:59:01 PM PDT 24 Jul 05 05:59:05 PM PDT 24 22672843 ps
T1063 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2037478746 Jul 05 05:59:20 PM PDT 24 Jul 05 05:59:21 PM PDT 24 131523851 ps
T183 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.259531457 Jul 05 05:58:55 PM PDT 24 Jul 05 05:58:59 PM PDT 24 291054259 ps
T1064 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2235267874 Jul 05 05:59:04 PM PDT 24 Jul 05 05:59:07 PM PDT 24 60233392 ps
T1065 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.801413802 Jul 05 05:58:58 PM PDT 24 Jul 05 05:59:04 PM PDT 24 338910202 ps
T137 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.1877010017 Jul 05 05:58:51 PM PDT 24 Jul 05 05:58:53 PM PDT 24 129086115 ps
T1066 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1024719029 Jul 05 05:58:55 PM PDT 24 Jul 05 05:58:58 PM PDT 24 54749977 ps
T1067 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2863402877 Jul 05 05:58:57 PM PDT 24 Jul 05 05:59:01 PM PDT 24 40641038 ps
T1068 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3146643035 Jul 05 05:58:55 PM PDT 24 Jul 05 05:58:59 PM PDT 24 101586705 ps
T138 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1984720920 Jul 05 05:58:58 PM PDT 24 Jul 05 05:59:03 PM PDT 24 44538636 ps
T1069 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3974671111 Jul 05 05:59:08 PM PDT 24 Jul 05 05:59:09 PM PDT 24 70118983 ps
T1070 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3481462223 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:32 PM PDT 24 21140262 ps
T1071 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.4161251592 Jul 05 05:59:11 PM PDT 24 Jul 05 05:59:13 PM PDT 24 56833454 ps
T1072 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1622491311 Jul 05 05:59:04 PM PDT 24 Jul 05 05:59:07 PM PDT 24 26353356 ps
T1073 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.401021256 Jul 05 05:58:56 PM PDT 24 Jul 05 05:58:59 PM PDT 24 115511795 ps
T1074 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.831252103 Jul 05 05:59:01 PM PDT 24 Jul 05 05:59:05 PM PDT 24 46186105 ps
T1075 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2056308386 Jul 05 05:58:56 PM PDT 24 Jul 05 05:59:01 PM PDT 24 25164553 ps
T1076 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3018822205 Jul 05 05:59:11 PM PDT 24 Jul 05 05:59:13 PM PDT 24 44182233 ps
T1077 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.4294555499 Jul 05 05:59:20 PM PDT 24 Jul 05 05:59:21 PM PDT 24 84831472 ps
T139 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3892057500 Jul 05 05:58:57 PM PDT 24 Jul 05 05:59:01 PM PDT 24 17332475 ps
T1078 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.4162452773 Jul 05 05:59:25 PM PDT 24 Jul 05 05:59:27 PM PDT 24 30891929 ps
T1079 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.160310253 Jul 05 05:59:23 PM PDT 24 Jul 05 05:59:24 PM PDT 24 113285411 ps
T1080 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3405876822 Jul 05 05:59:28 PM PDT 24 Jul 05 05:59:29 PM PDT 24 31108782 ps
T1081 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2896055007 Jul 05 05:58:56 PM PDT 24 Jul 05 05:59:00 PM PDT 24 19782775 ps
T1082 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.1690423309 Jul 05 05:59:02 PM PDT 24 Jul 05 05:59:06 PM PDT 24 26080826 ps
T1083 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3404434215 Jul 05 05:59:01 PM PDT 24 Jul 05 05:59:05 PM PDT 24 46653882 ps
T1084 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1237960497 Jul 05 05:58:56 PM PDT 24 Jul 05 05:59:02 PM PDT 24 128740751 ps
T1085 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.4145400981 Jul 05 05:59:02 PM PDT 24 Jul 05 05:59:06 PM PDT 24 218929694 ps
T1086 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1264682550 Jul 05 05:58:54 PM PDT 24 Jul 05 05:58:57 PM PDT 24 353491970 ps
T1087 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3378818647 Jul 05 05:59:09 PM PDT 24 Jul 05 05:59:10 PM PDT 24 50144378 ps
T140 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2791093305 Jul 05 05:58:56 PM PDT 24 Jul 05 05:59:01 PM PDT 24 44589325 ps
T1088 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.2682822370 Jul 05 05:58:59 PM PDT 24 Jul 05 05:59:04 PM PDT 24 166012058 ps
T1089 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1081436710 Jul 05 05:59:00 PM PDT 24 Jul 05 05:59:05 PM PDT 24 362724901 ps
T1090 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.755792586 Jul 05 05:59:03 PM PDT 24 Jul 05 05:59:06 PM PDT 24 69061680 ps
T1091 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2400801606 Jul 05 05:59:05 PM PDT 24 Jul 05 05:59:08 PM PDT 24 47519650 ps
T1092 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3523022901 Jul 05 05:59:23 PM PDT 24 Jul 05 05:59:24 PM PDT 24 83980003 ps
T1093 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1452885546 Jul 05 05:59:16 PM PDT 24 Jul 05 05:59:17 PM PDT 24 33694644 ps
T1094 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.695264898 Jul 05 05:58:55 PM PDT 24 Jul 05 05:58:58 PM PDT 24 20492527 ps
T1095 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.503637058 Jul 05 05:58:58 PM PDT 24 Jul 05 05:59:02 PM PDT 24 177692964 ps
T1096 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3119403953 Jul 05 05:58:58 PM PDT 24 Jul 05 05:59:03 PM PDT 24 47558099 ps
T1097 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.86639507 Jul 05 05:58:58 PM PDT 24 Jul 05 05:59:03 PM PDT 24 120552881 ps
T1098 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.357949658 Jul 05 05:58:56 PM PDT 24 Jul 05 05:59:00 PM PDT 24 17061443 ps
T1099 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.4135978222 Jul 05 05:59:04 PM PDT 24 Jul 05 05:59:07 PM PDT 24 18299776 ps
T1100 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1686875376 Jul 05 05:58:58 PM PDT 24 Jul 05 05:59:03 PM PDT 24 27974200 ps
T1101 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1895909665 Jul 05 05:58:56 PM PDT 24 Jul 05 05:59:00 PM PDT 24 62969229 ps
T1102 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.4161706535 Jul 05 05:59:25 PM PDT 24 Jul 05 05:59:26 PM PDT 24 34347115 ps
T1103 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1373685163 Jul 05 05:59:04 PM PDT 24 Jul 05 05:59:07 PM PDT 24 184771315 ps
T1104 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.935420750 Jul 05 05:59:02 PM PDT 24 Jul 05 05:59:07 PM PDT 24 117113396 ps
T1105 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1067862463 Jul 05 05:59:16 PM PDT 24 Jul 05 05:59:17 PM PDT 24 45836888 ps
T1106 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.826429752 Jul 05 05:59:03 PM PDT 24 Jul 05 05:59:07 PM PDT 24 94866252 ps
T1107 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1555192756 Jul 05 05:59:04 PM PDT 24 Jul 05 05:59:07 PM PDT 24 74122996 ps
T1108 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.741762457 Jul 05 05:59:00 PM PDT 24 Jul 05 05:59:06 PM PDT 24 222260740 ps
T1109 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.416398803 Jul 05 05:59:23 PM PDT 24 Jul 05 05:59:25 PM PDT 24 181081653 ps
T1110 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.1872235064 Jul 05 05:59:06 PM PDT 24 Jul 05 05:59:08 PM PDT 24 55647086 ps
T1111 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.429988988 Jul 05 05:59:08 PM PDT 24 Jul 05 05:59:09 PM PDT 24 89107937 ps
T1112 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.214658566 Jul 05 05:59:20 PM PDT 24 Jul 05 05:59:21 PM PDT 24 33574621 ps
T1113 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.1334937498 Jul 05 05:58:55 PM PDT 24 Jul 05 05:58:57 PM PDT 24 16858884 ps
T1114 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1267422108 Jul 05 05:59:19 PM PDT 24 Jul 05 05:59:20 PM PDT 24 37678560 ps
T1115 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2949041306 Jul 05 05:58:58 PM PDT 24 Jul 05 05:59:03 PM PDT 24 166268485 ps
T1116 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2389721801 Jul 05 05:58:56 PM PDT 24 Jul 05 05:59:00 PM PDT 24 57373420 ps
T1117 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3181850247 Jul 05 05:59:04 PM PDT 24 Jul 05 05:59:06 PM PDT 24 67419725 ps
T1118 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2402902296 Jul 05 05:59:08 PM PDT 24 Jul 05 05:59:09 PM PDT 24 122406547 ps
T1119 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1024993310 Jul 05 05:59:05 PM PDT 24 Jul 05 05:59:07 PM PDT 24 167085300 ps

Test location /workspace/coverage/default/30.pwrmgr_stress_all.3172393052
Short name T4
Test name
Test status
Simulation time 736072624 ps
CPU time 1.81 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:21 PM PDT 24
Peak memory 200936 kb
Host smart-ed287b48-7d97-4add-b7ca-b19c52254758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172393052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.3172393052
Directory /workspace/30.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.349895638
Short name T2
Test name
Test status
Simulation time 785055446 ps
CPU time 3.05 seconds
Started Jul 05 05:52:48 PM PDT 24
Finished Jul 05 05:52:53 PM PDT 24
Peak memory 200928 kb
Host smart-494283f6-e66f-44fc-ab70-b45b7dc940cd
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349895638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.349895638
Directory /workspace/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.2477133404
Short name T42
Test name
Test status
Simulation time 114381030 ps
CPU time 1.01 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:03 PM PDT 24
Peak memory 209244 kb
Host smart-0065a96e-cf8a-45c2-89a5-573f7147892b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477133404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.2477133404
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.3797346809
Short name T20
Test name
Test status
Simulation time 640406239 ps
CPU time 2.17 seconds
Started Jul 05 05:50:41 PM PDT 24
Finished Jul 05 05:50:44 PM PDT 24
Peak memory 216500 kb
Host smart-8cdcbdf9-019f-46f4-bb4a-765b2f2115ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797346809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.3797346809
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1015632402
Short name T53
Test name
Test status
Simulation time 267868289 ps
CPU time 1.64 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 200560 kb
Host smart-4b7c0f27-a056-4af3-8d03-5b10214cde5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015632402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.1015632402
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all_with_rand_reset.3913646663
Short name T55
Test name
Test status
Simulation time 8642117918 ps
CPU time 28.69 seconds
Started Jul 05 05:51:31 PM PDT 24
Finished Jul 05 05:52:00 PM PDT 24
Peak memory 201108 kb
Host smart-880b4ad6-a1e4-4cac-a841-8f1bb8894a98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913646663 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all_with_rand_reset.3913646663
Directory /workspace/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.3956947757
Short name T45
Test name
Test status
Simulation time 56659076 ps
CPU time 0.67 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 201092 kb
Host smart-0e117ed2-dbe6-4cc1-add2-c04ab4e389c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956947757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.3956947757
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2054904730
Short name T185
Test name
Test status
Simulation time 25844653 ps
CPU time 0.61 seconds
Started Jul 05 05:59:11 PM PDT 24
Finished Jul 05 05:59:13 PM PDT 24
Peak memory 195048 kb
Host smart-a41848a1-83e7-4d00-a18c-72f6c6b8887b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054904730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2054904730
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.1887934516
Short name T61
Test name
Test status
Simulation time 218306029 ps
CPU time 1.16 seconds
Started Jul 05 05:52:15 PM PDT 24
Finished Jul 05 05:52:17 PM PDT 24
Peak memory 199620 kb
Host smart-b86ca719-e36f-41f4-8553-45afc84ce300
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887934516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_
cm_ctrl_config_regwen.1887934516
Directory /workspace/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.1435043871
Short name T167
Test name
Test status
Simulation time 840683913 ps
CPU time 0.98 seconds
Started Jul 05 05:51:25 PM PDT 24
Finished Jul 05 05:51:26 PM PDT 24
Peak memory 197848 kb
Host smart-91733998-97c2-4c4e-805d-9c6f937ece00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435043871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.1435043871
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1118661599
Short name T134
Test name
Test status
Simulation time 161938500 ps
CPU time 1 seconds
Started Jul 05 05:58:52 PM PDT 24
Finished Jul 05 05:58:53 PM PDT 24
Peak memory 198768 kb
Host smart-3b34a9a9-8912-45b2-8024-f62be9213fa6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118661599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1
118661599
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3484397379
Short name T87
Test name
Test status
Simulation time 1414673282 ps
CPU time 2.17 seconds
Started Jul 05 05:50:58 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 200880 kb
Host smart-812901ae-6422-4f01-b2ca-0609a323a403
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484397379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3484397379
Directory /workspace/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.1700629771
Short name T56
Test name
Test status
Simulation time 47954799 ps
CPU time 2.24 seconds
Started Jul 05 05:58:53 PM PDT 24
Finished Jul 05 05:58:56 PM PDT 24
Peak memory 197676 kb
Host smart-47efdf54-1392-4982-883d-257436281d46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700629771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.1700629771
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.377253859
Short name T193
Test name
Test status
Simulation time 51904576 ps
CPU time 0.84 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:47 PM PDT 24
Peak memory 198892 kb
Host smart-2f863675-7aba-4adf-8244-bc882326fde5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377253859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disa
ble_rom_integrity_check.377253859
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3827125126
Short name T72
Test name
Test status
Simulation time 254872937 ps
CPU time 1.6 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:00 PM PDT 24
Peak memory 200632 kb
Host smart-d871529e-6236-422e-86be-7b386814184f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827125126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.3827125126
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all.4133114155
Short name T38
Test name
Test status
Simulation time 1420916431 ps
CPU time 2.41 seconds
Started Jul 05 05:52:11 PM PDT 24
Finished Jul 05 05:52:14 PM PDT 24
Peak memory 200972 kb
Host smart-960de3b6-7b5c-4cd0-a03c-ba32525fae21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133114155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.4133114155
Directory /workspace/28.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.1800939490
Short name T191
Test name
Test status
Simulation time 53901438 ps
CPU time 0.76 seconds
Started Jul 05 05:52:17 PM PDT 24
Finished Jul 05 05:52:19 PM PDT 24
Peak memory 198816 kb
Host smart-74ef97e7-f3fe-4181-b976-cb760a8377ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800939490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.1800939490
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3767012688
Short name T146
Test name
Test status
Simulation time 55530958 ps
CPU time 0.76 seconds
Started Jul 05 05:58:52 PM PDT 24
Finished Jul 05 05:58:54 PM PDT 24
Peak memory 197380 kb
Host smart-eb8e2499-ff8a-4128-90eb-6a58cafa9392
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767012688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.3767012688
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all_with_rand_reset.405850259
Short name T161
Test name
Test status
Simulation time 1598255825 ps
CPU time 6.64 seconds
Started Jul 05 05:51:25 PM PDT 24
Finished Jul 05 05:51:32 PM PDT 24
Peak memory 201056 kb
Host smart-a1987c19-8fed-4383-a232-5e642416cbbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405850259 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all_with_rand_reset.405850259
Directory /workspace/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.727860275
Short name T1032
Test name
Test status
Simulation time 23720446 ps
CPU time 0.59 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:00 PM PDT 24
Peak memory 194996 kb
Host smart-27dc7072-af18-421a-b5c1-991ebb8f74b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727860275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.727860275
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.4198211584
Short name T567
Test name
Test status
Simulation time 69980805 ps
CPU time 0.71 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:09 PM PDT 24
Peak memory 198436 kb
Host smart-0e221723-ec69-4787-99e0-ffedeb1e1eb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198211584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.4198211584
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.3813011414
Short name T25
Test name
Test status
Simulation time 64039306 ps
CPU time 0.82 seconds
Started Jul 05 05:51:33 PM PDT 24
Finished Jul 05 05:51:35 PM PDT 24
Peak memory 198852 kb
Host smart-0a7334fe-2770-43df-80d1-1bf290130bdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813011414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.3813011414
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1267455525
Short name T80
Test name
Test status
Simulation time 186860759 ps
CPU time 1.67 seconds
Started Jul 05 05:58:53 PM PDT 24
Finished Jul 05 05:58:56 PM PDT 24
Peak memory 195324 kb
Host smart-a486d652-cd8a-4c69-b545-00a662cb5d26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267455525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.1267455525
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.3022547804
Short name T326
Test name
Test status
Simulation time 165634529 ps
CPU time 0.62 seconds
Started Jul 05 05:50:36 PM PDT 24
Finished Jul 05 05:50:39 PM PDT 24
Peak memory 197904 kb
Host smart-b110354b-23ab-4801-b8ff-0e9a5830751d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022547804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3022547804
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.643254217
Short name T1027
Test name
Test status
Simulation time 39888831 ps
CPU time 1 seconds
Started Jul 05 05:58:53 PM PDT 24
Finished Jul 05 05:58:55 PM PDT 24
Peak memory 200168 kb
Host smart-db302b1c-53cc-496a-b65c-ff8b33a168f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643254217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.643254217
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1567498897
Short name T165
Test name
Test status
Simulation time 271636586 ps
CPU time 3.33 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:06 PM PDT 24
Peak memory 195244 kb
Host smart-910f5c4b-6210-4759-aa63-1f8841e70a6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567498897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.1
567498897
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2948555415
Short name T1026
Test name
Test status
Simulation time 26784053 ps
CPU time 0.71 seconds
Started Jul 05 05:59:09 PM PDT 24
Finished Jul 05 05:59:10 PM PDT 24
Peak memory 195048 kb
Host smart-eb61e1e5-e0d4-461a-9790-d59310a447a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948555415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.2
948555415
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2389721801
Short name T1116
Test name
Test status
Simulation time 57373420 ps
CPU time 0.71 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:00 PM PDT 24
Peak memory 195040 kb
Host smart-7fe5a96d-621a-4a9b-823a-d611c88c959b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389721801 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.2389721801
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2426756967
Short name T136
Test name
Test status
Simulation time 63631710 ps
CPU time 0.68 seconds
Started Jul 05 05:58:57 PM PDT 24
Finished Jul 05 05:59:02 PM PDT 24
Peak memory 197496 kb
Host smart-c529745e-d52a-432d-84b0-28efbd785de8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426756967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.2426756967
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2956534244
Short name T1018
Test name
Test status
Simulation time 30765111 ps
CPU time 0.76 seconds
Started Jul 05 05:58:53 PM PDT 24
Finished Jul 05 05:58:56 PM PDT 24
Peak memory 199696 kb
Host smart-95c8c144-a972-4276-ae1a-d79f22bad6a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956534244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.2956534244
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.2263250452
Short name T1024
Test name
Test status
Simulation time 111777850 ps
CPU time 2.56 seconds
Started Jul 05 05:58:50 PM PDT 24
Finished Jul 05 05:58:53 PM PDT 24
Peak memory 197620 kb
Host smart-9c46433c-f438-42e8-81ff-e57c00e42d71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263250452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.2263250452
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.1621158633
Short name T78
Test name
Test status
Simulation time 174057529 ps
CPU time 1.65 seconds
Started Jul 05 05:58:50 PM PDT 24
Finished Jul 05 05:58:52 PM PDT 24
Peak memory 195356 kb
Host smart-e2e3bacd-1e23-4ef1-8272-395cc0b26bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621158633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.1621158633
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2791093305
Short name T140
Test name
Test status
Simulation time 44589325 ps
CPU time 1.64 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:01 PM PDT 24
Peak memory 195044 kb
Host smart-92079808-061a-4cad-a27d-e635c008d52c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791093305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.2
791093305
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3439569546
Short name T130
Test name
Test status
Simulation time 35822912 ps
CPU time 0.71 seconds
Started Jul 05 05:58:48 PM PDT 24
Finished Jul 05 05:58:49 PM PDT 24
Peak memory 198372 kb
Host smart-bcec876f-0e1e-474b-8768-99e1d7021d20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439569546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.3
439569546
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3590573927
Short name T1052
Test name
Test status
Simulation time 80025854 ps
CPU time 0.94 seconds
Started Jul 05 05:58:59 PM PDT 24
Finished Jul 05 05:59:04 PM PDT 24
Peak memory 196200 kb
Host smart-2b249713-1b7e-4303-b4de-247fee9c9150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590573927 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.3590573927
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.1877010017
Short name T137
Test name
Test status
Simulation time 129086115 ps
CPU time 0.63 seconds
Started Jul 05 05:58:51 PM PDT 24
Finished Jul 05 05:58:53 PM PDT 24
Peak memory 195232 kb
Host smart-3c84b19a-9dd7-4e56-b1e2-a6a19cac3200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877010017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.1877010017
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.695264898
Short name T1094
Test name
Test status
Simulation time 20492527 ps
CPU time 0.6 seconds
Started Jul 05 05:58:55 PM PDT 24
Finished Jul 05 05:58:58 PM PDT 24
Peak memory 195076 kb
Host smart-042ef98d-73cd-4b63-8fad-a257af8a7e20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695264898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.695264898
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.920061714
Short name T1008
Test name
Test status
Simulation time 270172575 ps
CPU time 1.27 seconds
Started Jul 05 05:58:46 PM PDT 24
Finished Jul 05 05:58:48 PM PDT 24
Peak memory 196372 kb
Host smart-63fd202a-6a66-4f5c-b1dd-97542f066990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920061714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.920061714
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2876367153
Short name T66
Test name
Test status
Simulation time 55131183 ps
CPU time 0.92 seconds
Started Jul 05 05:58:57 PM PDT 24
Finished Jul 05 05:59:02 PM PDT 24
Peak memory 200556 kb
Host smart-c4615b59-9213-42c3-adcf-0d6413b28c9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876367153 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.2876367153
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.357949658
Short name T1098
Test name
Test status
Simulation time 17061443 ps
CPU time 0.64 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:00 PM PDT 24
Peak memory 195156 kb
Host smart-8ec95d99-866f-47ff-a058-f592b4d98f51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357949658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.357949658
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.2460842614
Short name T1012
Test name
Test status
Simulation time 43137910 ps
CPU time 0.66 seconds
Started Jul 05 05:59:00 PM PDT 24
Finished Jul 05 05:59:04 PM PDT 24
Peak memory 195052 kb
Host smart-c0b9377e-cafc-4c8a-b781-923834da339a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460842614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.2460842614
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.831252103
Short name T1074
Test name
Test status
Simulation time 46186105 ps
CPU time 0.87 seconds
Started Jul 05 05:59:01 PM PDT 24
Finished Jul 05 05:59:05 PM PDT 24
Peak memory 198412 kb
Host smart-f3ff73ba-0df0-4399-90f1-8dcd4c2500ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831252103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sa
me_csr_outstanding.831252103
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3149115556
Short name T1009
Test name
Test status
Simulation time 231136153 ps
CPU time 1.45 seconds
Started Jul 05 05:58:59 PM PDT 24
Finished Jul 05 05:59:05 PM PDT 24
Peak memory 196472 kb
Host smart-e8cdca0f-25ae-41f5-a01a-bcd473936c24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149115556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.3149115556
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.259531457
Short name T183
Test name
Test status
Simulation time 291054259 ps
CPU time 1.66 seconds
Started Jul 05 05:58:55 PM PDT 24
Finished Jul 05 05:58:59 PM PDT 24
Peak memory 195344 kb
Host smart-61e96e1c-29b8-47fe-bc92-f40ce5f0796c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259531457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err
.259531457
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.305427832
Short name T1010
Test name
Test status
Simulation time 112844977 ps
CPU time 0.91 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:00 PM PDT 24
Peak memory 195268 kb
Host smart-b993fff6-eb78-412e-a7ec-b916dd127c6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305427832 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.305427832
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3892057500
Short name T139
Test name
Test status
Simulation time 17332475 ps
CPU time 0.62 seconds
Started Jul 05 05:58:57 PM PDT 24
Finished Jul 05 05:59:01 PM PDT 24
Peak memory 195084 kb
Host smart-94a331e1-f73c-4791-810c-d486b29d039a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892057500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3892057500
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.442565912
Short name T186
Test name
Test status
Simulation time 69955070 ps
CPU time 0.6 seconds
Started Jul 05 05:58:55 PM PDT 24
Finished Jul 05 05:58:57 PM PDT 24
Peak memory 194948 kb
Host smart-41351079-119e-471d-8674-ed42a7bfb2c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442565912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.442565912
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3018822205
Short name T1076
Test name
Test status
Simulation time 44182233 ps
CPU time 0.73 seconds
Started Jul 05 05:59:11 PM PDT 24
Finished Jul 05 05:59:13 PM PDT 24
Peak memory 197384 kb
Host smart-c6d04c89-9e79-4c4e-92b4-1a9860ac3c1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018822205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.3018822205
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.503637058
Short name T1095
Test name
Test status
Simulation time 177692964 ps
CPU time 1.18 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:02 PM PDT 24
Peak memory 197232 kb
Host smart-aa9a9c15-f227-43c1-a3c7-731c4a275b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503637058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.503637058
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.631051132
Short name T58
Test name
Test status
Simulation time 307573795 ps
CPU time 1.86 seconds
Started Jul 05 05:58:55 PM PDT 24
Finished Jul 05 05:58:58 PM PDT 24
Peak memory 200536 kb
Host smart-8ba31544-4d1a-47f7-b9d3-0b0c4c4066ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631051132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err
.631051132
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1062195044
Short name T71
Test name
Test status
Simulation time 40009871 ps
CPU time 0.7 seconds
Started Jul 05 05:59:23 PM PDT 24
Finished Jul 05 05:59:24 PM PDT 24
Peak memory 195336 kb
Host smart-e78222fc-0d16-443b-80e4-667b12592356
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062195044 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.1062195044
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2662574510
Short name T132
Test name
Test status
Simulation time 25934660 ps
CPU time 0.62 seconds
Started Jul 05 05:59:22 PM PDT 24
Finished Jul 05 05:59:22 PM PDT 24
Peak memory 197276 kb
Host smart-e1d6d710-ea6f-4c47-ad46-3b18d78dba97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662574510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2662574510
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1622491311
Short name T1072
Test name
Test status
Simulation time 26353356 ps
CPU time 0.63 seconds
Started Jul 05 05:59:04 PM PDT 24
Finished Jul 05 05:59:07 PM PDT 24
Peak memory 195052 kb
Host smart-5a05e7cc-7e10-4f77-96e3-ff2b52993ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622491311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.1622491311
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2235267874
Short name T1064
Test name
Test status
Simulation time 60233392 ps
CPU time 0.75 seconds
Started Jul 05 05:59:04 PM PDT 24
Finished Jul 05 05:59:07 PM PDT 24
Peak memory 197348 kb
Host smart-b9fe9958-da3b-4be5-98d3-dfcc16c7c355
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235267874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.2235267874
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.2724818883
Short name T1033
Test name
Test status
Simulation time 156580312 ps
CPU time 1.59 seconds
Started Jul 05 05:59:13 PM PDT 24
Finished Jul 05 05:59:15 PM PDT 24
Peak memory 196448 kb
Host smart-1cc8e632-99dd-4c02-b35e-4c51e2f50010
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724818883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.2724818883
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1197052627
Short name T1040
Test name
Test status
Simulation time 140408245 ps
CPU time 1.06 seconds
Started Jul 05 05:59:04 PM PDT 24
Finished Jul 05 05:59:07 PM PDT 24
Peak memory 200380 kb
Host smart-5da4b177-9dc6-44ae-b390-fe9ead3a3f5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197052627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.1197052627
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1555192756
Short name T1107
Test name
Test status
Simulation time 74122996 ps
CPU time 1.01 seconds
Started Jul 05 05:59:04 PM PDT 24
Finished Jul 05 05:59:07 PM PDT 24
Peak memory 195248 kb
Host smart-72d89201-8de9-480b-8958-1ad717ee9dff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555192756 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.1555192756
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.1690423309
Short name T1082
Test name
Test status
Simulation time 26080826 ps
CPU time 0.69 seconds
Started Jul 05 05:59:02 PM PDT 24
Finished Jul 05 05:59:06 PM PDT 24
Peak memory 197364 kb
Host smart-808140b4-3cca-4fbe-9bbc-921b85303958
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690423309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.1690423309
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.4135978222
Short name T1099
Test name
Test status
Simulation time 18299776 ps
CPU time 0.65 seconds
Started Jul 05 05:59:04 PM PDT 24
Finished Jul 05 05:59:07 PM PDT 24
Peak memory 195052 kb
Host smart-673635e0-de85-4b5a-a959-624095e7f6be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135978222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.4135978222
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1452885546
Short name T1093
Test name
Test status
Simulation time 33694644 ps
CPU time 0.75 seconds
Started Jul 05 05:59:16 PM PDT 24
Finished Jul 05 05:59:17 PM PDT 24
Peak memory 195132 kb
Host smart-be3e3025-96bc-489c-8131-4b9eda7658a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452885546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.1452885546
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.416398803
Short name T1109
Test name
Test status
Simulation time 181081653 ps
CPU time 1.58 seconds
Started Jul 05 05:59:23 PM PDT 24
Finished Jul 05 05:59:25 PM PDT 24
Peak memory 196700 kb
Host smart-2847cad2-4416-41e0-80e4-03ed10d64af8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416398803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.416398803
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.2682822370
Short name T1088
Test name
Test status
Simulation time 166012058 ps
CPU time 1.12 seconds
Started Jul 05 05:58:59 PM PDT 24
Finished Jul 05 05:59:04 PM PDT 24
Peak memory 200216 kb
Host smart-b1dc69bd-7540-4f32-a06a-469d9741a109
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682822370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.2682822370
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.19794708
Short name T1038
Test name
Test status
Simulation time 119059901 ps
CPU time 0.73 seconds
Started Jul 05 05:59:03 PM PDT 24
Finished Jul 05 05:59:06 PM PDT 24
Peak memory 195276 kb
Host smart-18434fbe-57ea-43c5-a28b-10652199042c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794708 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.19794708
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1289858556
Short name T1061
Test name
Test status
Simulation time 17679803 ps
CPU time 0.63 seconds
Started Jul 05 05:59:14 PM PDT 24
Finished Jul 05 05:59:15 PM PDT 24
Peak memory 195216 kb
Host smart-b7bb5ff8-28ff-4865-97d9-76b09768d284
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289858556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1289858556
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.4013783322
Short name T1055
Test name
Test status
Simulation time 20717331 ps
CPU time 0.65 seconds
Started Jul 05 05:59:02 PM PDT 24
Finished Jul 05 05:59:05 PM PDT 24
Peak memory 195020 kb
Host smart-c82cf731-c7b1-4a66-b03b-45bc36e03e44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013783322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.4013783322
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1679548620
Short name T1049
Test name
Test status
Simulation time 66077656 ps
CPU time 0.85 seconds
Started Jul 05 05:59:25 PM PDT 24
Finished Jul 05 05:59:26 PM PDT 24
Peak memory 195064 kb
Host smart-a6b78035-0f57-40e9-a1e8-0ffbfc9f6b44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679548620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.1679548620
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.4124506280
Short name T1014
Test name
Test status
Simulation time 36356528 ps
CPU time 1.46 seconds
Started Jul 05 05:59:01 PM PDT 24
Finished Jul 05 05:59:06 PM PDT 24
Peak memory 196280 kb
Host smart-39d5fc0b-8a33-45c3-910c-8ec2eaea5c64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124506280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.4124506280
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1120468693
Short name T1047
Test name
Test status
Simulation time 156888812 ps
CPU time 1.12 seconds
Started Jul 05 05:59:04 PM PDT 24
Finished Jul 05 05:59:07 PM PDT 24
Peak memory 195332 kb
Host smart-3728443b-2b55-4a81-8c41-842e5f591d19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120468693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.1120468693
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3163250579
Short name T1022
Test name
Test status
Simulation time 40683623 ps
CPU time 0.8 seconds
Started Jul 05 05:59:20 PM PDT 24
Finished Jul 05 05:59:21 PM PDT 24
Peak memory 195304 kb
Host smart-059f2dc5-2eae-473e-95c8-1a54bd6f682c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163250579 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.3163250579
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1979539199
Short name T135
Test name
Test status
Simulation time 28215285 ps
CPU time 0.65 seconds
Started Jul 05 05:59:03 PM PDT 24
Finished Jul 05 05:59:06 PM PDT 24
Peak memory 195144 kb
Host smart-2c3c5010-0f06-4eaa-bf5a-06fb14df5ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979539199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.1979539199
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.4294555499
Short name T1077
Test name
Test status
Simulation time 84831472 ps
CPU time 0.61 seconds
Started Jul 05 05:59:20 PM PDT 24
Finished Jul 05 05:59:21 PM PDT 24
Peak memory 195076 kb
Host smart-cd101920-7d44-4261-b615-3b039f83a004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294555499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.4294555499
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.3705803232
Short name T1029
Test name
Test status
Simulation time 78930049 ps
CPU time 0.84 seconds
Started Jul 05 05:59:03 PM PDT 24
Finished Jul 05 05:59:06 PM PDT 24
Peak memory 198608 kb
Host smart-30bc6058-d8b1-449d-9896-61316d12b8c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705803232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.3705803232
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.32041462
Short name T52
Test name
Test status
Simulation time 78944519 ps
CPU time 1.13 seconds
Started Jul 05 05:59:22 PM PDT 24
Finished Jul 05 05:59:23 PM PDT 24
Peak memory 200696 kb
Host smart-b1ad7731-950f-4ef0-af2e-9b384e610ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32041462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.32041462
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1574434630
Short name T59
Test name
Test status
Simulation time 345680629 ps
CPU time 1.43 seconds
Started Jul 05 05:59:02 PM PDT 24
Finished Jul 05 05:59:06 PM PDT 24
Peak memory 195384 kb
Host smart-1ac02c3a-460f-448c-908f-d2786847d703
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574434630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.1574434630
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.84084740
Short name T1035
Test name
Test status
Simulation time 90897024 ps
CPU time 0.84 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 195264 kb
Host smart-79cce62a-136c-467e-9459-65821cc115e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84084740 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.84084740
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3404434215
Short name T1083
Test name
Test status
Simulation time 46653882 ps
CPU time 0.65 seconds
Started Jul 05 05:59:01 PM PDT 24
Finished Jul 05 05:59:05 PM PDT 24
Peak memory 197368 kb
Host smart-e71cc61f-8299-4bbf-a994-80a896c46a69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404434215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.3404434215
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.612359465
Short name T1062
Test name
Test status
Simulation time 22672843 ps
CPU time 0.65 seconds
Started Jul 05 05:59:01 PM PDT 24
Finished Jul 05 05:59:05 PM PDT 24
Peak memory 195060 kb
Host smart-2ce264e3-8ce7-4e9f-a3d2-acb4021d44dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612359465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.612359465
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.755792586
Short name T1090
Test name
Test status
Simulation time 69061680 ps
CPU time 0.93 seconds
Started Jul 05 05:59:03 PM PDT 24
Finished Jul 05 05:59:06 PM PDT 24
Peak memory 195120 kb
Host smart-b79cc45f-b832-4614-99ef-81543789d16f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755792586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sa
me_csr_outstanding.755792586
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1081436710
Short name T1089
Test name
Test status
Simulation time 362724901 ps
CPU time 2.39 seconds
Started Jul 05 05:59:00 PM PDT 24
Finished Jul 05 05:59:05 PM PDT 24
Peak memory 196456 kb
Host smart-7231a5bd-acf5-4e81-857b-bb1cd1e1b319
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081436710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1081436710
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1947464829
Short name T1007
Test name
Test status
Simulation time 239941054 ps
CPU time 1.16 seconds
Started Jul 05 05:59:08 PM PDT 24
Finished Jul 05 05:59:10 PM PDT 24
Peak memory 200480 kb
Host smart-8b9b56d9-e93b-4072-a924-f7ecdd164824
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947464829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.1947464829
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1628413988
Short name T188
Test name
Test status
Simulation time 54723556 ps
CPU time 0.97 seconds
Started Jul 05 05:59:13 PM PDT 24
Finished Jul 05 05:59:14 PM PDT 24
Peak memory 195268 kb
Host smart-7f2e979f-654d-42d6-8ffa-a581c57ad8db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628413988 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.1628413988
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1452403505
Short name T1023
Test name
Test status
Simulation time 34092006 ps
CPU time 0.62 seconds
Started Jul 05 05:59:05 PM PDT 24
Finished Jul 05 05:59:07 PM PDT 24
Peak memory 195164 kb
Host smart-965e7fd6-2ab0-4ad4-8fab-7351a56913f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452403505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1452403505
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3163870204
Short name T1060
Test name
Test status
Simulation time 43871812 ps
CPU time 0.61 seconds
Started Jul 05 05:59:05 PM PDT 24
Finished Jul 05 05:59:07 PM PDT 24
Peak memory 195056 kb
Host smart-341b5d18-5029-4e19-820e-542e2b0beac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163870204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.3163870204
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.145444550
Short name T143
Test name
Test status
Simulation time 51329023 ps
CPU time 0.74 seconds
Started Jul 05 05:59:20 PM PDT 24
Finished Jul 05 05:59:21 PM PDT 24
Peak memory 198352 kb
Host smart-91d811a0-e1b6-47db-a019-9b3633a5f51d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145444550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sa
me_csr_outstanding.145444550
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.4161251592
Short name T1071
Test name
Test status
Simulation time 56833454 ps
CPU time 1.36 seconds
Started Jul 05 05:59:11 PM PDT 24
Finished Jul 05 05:59:13 PM PDT 24
Peak memory 195552 kb
Host smart-80ea16f4-7e46-45cb-adb9-ee243d144c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161251592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.4161251592
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3150860687
Short name T73
Test name
Test status
Simulation time 191132233 ps
CPU time 1.76 seconds
Started Jul 05 05:59:06 PM PDT 24
Finished Jul 05 05:59:09 PM PDT 24
Peak memory 200348 kb
Host smart-af6443fe-5d84-4016-a84d-e42fce9d084c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150860687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.3150860687
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3523022901
Short name T1092
Test name
Test status
Simulation time 83980003 ps
CPU time 0.83 seconds
Started Jul 05 05:59:23 PM PDT 24
Finished Jul 05 05:59:24 PM PDT 24
Peak memory 194464 kb
Host smart-cb22bbb4-14a8-4cd3-b67c-7af6b0f9f7f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523022901 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.3523022901
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.3149365424
Short name T131
Test name
Test status
Simulation time 23350964 ps
CPU time 0.68 seconds
Started Jul 05 05:59:12 PM PDT 24
Finished Jul 05 05:59:13 PM PDT 24
Peak memory 195240 kb
Host smart-a473198f-43a2-406d-9c19-e1e09c229cbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149365424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.3149365424
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3755725195
Short name T1019
Test name
Test status
Simulation time 23106820 ps
CPU time 0.71 seconds
Started Jul 05 05:59:17 PM PDT 24
Finished Jul 05 05:59:18 PM PDT 24
Peak memory 195080 kb
Host smart-67107f5f-9e57-4bf9-9435-9358f417faa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755725195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.3755725195
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1686875376
Short name T1100
Test name
Test status
Simulation time 27974200 ps
CPU time 0.71 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 195132 kb
Host smart-7ee42631-110d-4530-af19-3379cbadad6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686875376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.1686875376
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.826429752
Short name T1106
Test name
Test status
Simulation time 94866252 ps
CPU time 1.38 seconds
Started Jul 05 05:59:03 PM PDT 24
Finished Jul 05 05:59:07 PM PDT 24
Peak memory 196396 kb
Host smart-6f6261a7-2196-40d0-9f02-d46eca1e7668
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826429752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.826429752
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.4145400981
Short name T1085
Test name
Test status
Simulation time 218929694 ps
CPU time 1.74 seconds
Started Jul 05 05:59:02 PM PDT 24
Finished Jul 05 05:59:06 PM PDT 24
Peak memory 200364 kb
Host smart-486c8fcb-9237-48b6-b9df-4e4da7f0302a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145400981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.4145400981
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1583916211
Short name T1004
Test name
Test status
Simulation time 96769086 ps
CPU time 0.88 seconds
Started Jul 05 05:59:09 PM PDT 24
Finished Jul 05 05:59:11 PM PDT 24
Peak memory 200524 kb
Host smart-2e10ee94-1306-4072-97c7-f5282634ab8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583916211 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.1583916211
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.214658566
Short name T1112
Test name
Test status
Simulation time 33574621 ps
CPU time 0.71 seconds
Started Jul 05 05:59:20 PM PDT 24
Finished Jul 05 05:59:21 PM PDT 24
Peak memory 197384 kb
Host smart-b6d87a4f-e936-48b8-bd76-ffd15d8181ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214658566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.214658566
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.376890998
Short name T1056
Test name
Test status
Simulation time 19615257 ps
CPU time 0.66 seconds
Started Jul 05 05:59:24 PM PDT 24
Finished Jul 05 05:59:25 PM PDT 24
Peak memory 195072 kb
Host smart-0ce7a3ae-7051-41c4-b1b5-1d0cd183e37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376890998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.376890998
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1373685163
Short name T1103
Test name
Test status
Simulation time 184771315 ps
CPU time 0.91 seconds
Started Jul 05 05:59:04 PM PDT 24
Finished Jul 05 05:59:07 PM PDT 24
Peak memory 194972 kb
Host smart-47dacb25-3b9a-4a25-ab82-278bec3169b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373685163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.1373685163
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.160310253
Short name T1079
Test name
Test status
Simulation time 113285411 ps
CPU time 0.96 seconds
Started Jul 05 05:59:23 PM PDT 24
Finished Jul 05 05:59:24 PM PDT 24
Peak memory 194404 kb
Host smart-70ad321c-5b87-41af-bf91-37ebd743f02c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160310253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.160310253
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3094076199
Short name T1043
Test name
Test status
Simulation time 211680436 ps
CPU time 1.69 seconds
Started Jul 05 05:59:24 PM PDT 24
Finished Jul 05 05:59:26 PM PDT 24
Peak memory 195324 kb
Host smart-78772444-195a-4e8e-a04a-8fe5d4db6f60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094076199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.3094076199
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2575761369
Short name T133
Test name
Test status
Simulation time 41675870 ps
CPU time 0.99 seconds
Started Jul 05 05:58:55 PM PDT 24
Finished Jul 05 05:58:58 PM PDT 24
Peak memory 195076 kb
Host smart-884e166e-54c5-45d8-abe1-1a0ff428a826
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575761369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.2
575761369
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.935420750
Short name T1104
Test name
Test status
Simulation time 117113396 ps
CPU time 1.9 seconds
Started Jul 05 05:59:02 PM PDT 24
Finished Jul 05 05:59:07 PM PDT 24
Peak memory 195328 kb
Host smart-d6b027c0-791f-4c53-a7b8-9add8d24e4e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935420750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.935420750
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.401021256
Short name T1073
Test name
Test status
Simulation time 115511795 ps
CPU time 0.68 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:58:59 PM PDT 24
Peak memory 195160 kb
Host smart-813bef8c-a1f6-437a-95b7-cca679c2dd55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401021256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.401021256
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1024719029
Short name T1066
Test name
Test status
Simulation time 54749977 ps
CPU time 0.82 seconds
Started Jul 05 05:58:55 PM PDT 24
Finished Jul 05 05:58:58 PM PDT 24
Peak memory 195272 kb
Host smart-0ca32999-44fb-4d8f-88fc-942fa129ebef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024719029 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.1024719029
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.3838097305
Short name T145
Test name
Test status
Simulation time 19009446 ps
CPU time 0.69 seconds
Started Jul 05 05:58:53 PM PDT 24
Finished Jul 05 05:58:55 PM PDT 24
Peak memory 197320 kb
Host smart-7dba3cc8-14a0-487b-907c-85ceae93391b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838097305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.3838097305
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3588751830
Short name T1053
Test name
Test status
Simulation time 49029631 ps
CPU time 0.63 seconds
Started Jul 05 05:59:01 PM PDT 24
Finished Jul 05 05:59:05 PM PDT 24
Peak memory 195080 kb
Host smart-09519bda-8879-48c4-9cd6-e1e34db84878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588751830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.3588751830
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2056308386
Short name T1075
Test name
Test status
Simulation time 25164553 ps
CPU time 0.85 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:01 PM PDT 24
Peak memory 198524 kb
Host smart-250db71e-da7c-4aa2-940a-61765b131930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056308386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.2056308386
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3146643035
Short name T1068
Test name
Test status
Simulation time 101586705 ps
CPU time 1.16 seconds
Started Jul 05 05:58:55 PM PDT 24
Finished Jul 05 05:58:59 PM PDT 24
Peak memory 200236 kb
Host smart-03dbb3b4-73a6-431c-a79a-c72d9b47895b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146643035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.3146643035
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3335542581
Short name T1051
Test name
Test status
Simulation time 28198110 ps
CPU time 0.59 seconds
Started Jul 05 05:59:19 PM PDT 24
Finished Jul 05 05:59:21 PM PDT 24
Peak memory 195056 kb
Host smart-e981bc18-87f4-4c06-a7ef-bc94f3e7280e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335542581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.3335542581
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.3898484485
Short name T1031
Test name
Test status
Simulation time 56074334 ps
CPU time 0.63 seconds
Started Jul 05 05:59:10 PM PDT 24
Finished Jul 05 05:59:11 PM PDT 24
Peak memory 194972 kb
Host smart-3e5de66b-0817-4f58-a195-d03e67960255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898484485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.3898484485
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.912653649
Short name T1046
Test name
Test status
Simulation time 46951955 ps
CPU time 0.62 seconds
Started Jul 05 05:59:14 PM PDT 24
Finished Jul 05 05:59:15 PM PDT 24
Peak memory 195080 kb
Host smart-0c2f96d8-4aa9-4085-a778-40346c731025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912653649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.912653649
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.429988988
Short name T1111
Test name
Test status
Simulation time 89107937 ps
CPU time 0.63 seconds
Started Jul 05 05:59:08 PM PDT 24
Finished Jul 05 05:59:09 PM PDT 24
Peak memory 195024 kb
Host smart-14d43fb9-a142-460e-98ee-4e7280da571c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429988988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.429988988
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.2037478746
Short name T1063
Test name
Test status
Simulation time 131523851 ps
CPU time 0.57 seconds
Started Jul 05 05:59:20 PM PDT 24
Finished Jul 05 05:59:21 PM PDT 24
Peak memory 195036 kb
Host smart-08ecc589-74e7-4a8e-8813-66b1ab4dc853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037478746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.2037478746
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3974671111
Short name T1069
Test name
Test status
Simulation time 70118983 ps
CPU time 0.59 seconds
Started Jul 05 05:59:08 PM PDT 24
Finished Jul 05 05:59:09 PM PDT 24
Peak memory 195032 kb
Host smart-0de623d3-926c-4cdd-9b79-720f6eeda3c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974671111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3974671111
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1487939796
Short name T1025
Test name
Test status
Simulation time 16792387 ps
CPU time 0.61 seconds
Started Jul 05 05:59:13 PM PDT 24
Finished Jul 05 05:59:14 PM PDT 24
Peak memory 195052 kb
Host smart-4653ce44-00f6-45ef-a1c7-cfe68feac73f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487939796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1487939796
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2064981994
Short name T1041
Test name
Test status
Simulation time 20321392 ps
CPU time 0.63 seconds
Started Jul 05 05:59:20 PM PDT 24
Finished Jul 05 05:59:26 PM PDT 24
Peak memory 195040 kb
Host smart-311df818-fb14-4939-9980-7de66367f73c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064981994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.2064981994
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3379628288
Short name T1021
Test name
Test status
Simulation time 27870654 ps
CPU time 0.66 seconds
Started Jul 05 05:59:10 PM PDT 24
Finished Jul 05 05:59:11 PM PDT 24
Peak memory 194972 kb
Host smart-9220730a-af8a-4563-aec1-dbeaa773cd4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379628288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.3379628288
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3378818647
Short name T1087
Test name
Test status
Simulation time 50144378 ps
CPU time 0.62 seconds
Started Jul 05 05:59:09 PM PDT 24
Finished Jul 05 05:59:10 PM PDT 24
Peak memory 195056 kb
Host smart-122b6012-eae8-4621-a861-71e62289c815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378818647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.3378818647
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3935586952
Short name T1045
Test name
Test status
Simulation time 162270477 ps
CPU time 1 seconds
Started Jul 05 05:58:59 PM PDT 24
Finished Jul 05 05:59:04 PM PDT 24
Peak memory 198624 kb
Host smart-26dcf8f8-c159-4fc0-bcc6-d99f26d5a877
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935586952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.3
935586952
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1245315887
Short name T1050
Test name
Test status
Simulation time 406187934 ps
CPU time 3.18 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:02 PM PDT 24
Peak memory 195280 kb
Host smart-f1f5a67c-d0df-49ff-9836-77d607198c2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245315887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.1
245315887
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1024993310
Short name T1119
Test name
Test status
Simulation time 167085300 ps
CPU time 0.63 seconds
Started Jul 05 05:59:05 PM PDT 24
Finished Jul 05 05:59:07 PM PDT 24
Peak memory 198320 kb
Host smart-a5ae3d07-cc9c-41bb-b030-84c77a25e3e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024993310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.1
024993310
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1895909665
Short name T1101
Test name
Test status
Simulation time 62969229 ps
CPU time 0.99 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:00 PM PDT 24
Peak memory 195292 kb
Host smart-fbaf1c56-6672-433d-9fec-6ae12cc6f736
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895909665 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.1895909665
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3236839254
Short name T141
Test name
Test status
Simulation time 41099363 ps
CPU time 0.65 seconds
Started Jul 05 05:58:57 PM PDT 24
Finished Jul 05 05:59:01 PM PDT 24
Peak memory 197356 kb
Host smart-f06fb2d4-f8d5-41de-ac14-45a05022cd19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236839254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.3236839254
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3119403953
Short name T1096
Test name
Test status
Simulation time 47558099 ps
CPU time 0.66 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 195052 kb
Host smart-e1e09336-46b0-4388-9788-a44a4f5c9839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119403953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.3119403953
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.188101994
Short name T142
Test name
Test status
Simulation time 34564160 ps
CPU time 0.71 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 197316 kb
Host smart-c4d1125d-e8a6-4344-bc92-07184ba66278
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188101994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sam
e_csr_outstanding.188101994
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.618764996
Short name T70
Test name
Test status
Simulation time 52036740 ps
CPU time 2.36 seconds
Started Jul 05 05:58:57 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 197428 kb
Host smart-4eb2ab0c-79c6-445f-b0b3-147246bf059d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618764996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.618764996
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3312969457
Short name T1054
Test name
Test status
Simulation time 49485062 ps
CPU time 0.61 seconds
Started Jul 05 05:59:16 PM PDT 24
Finished Jul 05 05:59:17 PM PDT 24
Peak memory 195048 kb
Host smart-f65fad15-ba9a-4d3a-93b4-4665f60877ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312969457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.3312969457
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2757661498
Short name T68
Test name
Test status
Simulation time 45346327 ps
CPU time 0.6 seconds
Started Jul 05 05:59:19 PM PDT 24
Finished Jul 05 05:59:20 PM PDT 24
Peak memory 195080 kb
Host smart-3b3c794f-a4eb-41dd-976d-2f4e20bc2f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757661498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.2757661498
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3538293290
Short name T1057
Test name
Test status
Simulation time 22904607 ps
CPU time 0.63 seconds
Started Jul 05 05:59:11 PM PDT 24
Finished Jul 05 05:59:12 PM PDT 24
Peak memory 195056 kb
Host smart-1eafb0aa-b033-47e7-9897-09d621ac8261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538293290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.3538293290
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4052012557
Short name T1015
Test name
Test status
Simulation time 18111558 ps
CPU time 0.65 seconds
Started Jul 05 05:59:22 PM PDT 24
Finished Jul 05 05:59:23 PM PDT 24
Peak memory 195056 kb
Host smart-42775292-fa76-4b47-becc-d46d49d5d45d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052012557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.4052012557
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3181850247
Short name T1117
Test name
Test status
Simulation time 67419725 ps
CPU time 0.6 seconds
Started Jul 05 05:59:04 PM PDT 24
Finished Jul 05 05:59:06 PM PDT 24
Peak memory 195056 kb
Host smart-d76d9860-b6e7-4343-a511-e84cbe0d3de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181850247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.3181850247
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.1872235064
Short name T1110
Test name
Test status
Simulation time 55647086 ps
CPU time 0.65 seconds
Started Jul 05 05:59:06 PM PDT 24
Finished Jul 05 05:59:08 PM PDT 24
Peak memory 195048 kb
Host smart-3e5293bd-ada7-4b82-89b8-61ed6663c8b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872235064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.1872235064
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3378381467
Short name T1017
Test name
Test status
Simulation time 23655212 ps
CPU time 0.62 seconds
Started Jul 05 05:59:11 PM PDT 24
Finished Jul 05 05:59:12 PM PDT 24
Peak memory 195056 kb
Host smart-83016c18-282c-4c23-bfbc-848031c71bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378381467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.3378381467
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3306475654
Short name T1039
Test name
Test status
Simulation time 41985572 ps
CPU time 0.63 seconds
Started Jul 05 05:59:15 PM PDT 24
Finished Jul 05 05:59:16 PM PDT 24
Peak memory 195056 kb
Host smart-dfad8a23-d6a2-49d3-90e0-21f790938d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306475654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.3306475654
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.4161706535
Short name T1102
Test name
Test status
Simulation time 34347115 ps
CPU time 0.63 seconds
Started Jul 05 05:59:25 PM PDT 24
Finished Jul 05 05:59:26 PM PDT 24
Peak memory 195044 kb
Host smart-5839d8fc-6af7-4db7-8097-d48c85149344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161706535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.4161706535
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1516030500
Short name T64
Test name
Test status
Simulation time 44052338 ps
CPU time 1.05 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:00 PM PDT 24
Peak memory 198704 kb
Host smart-874d6f98-d32d-4e31-b927-72c032e7db09
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516030500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.1
516030500
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.741762457
Short name T1108
Test name
Test status
Simulation time 222260740 ps
CPU time 1.92 seconds
Started Jul 05 05:59:00 PM PDT 24
Finished Jul 05 05:59:06 PM PDT 24
Peak memory 195288 kb
Host smart-c29357d6-f77a-45f9-b94f-371701310119
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741762457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.741762457
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.554988229
Short name T1002
Test name
Test status
Simulation time 73169220 ps
CPU time 0.73 seconds
Started Jul 05 05:58:54 PM PDT 24
Finished Jul 05 05:58:56 PM PDT 24
Peak memory 195092 kb
Host smart-d1f631db-d6e9-48f0-9e96-be78a4cafdfd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554988229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.554988229
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.86639507
Short name T1097
Test name
Test status
Simulation time 120552881 ps
CPU time 0.91 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 195284 kb
Host smart-97b3665a-bff7-4c4a-bfb6-b71ea07b6527
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86639507 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.86639507
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.902986287
Short name T1030
Test name
Test status
Simulation time 32006757 ps
CPU time 0.64 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:58:59 PM PDT 24
Peak memory 197320 kb
Host smart-daaf6e2d-bfdb-4c56-81a3-22dd869dcf97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902986287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.902986287
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.1397193872
Short name T1048
Test name
Test status
Simulation time 39569088 ps
CPU time 0.62 seconds
Started Jul 05 05:58:57 PM PDT 24
Finished Jul 05 05:59:01 PM PDT 24
Peak memory 195056 kb
Host smart-0b223fc4-6bd4-4c67-85b1-69b441c042e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397193872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1397193872
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3888717197
Short name T1036
Test name
Test status
Simulation time 28981945 ps
CPU time 0.76 seconds
Started Jul 05 05:58:57 PM PDT 24
Finished Jul 05 05:59:02 PM PDT 24
Peak memory 195156 kb
Host smart-aee4e978-7a0a-4221-aaa8-ea85135791b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888717197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.3888717197
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.801413802
Short name T1065
Test name
Test status
Simulation time 338910202 ps
CPU time 1.93 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:04 PM PDT 24
Peak memory 196400 kb
Host smart-7e50aea5-898b-4525-b213-f4428cd847f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801413802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.801413802
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2961732084
Short name T182
Test name
Test status
Simulation time 412897971 ps
CPU time 1.63 seconds
Started Jul 05 05:59:19 PM PDT 24
Finished Jul 05 05:59:21 PM PDT 24
Peak memory 200640 kb
Host smart-143e907f-d265-435d-ac01-91dcab03a6e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961732084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.2961732084
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.305950931
Short name T67
Test name
Test status
Simulation time 17950278 ps
CPU time 0.64 seconds
Started Jul 05 05:59:09 PM PDT 24
Finished Jul 05 05:59:11 PM PDT 24
Peak memory 195048 kb
Host smart-b1615df5-8c25-41d6-8c9b-2134dc415c6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305950931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.305950931
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.3612511251
Short name T1037
Test name
Test status
Simulation time 17554783 ps
CPU time 0.64 seconds
Started Jul 05 05:59:12 PM PDT 24
Finished Jul 05 05:59:13 PM PDT 24
Peak memory 195048 kb
Host smart-f245372a-e2d2-428f-ad5f-f7207d0834a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612511251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.3612511251
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1067862463
Short name T1105
Test name
Test status
Simulation time 45836888 ps
CPU time 0.64 seconds
Started Jul 05 05:59:16 PM PDT 24
Finished Jul 05 05:59:17 PM PDT 24
Peak memory 195076 kb
Host smart-56ad1d6d-cc79-43e9-9999-edab05721cb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067862463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.1067862463
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2830025903
Short name T1011
Test name
Test status
Simulation time 48287768 ps
CPU time 0.59 seconds
Started Jul 05 05:59:24 PM PDT 24
Finished Jul 05 05:59:25 PM PDT 24
Peak memory 195060 kb
Host smart-5a3aaacf-354e-4877-b92c-b294f872c5c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830025903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2830025903
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3405876822
Short name T1080
Test name
Test status
Simulation time 31108782 ps
CPU time 0.63 seconds
Started Jul 05 05:59:28 PM PDT 24
Finished Jul 05 05:59:29 PM PDT 24
Peak memory 194980 kb
Host smart-1fb8a50f-2287-423b-9ba9-18c3cd109f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405876822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.3405876822
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3481462223
Short name T1070
Test name
Test status
Simulation time 21140262 ps
CPU time 0.62 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:32 PM PDT 24
Peak memory 195060 kb
Host smart-fd452a9b-01b1-4d4e-8cc6-6643bf0e9590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481462223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3481462223
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3969585777
Short name T1006
Test name
Test status
Simulation time 83051424 ps
CPU time 0.61 seconds
Started Jul 05 05:59:34 PM PDT 24
Finished Jul 05 05:59:36 PM PDT 24
Peak memory 195048 kb
Host smart-9176e0bd-f7e8-4585-ada7-abc1b66b6f28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969585777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.3969585777
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1267422108
Short name T1114
Test name
Test status
Simulation time 37678560 ps
CPU time 0.61 seconds
Started Jul 05 05:59:19 PM PDT 24
Finished Jul 05 05:59:20 PM PDT 24
Peak memory 195056 kb
Host smart-8f34a7e8-1b5b-442e-a13b-0489ca776f38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267422108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1267422108
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.4162452773
Short name T1078
Test name
Test status
Simulation time 30891929 ps
CPU time 0.61 seconds
Started Jul 05 05:59:25 PM PDT 24
Finished Jul 05 05:59:27 PM PDT 24
Peak memory 195076 kb
Host smart-2001f49f-d685-4e93-ac90-ca1c714c5436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162452773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.4162452773
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.298063160
Short name T1042
Test name
Test status
Simulation time 81316773 ps
CPU time 0.62 seconds
Started Jul 05 05:59:32 PM PDT 24
Finished Jul 05 05:59:34 PM PDT 24
Peak memory 195076 kb
Host smart-37a53eca-6290-4ef2-a2b8-7aa82f999c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298063160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.298063160
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1175601349
Short name T1020
Test name
Test status
Simulation time 179834335 ps
CPU time 1.02 seconds
Started Jul 05 05:58:57 PM PDT 24
Finished Jul 05 05:59:01 PM PDT 24
Peak memory 195296 kb
Host smart-2d26c630-67f9-4a34-a8b7-8371557afdf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175601349 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.1175601349
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.1984720920
Short name T138
Test name
Test status
Simulation time 44538636 ps
CPU time 0.69 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 197772 kb
Host smart-8fb38fca-5515-4dd4-bac8-8d8a227b7107
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984720920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.1984720920
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2896055007
Short name T1081
Test name
Test status
Simulation time 19782775 ps
CPU time 0.62 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:00 PM PDT 24
Peak memory 195036 kb
Host smart-a499fb0b-d2b7-4234-b64d-2f07affcb731
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896055007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.2896055007
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2949041306
Short name T1115
Test name
Test status
Simulation time 166268485 ps
CPU time 0.87 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 199908 kb
Host smart-f8a81efa-316b-403c-a02e-bc5c512bce6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949041306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2949041306
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1705180592
Short name T76
Test name
Test status
Simulation time 285517131 ps
CPU time 1.66 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:01 PM PDT 24
Peak memory 196420 kb
Host smart-5b55db91-5096-4b3e-ab87-b07289ecef40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705180592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.1705180592
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2511434120
Short name T1013
Test name
Test status
Simulation time 284765367 ps
CPU time 1.66 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:04 PM PDT 24
Peak memory 200640 kb
Host smart-01349ef8-2bec-43ea-b02a-b72ccdd0da84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511434120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.2511434120
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.669626737
Short name T1005
Test name
Test status
Simulation time 36289614 ps
CPU time 0.87 seconds
Started Jul 05 05:59:04 PM PDT 24
Finished Jul 05 05:59:06 PM PDT 24
Peak memory 200560 kb
Host smart-4248ef45-8a97-4088-95ef-bdefe34b5e19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669626737 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.669626737
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.3640035924
Short name T1001
Test name
Test status
Simulation time 66013644 ps
CPU time 0.64 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:00 PM PDT 24
Peak memory 197392 kb
Host smart-4320a107-6845-4f38-b61c-b635c36b6adf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640035924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.3640035924
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.1066378960
Short name T187
Test name
Test status
Simulation time 20032606 ps
CPU time 0.68 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 195076 kb
Host smart-6b42ef1f-a35b-48b8-a044-2761a48a101b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066378960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.1066378960
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.3380298311
Short name T144
Test name
Test status
Simulation time 47007042 ps
CPU time 0.92 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 198412 kb
Host smart-036c47da-18c7-4bf0-8f85-9cd1b54d2a97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380298311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.3380298311
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.333325969
Short name T1003
Test name
Test status
Simulation time 488420527 ps
CPU time 1.27 seconds
Started Jul 05 05:58:55 PM PDT 24
Finished Jul 05 05:58:59 PM PDT 24
Peak memory 196376 kb
Host smart-6f5365dd-aa78-4c00-816d-71d453ede85a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333325969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.333325969
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.785170994
Short name T1016
Test name
Test status
Simulation time 52662740 ps
CPU time 1.33 seconds
Started Jul 05 05:58:55 PM PDT 24
Finished Jul 05 05:58:59 PM PDT 24
Peak memory 196644 kb
Host smart-a2cbc94b-ef1b-4d1f-a2bd-9e64e5c69a81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785170994 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.785170994
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.2859007476
Short name T63
Test name
Test status
Simulation time 32537817 ps
CPU time 0.73 seconds
Started Jul 05 05:58:54 PM PDT 24
Finished Jul 05 05:58:56 PM PDT 24
Peak memory 197348 kb
Host smart-e23591bc-4d97-483b-8eb9-633371f68eb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859007476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.2859007476
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3267102358
Short name T69
Test name
Test status
Simulation time 44942390 ps
CPU time 0.65 seconds
Started Jul 05 05:58:57 PM PDT 24
Finished Jul 05 05:59:01 PM PDT 24
Peak memory 195056 kb
Host smart-a58950b6-7267-4d91-b8cd-99463ac4aa78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267102358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.3267102358
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.32766201
Short name T147
Test name
Test status
Simulation time 74947298 ps
CPU time 0.81 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:58:59 PM PDT 24
Peak memory 199968 kb
Host smart-d37daa78-2625-48ee-bd0f-861c69eacb46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32766201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_same
_csr_outstanding.32766201
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.252689095
Short name T1058
Test name
Test status
Simulation time 308998672 ps
CPU time 1.74 seconds
Started Jul 05 05:58:59 PM PDT 24
Finished Jul 05 05:59:05 PM PDT 24
Peak memory 196404 kb
Host smart-0df570ae-083f-423c-86dc-b7da61d712f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252689095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.252689095
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1264682550
Short name T1086
Test name
Test status
Simulation time 353491970 ps
CPU time 1.5 seconds
Started Jul 05 05:58:54 PM PDT 24
Finished Jul 05 05:58:57 PM PDT 24
Peak memory 195364 kb
Host smart-3d856923-f123-496f-9039-dc7ceba6b9fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264682550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.1264682550
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.192135801
Short name T166
Test name
Test status
Simulation time 39479568 ps
CPU time 0.79 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 195256 kb
Host smart-58b6ff3a-1912-497a-ab4f-6c85264ba184
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192135801 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.192135801
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.1334937498
Short name T1113
Test name
Test status
Simulation time 16858884 ps
CPU time 0.67 seconds
Started Jul 05 05:58:55 PM PDT 24
Finished Jul 05 05:58:57 PM PDT 24
Peak memory 195156 kb
Host smart-098bebc7-00f5-4b97-af24-955882ce9db1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334937498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.1334937498
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.2566415327
Short name T1059
Test name
Test status
Simulation time 22240123 ps
CPU time 0.63 seconds
Started Jul 05 05:59:01 PM PDT 24
Finished Jul 05 05:59:05 PM PDT 24
Peak memory 195060 kb
Host smart-8393c3c0-4475-4100-bc83-fb470150c689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566415327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.2566415327
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1850876921
Short name T1044
Test name
Test status
Simulation time 42259065 ps
CPU time 0.92 seconds
Started Jul 05 05:58:57 PM PDT 24
Finished Jul 05 05:59:02 PM PDT 24
Peak memory 195112 kb
Host smart-38d5a936-5067-4edb-aaae-ae1c91cf1042
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850876921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.1850876921
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1237960497
Short name T1084
Test name
Test status
Simulation time 128740751 ps
CPU time 2.24 seconds
Started Jul 05 05:58:56 PM PDT 24
Finished Jul 05 05:59:02 PM PDT 24
Peak memory 196620 kb
Host smart-5fb0d87a-88cd-4f7d-abb5-d264ffdc0e4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237960497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.1237960497
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1880572357
Short name T1034
Test name
Test status
Simulation time 360293898 ps
CPU time 1.64 seconds
Started Jul 05 05:59:04 PM PDT 24
Finished Jul 05 05:59:08 PM PDT 24
Peak memory 200604 kb
Host smart-c428c33d-e6db-4e34-b5bc-837004aa16e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880572357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.1880572357
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2402902296
Short name T1118
Test name
Test status
Simulation time 122406547 ps
CPU time 1.2 seconds
Started Jul 05 05:59:08 PM PDT 24
Finished Jul 05 05:59:09 PM PDT 24
Peak memory 197404 kb
Host smart-a28d4670-26d7-4cd7-a504-7f36a3a996a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402902296 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.2402902296
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2908987596
Short name T129
Test name
Test status
Simulation time 56341384 ps
CPU time 0.63 seconds
Started Jul 05 05:58:59 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 195172 kb
Host smart-848efbaa-082c-4c88-b239-f5069178fadb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908987596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.2908987596
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.73421212
Short name T184
Test name
Test status
Simulation time 42897394 ps
CPU time 0.6 seconds
Started Jul 05 05:58:58 PM PDT 24
Finished Jul 05 05:59:03 PM PDT 24
Peak memory 195072 kb
Host smart-c062edef-8a59-464f-8150-65eb722206fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73421212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.73421212
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2863402877
Short name T1067
Test name
Test status
Simulation time 40641038 ps
CPU time 0.78 seconds
Started Jul 05 05:58:57 PM PDT 24
Finished Jul 05 05:59:01 PM PDT 24
Peak memory 197376 kb
Host smart-f6fba5e0-b113-4d4c-bd11-e6988477642d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863402877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.2863402877
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2400801606
Short name T1091
Test name
Test status
Simulation time 47519650 ps
CPU time 1.96 seconds
Started Jul 05 05:59:05 PM PDT 24
Finished Jul 05 05:59:08 PM PDT 24
Peak memory 196376 kb
Host smart-ea563c2a-56ea-4426-973d-8d5d995f7e52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400801606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.2400801606
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2881986547
Short name T1028
Test name
Test status
Simulation time 211508586 ps
CPU time 1.52 seconds
Started Jul 05 05:58:55 PM PDT 24
Finished Jul 05 05:58:58 PM PDT 24
Peak memory 200604 kb
Host smart-b846729f-dfbb-477b-b8b6-35001ea6201e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881986547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.2881986547
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.2637924621
Short name T149
Test name
Test status
Simulation time 42338788 ps
CPU time 0.71 seconds
Started Jul 05 05:50:38 PM PDT 24
Finished Jul 05 05:50:41 PM PDT 24
Peak memory 198640 kb
Host smart-24b4c08a-f905-460e-9ff2-8abb32681898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637924621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.2637924621
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.2348191581
Short name T780
Test name
Test status
Simulation time 82841022 ps
CPU time 0.69 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:40 PM PDT 24
Peak memory 198244 kb
Host smart-25e7c2cd-831d-4f9a-807d-a5d6e15f6fdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348191581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.2348191581
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.791140502
Short name T983
Test name
Test status
Simulation time 29355272 ps
CPU time 0.64 seconds
Started Jul 05 05:50:50 PM PDT 24
Finished Jul 05 05:50:53 PM PDT 24
Peak memory 197812 kb
Host smart-254f020c-85e6-421e-a550-e5699d39471e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791140502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_m
alfunc.791140502
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.3435629048
Short name T879
Test name
Test status
Simulation time 314598945 ps
CPU time 0.96 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:41 PM PDT 24
Peak memory 198144 kb
Host smart-49a880e2-b6c0-4a4c-b473-20d1ced79da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435629048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3435629048
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.4237063823
Short name T938
Test name
Test status
Simulation time 44832143 ps
CPU time 0.63 seconds
Started Jul 05 05:50:45 PM PDT 24
Finished Jul 05 05:50:46 PM PDT 24
Peak memory 198172 kb
Host smart-25325462-24c8-4b78-ae8b-c1b9257efb99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237063823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.4237063823
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.276725473
Short name T791
Test name
Test status
Simulation time 44338056 ps
CPU time 0.74 seconds
Started Jul 05 05:50:38 PM PDT 24
Finished Jul 05 05:50:40 PM PDT 24
Peak memory 201132 kb
Host smart-0c757c42-f1c8-486c-b406-29142126ff9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276725473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid
.276725473
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.1973782468
Short name T306
Test name
Test status
Simulation time 146002168 ps
CPU time 0.77 seconds
Started Jul 05 05:50:36 PM PDT 24
Finished Jul 05 05:50:39 PM PDT 24
Peak memory 198228 kb
Host smart-d108ca25-4e7a-4787-be1c-c86073bc9ca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973782468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wa
keup_race.1973782468
Directory /workspace/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.4276552793
Short name T474
Test name
Test status
Simulation time 156177243 ps
CPU time 0.82 seconds
Started Jul 05 05:50:35 PM PDT 24
Finished Jul 05 05:50:38 PM PDT 24
Peak memory 199708 kb
Host smart-00e1729d-e2ef-423e-af44-7d8a36b9179e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276552793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.4276552793
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.2856615348
Short name T888
Test name
Test status
Simulation time 183484773 ps
CPU time 0.76 seconds
Started Jul 05 05:50:34 PM PDT 24
Finished Jul 05 05:50:36 PM PDT 24
Peak memory 209296 kb
Host smart-b627b2d8-5383-4f68-912d-2907f029f390
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856615348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.2856615348
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1299245782
Short name T290
Test name
Test status
Simulation time 567383392 ps
CPU time 0.88 seconds
Started Jul 05 05:50:49 PM PDT 24
Finished Jul 05 05:50:52 PM PDT 24
Peak memory 199908 kb
Host smart-9828f00c-a827-467b-9d28-f8b218174918
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299245782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_c
m_ctrl_config_regwen.1299245782
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4021626850
Short name T544
Test name
Test status
Simulation time 786285212 ps
CPU time 3.04 seconds
Started Jul 05 05:50:41 PM PDT 24
Finished Jul 05 05:50:45 PM PDT 24
Peak memory 200828 kb
Host smart-04f0b993-dcf1-46ba-99dc-11d600417891
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021626850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4021626850
Directory /workspace/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2168724833
Short name T252
Test name
Test status
Simulation time 865035582 ps
CPU time 3.23 seconds
Started Jul 05 05:50:49 PM PDT 24
Finished Jul 05 05:50:55 PM PDT 24
Peak memory 200952 kb
Host smart-fd26ff46-9745-4528-8dfe-fe2192dfc20a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168724833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2168724833
Directory /workspace/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3162752685
Short name T40
Test name
Test status
Simulation time 79992106 ps
CPU time 0.94 seconds
Started Jul 05 05:50:34 PM PDT 24
Finished Jul 05 05:50:37 PM PDT 24
Peak memory 199196 kb
Host smart-44bdd9e5-28af-43c3-a024-ca6b385cf51b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162752685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3162752685
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.2254347657
Short name T390
Test name
Test status
Simulation time 89060061 ps
CPU time 0.61 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:40 PM PDT 24
Peak memory 198272 kb
Host smart-02e21b65-ffc3-4cd9-a60b-d6b5437bbd0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254347657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.2254347657
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all.1812063276
Short name T771
Test name
Test status
Simulation time 865169476 ps
CPU time 2.13 seconds
Started Jul 05 05:50:38 PM PDT 24
Finished Jul 05 05:50:42 PM PDT 24
Peak memory 200888 kb
Host smart-8c0ac14f-d9c7-407a-80fc-6e6a2319cb62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812063276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.1812063276
Directory /workspace/0.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all_with_rand_reset.3145474336
Short name T93
Test name
Test status
Simulation time 3724549634 ps
CPU time 12.45 seconds
Started Jul 05 05:50:47 PM PDT 24
Finished Jul 05 05:51:00 PM PDT 24
Peak memory 201128 kb
Host smart-a7f5e7ff-e66e-4200-9220-40008ef3b826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145474336 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all_with_rand_reset.3145474336
Directory /workspace/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup.355273045
Short name T158
Test name
Test status
Simulation time 277397682 ps
CPU time 0.96 seconds
Started Jul 05 05:50:42 PM PDT 24
Finished Jul 05 05:50:44 PM PDT 24
Peak memory 199412 kb
Host smart-19a5e574-dfca-4cd1-aaa8-af9ebfbbbf04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355273045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.355273045
Directory /workspace/0.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.649420053
Short name T807
Test name
Test status
Simulation time 88777659 ps
CPU time 0.78 seconds
Started Jul 05 05:50:47 PM PDT 24
Finished Jul 05 05:50:48 PM PDT 24
Peak memory 199068 kb
Host smart-46e35506-b5d9-4f1d-91d1-0bcc442cf7ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649420053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.649420053
Directory /workspace/0.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.1002908113
Short name T907
Test name
Test status
Simulation time 19144201 ps
CPU time 0.67 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 198904 kb
Host smart-2dc57431-00d6-45b6-9b3d-b571abe985f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002908113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.1002908113
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.1275074862
Short name T512
Test name
Test status
Simulation time 58872069 ps
CPU time 0.77 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:40 PM PDT 24
Peak memory 198860 kb
Host smart-aa92a7be-3a74-444d-a668-dc3c169b0095
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275074862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.1275074862
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1810012331
Short name T283
Test name
Test status
Simulation time 38101596 ps
CPU time 0.6 seconds
Started Jul 05 05:50:39 PM PDT 24
Finished Jul 05 05:50:41 PM PDT 24
Peak memory 197692 kb
Host smart-9f2d47a5-fccd-4d79-b7df-9a360cf8e400
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810012331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.1810012331
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.1059064874
Short name T284
Test name
Test status
Simulation time 310779629 ps
CPU time 0.93 seconds
Started Jul 05 05:50:42 PM PDT 24
Finished Jul 05 05:50:44 PM PDT 24
Peak memory 198168 kb
Host smart-8afe484a-d461-4a50-b20d-17a2558b8680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059064874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.1059064874
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.2761901747
Short name T797
Test name
Test status
Simulation time 46677434 ps
CPU time 0.69 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:50:56 PM PDT 24
Peak memory 197896 kb
Host smart-2e4e605a-92ca-4de5-877f-f9285992c14b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761901747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.2761901747
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.2796581565
Short name T225
Test name
Test status
Simulation time 22373512 ps
CPU time 0.63 seconds
Started Jul 05 05:50:44 PM PDT 24
Finished Jul 05 05:50:45 PM PDT 24
Peak memory 198100 kb
Host smart-986c97eb-b71b-45d1-8829-2e982865f368
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796581565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2796581565
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.4078531803
Short name T281
Test name
Test status
Simulation time 111912026 ps
CPU time 0.7 seconds
Started Jul 05 05:50:48 PM PDT 24
Finished Jul 05 05:50:49 PM PDT 24
Peak memory 201140 kb
Host smart-a7812ac6-2a77-4c69-acb5-edf4de93ab96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078531803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.4078531803
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.3605117842
Short name T461
Test name
Test status
Simulation time 52961555 ps
CPU time 0.73 seconds
Started Jul 05 05:50:40 PM PDT 24
Finished Jul 05 05:50:42 PM PDT 24
Peak memory 198852 kb
Host smart-c59ef87e-ccb5-4938-9418-e3fb48b02d7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605117842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wa
keup_race.3605117842
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.1014712079
Short name T423
Test name
Test status
Simulation time 126332921 ps
CPU time 0.95 seconds
Started Jul 05 05:50:40 PM PDT 24
Finished Jul 05 05:50:42 PM PDT 24
Peak memory 199792 kb
Host smart-b48c937b-115b-47e4-8187-458c51cf1370
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014712079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.1014712079
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.1855322728
Short name T922
Test name
Test status
Simulation time 104616317 ps
CPU time 0.93 seconds
Started Jul 05 05:50:42 PM PDT 24
Finished Jul 05 05:50:44 PM PDT 24
Peak memory 209388 kb
Host smart-c5eb1cbb-364e-413a-8e46-61766fa1cac8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855322728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.1855322728
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.2111205574
Short name T19
Test name
Test status
Simulation time 314378177 ps
CPU time 1.46 seconds
Started Jul 05 05:54:16 PM PDT 24
Finished Jul 05 05:54:19 PM PDT 24
Peak memory 217152 kb
Host smart-e8c4389a-a34c-40a2-99d1-4acab0e59a5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111205574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.2111205574
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3706244238
Short name T396
Test name
Test status
Simulation time 143427209 ps
CPU time 0.75 seconds
Started Jul 05 05:50:48 PM PDT 24
Finished Jul 05 05:50:51 PM PDT 24
Peak memory 198924 kb
Host smart-a7a7a953-13e9-4d97-97d5-c46eda1888eb
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706244238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_c
m_ctrl_config_regwen.3706244238
Directory /workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2486358301
Short name T24
Test name
Test status
Simulation time 797279980 ps
CPU time 3.03 seconds
Started Jul 05 05:50:46 PM PDT 24
Finished Jul 05 05:50:50 PM PDT 24
Peak memory 200952 kb
Host smart-2a352103-e8ab-4478-a11d-602f355ac23c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486358301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2486358301
Directory /workspace/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2094715060
Short name T472
Test name
Test status
Simulation time 942071278 ps
CPU time 2.32 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:50:58 PM PDT 24
Peak memory 200876 kb
Host smart-3efa8f3c-ed0b-4ab1-b924-69d5fc274e4d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094715060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2094715060
Directory /workspace/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.3871266111
Short name T798
Test name
Test status
Simulation time 69280407 ps
CPU time 0.88 seconds
Started Jul 05 05:50:39 PM PDT 24
Finished Jul 05 05:50:42 PM PDT 24
Peak memory 199012 kb
Host smart-e3ac52e7-ba47-4bd4-8000-fbf1816aaec6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871266111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3871266111
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.2045411776
Short name T403
Test name
Test status
Simulation time 34404092 ps
CPU time 0.67 seconds
Started Jul 05 05:50:47 PM PDT 24
Finished Jul 05 05:50:49 PM PDT 24
Peak memory 199132 kb
Host smart-027ab596-fe19-443e-b821-255c6dacb4ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045411776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.2045411776
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all.341742540
Short name T207
Test name
Test status
Simulation time 1562423202 ps
CPU time 4.82 seconds
Started Jul 05 05:50:56 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 200920 kb
Host smart-dc3e18df-afa0-4285-823c-33f02c6bb997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341742540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.341742540
Directory /workspace/1.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all_with_rand_reset.4020302700
Short name T1000
Test name
Test status
Simulation time 14486291070 ps
CPU time 19.69 seconds
Started Jul 05 05:50:41 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 201100 kb
Host smart-ddb50891-c4c4-4a27-88dc-35e292df9cbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020302700 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all_with_rand_reset.4020302700
Directory /workspace/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup.2121050236
Short name T618
Test name
Test status
Simulation time 543009005 ps
CPU time 1.01 seconds
Started Jul 05 05:50:53 PM PDT 24
Finished Jul 05 05:50:56 PM PDT 24
Peak memory 199616 kb
Host smart-46648813-489a-43a9-9235-a428cf2def46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121050236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.2121050236
Directory /workspace/1.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup_reset.610951594
Short name T937
Test name
Test status
Simulation time 272315712 ps
CPU time 1.15 seconds
Started Jul 05 05:50:47 PM PDT 24
Finished Jul 05 05:50:49 PM PDT 24
Peak memory 199712 kb
Host smart-5fe80c04-9daf-43ca-8c5f-e5c837c5c46b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610951594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.610951594
Directory /workspace/1.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.2758820314
Short name T507
Test name
Test status
Simulation time 203663859 ps
CPU time 0.7 seconds
Started Jul 05 05:51:07 PM PDT 24
Finished Jul 05 05:51:10 PM PDT 24
Peak memory 198464 kb
Host smart-7e17d614-9963-4471-8575-b3acb42265ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758820314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.2758820314
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.4017385970
Short name T413
Test name
Test status
Simulation time 30125260 ps
CPU time 0.64 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:01 PM PDT 24
Peak memory 197000 kb
Host smart-26f53df6-cda3-4557-967e-17e801336848
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017385970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.4017385970
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.826171089
Short name T761
Test name
Test status
Simulation time 215921282 ps
CPU time 0.95 seconds
Started Jul 05 05:51:04 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 197784 kb
Host smart-e5e507f7-494e-47f7-a557-e7b2dc0c8d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826171089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.826171089
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.3258340418
Short name T236
Test name
Test status
Simulation time 249578390 ps
CPU time 0.67 seconds
Started Jul 05 05:51:23 PM PDT 24
Finished Jul 05 05:51:24 PM PDT 24
Peak memory 197100 kb
Host smart-b44ede65-a28a-4158-bb12-ff8e87aaf4ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258340418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.3258340418
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.3385833404
Short name T394
Test name
Test status
Simulation time 153755142 ps
CPU time 0.6 seconds
Started Jul 05 05:51:22 PM PDT 24
Finished Jul 05 05:51:23 PM PDT 24
Peak memory 198168 kb
Host smart-e9e1ba41-d8ea-4e96-bac8-569222467671
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385833404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.3385833404
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.363682045
Short name T892
Test name
Test status
Simulation time 43437305 ps
CPU time 0.74 seconds
Started Jul 05 05:51:07 PM PDT 24
Finished Jul 05 05:51:10 PM PDT 24
Peak memory 201072 kb
Host smart-c77aa114-efe1-412d-b99c-337816b59067
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363682045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_invali
d.363682045
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.2322589375
Short name T596
Test name
Test status
Simulation time 147620754 ps
CPU time 0.76 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:09 PM PDT 24
Peak memory 198904 kb
Host smart-03d40d9d-0234-49aa-b264-35034ef35f00
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322589375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_w
akeup_race.2322589375
Directory /workspace/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.1887726767
Short name T839
Test name
Test status
Simulation time 56279280 ps
CPU time 0.89 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:09 PM PDT 24
Peak memory 198892 kb
Host smart-70617b2d-3dcb-45c8-bf2e-b078b63bb258
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887726767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.1887726767
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.2524442153
Short name T687
Test name
Test status
Simulation time 172704335 ps
CPU time 1.08 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:04 PM PDT 24
Peak memory 198572 kb
Host smart-ada7a0fe-35f1-4437-b273-84e01a7bb007
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524442153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_
cm_ctrl_config_regwen.2524442153
Directory /workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.600516928
Short name T897
Test name
Test status
Simulation time 1149729554 ps
CPU time 2.27 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:10 PM PDT 24
Peak memory 200836 kb
Host smart-8e08fe94-40d5-4e6f-887c-cd758d625ca7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600516928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.600516928
Directory /workspace/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3730380318
Short name T408
Test name
Test status
Simulation time 819227633 ps
CPU time 2.47 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:06 PM PDT 24
Peak memory 200864 kb
Host smart-a9bbb1eb-4adc-49ba-977a-22c5762a422c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730380318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3730380318
Directory /workspace/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2094346820
Short name T566
Test name
Test status
Simulation time 91884483 ps
CPU time 0.93 seconds
Started Jul 05 05:51:03 PM PDT 24
Finished Jul 05 05:51:06 PM PDT 24
Peak memory 198928 kb
Host smart-dbd76c8f-5911-4966-a5a6-00a9aed62342
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094346820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2094346820
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.1840253220
Short name T289
Test name
Test status
Simulation time 80329869 ps
CPU time 0.63 seconds
Started Jul 05 05:51:02 PM PDT 24
Finished Jul 05 05:51:05 PM PDT 24
Peak memory 199152 kb
Host smart-243a5a3e-d8e7-48fa-bec7-062b14978815
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840253220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.1840253220
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all.2626803552
Short name T828
Test name
Test status
Simulation time 1413350224 ps
CPU time 5.1 seconds
Started Jul 05 05:51:07 PM PDT 24
Finished Jul 05 05:51:14 PM PDT 24
Peak memory 200956 kb
Host smart-4cdc6230-a3cd-49c3-a987-09872d3bf8aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626803552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.2626803552
Directory /workspace/10.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all_with_rand_reset.4242116831
Short name T75
Test name
Test status
Simulation time 10058857897 ps
CPU time 16.02 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:19 PM PDT 24
Peak memory 201144 kb
Host smart-0ac8dc18-0687-49e2-a23d-bcbf1cb994d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242116831 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all_with_rand_reset.4242116831
Directory /workspace/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup.4122182498
Short name T639
Test name
Test status
Simulation time 185668750 ps
CPU time 1.03 seconds
Started Jul 05 05:50:55 PM PDT 24
Finished Jul 05 05:50:58 PM PDT 24
Peak memory 199380 kb
Host smart-eefe81e6-95ad-4a91-89c5-81d7f0793eac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122182498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.4122182498
Directory /workspace/10.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup_reset.4260338935
Short name T816
Test name
Test status
Simulation time 384622664 ps
CPU time 1.11 seconds
Started Jul 05 05:51:02 PM PDT 24
Finished Jul 05 05:51:05 PM PDT 24
Peak memory 200724 kb
Host smart-7c0e6970-5d7b-4790-906b-587fea8e7abb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260338935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.4260338935
Directory /workspace/10.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.3525380448
Short name T690
Test name
Test status
Simulation time 36946965 ps
CPU time 1.15 seconds
Started Jul 05 05:51:07 PM PDT 24
Finished Jul 05 05:51:10 PM PDT 24
Peak memory 200696 kb
Host smart-93b0b290-3711-4a18-b24b-6cb86556de03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525380448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.3525380448
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.1877125462
Short name T949
Test name
Test status
Simulation time 100200851 ps
CPU time 0.76 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:27 PM PDT 24
Peak memory 198844 kb
Host smart-af807e9e-8a32-4a0b-91cb-26f2b6c6dd4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877125462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.1877125462
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.3218054719
Short name T935
Test name
Test status
Simulation time 38723704 ps
CPU time 0.6 seconds
Started Jul 05 05:51:04 PM PDT 24
Finished Jul 05 05:51:06 PM PDT 24
Peak memory 197780 kb
Host smart-550c2e22-856e-49c3-ba80-5b989af11525
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218054719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.3218054719
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.2524562754
Short name T400
Test name
Test status
Simulation time 334860840 ps
CPU time 0.97 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:09 PM PDT 24
Peak memory 197848 kb
Host smart-54029081-9cc8-4193-a89c-0b8e96f30431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524562754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.2524562754
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.237333068
Short name T445
Test name
Test status
Simulation time 38504861 ps
CPU time 0.69 seconds
Started Jul 05 05:51:04 PM PDT 24
Finished Jul 05 05:51:06 PM PDT 24
Peak memory 197868 kb
Host smart-2f15655f-51fa-4960-828a-d73a088b2434
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237333068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.237333068
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.1195795427
Short name T958
Test name
Test status
Simulation time 29123483 ps
CPU time 0.63 seconds
Started Jul 05 05:51:17 PM PDT 24
Finished Jul 05 05:51:19 PM PDT 24
Peak memory 197848 kb
Host smart-413a3d6c-6b38-4b03-918e-8594a66746c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195795427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1195795427
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.1282827859
Short name T610
Test name
Test status
Simulation time 52262228 ps
CPU time 0.74 seconds
Started Jul 05 05:51:25 PM PDT 24
Finished Jul 05 05:51:26 PM PDT 24
Peak memory 201124 kb
Host smart-cbd79f2b-f31f-4f3e-b035-0b47befe6d0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282827859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.1282827859
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_wakeup_race.3535902820
Short name T28
Test name
Test status
Simulation time 288285512 ps
CPU time 1 seconds
Started Jul 05 05:51:04 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 199332 kb
Host smart-c3f9a55d-7a7b-4b6c-a8b7-16d1a1d9e8d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535902820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_w
akeup_race.3535902820
Directory /workspace/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.1924047181
Short name T440
Test name
Test status
Simulation time 182460599 ps
CPU time 0.8 seconds
Started Jul 05 05:50:58 PM PDT 24
Finished Jul 05 05:51:00 PM PDT 24
Peak memory 198772 kb
Host smart-772abda7-3f88-4b6e-909c-cda75ce877c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924047181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.1924047181
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.719051696
Short name T372
Test name
Test status
Simulation time 109267914 ps
CPU time 0.94 seconds
Started Jul 05 05:51:08 PM PDT 24
Finished Jul 05 05:51:11 PM PDT 24
Peak memory 209272 kb
Host smart-5b5153cb-c14d-4bf9-bd88-11af01d4b536
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719051696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.719051696
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.4135437776
Short name T106
Test name
Test status
Simulation time 114068595 ps
CPU time 0.75 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 198384 kb
Host smart-05538db6-57df-409a-ab7f-30416a31cca6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135437776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_
cm_ctrl_config_regwen.4135437776
Directory /workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3666491573
Short name T978
Test name
Test status
Simulation time 868502203 ps
CPU time 3.47 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:11 PM PDT 24
Peak memory 200928 kb
Host smart-4fdc9191-6d75-4620-a927-95cd4eee5a10
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666491573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3666491573
Directory /workspace/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.19892136
Short name T782
Test name
Test status
Simulation time 987385332 ps
CPU time 2.41 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 200944 kb
Host smart-48fedac1-d50f-497c-b4cf-6cf07f567221
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19892136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.19892136
Directory /workspace/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2734229794
Short name T492
Test name
Test status
Simulation time 102963449 ps
CPU time 0.87 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:05 PM PDT 24
Peak memory 198892 kb
Host smart-9075ca11-6721-44fe-b2d5-a7a6ef656b21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734229794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2734229794
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.2278399673
Short name T814
Test name
Test status
Simulation time 36542880 ps
CPU time 0.73 seconds
Started Jul 05 05:51:05 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 199164 kb
Host smart-3e76830d-69a9-4ede-a11a-8dd2209a91d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278399673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.2278399673
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all.3516482390
Short name T148
Test name
Test status
Simulation time 1395893629 ps
CPU time 3.65 seconds
Started Jul 05 05:51:09 PM PDT 24
Finished Jul 05 05:51:14 PM PDT 24
Peak memory 200956 kb
Host smart-1c0eff36-01f0-47c7-b93f-2ee0f0a4befa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516482390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.3516482390
Directory /workspace/11.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all_with_rand_reset.2621823852
Short name T531
Test name
Test status
Simulation time 9185214323 ps
CPU time 29.48 seconds
Started Jul 05 05:51:12 PM PDT 24
Finished Jul 05 05:51:42 PM PDT 24
Peak memory 201088 kb
Host smart-5316f784-7b11-41f9-b8ed-e639d7c1f38e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621823852 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all_with_rand_reset.2621823852
Directory /workspace/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup.872198530
Short name T233
Test name
Test status
Simulation time 125513151 ps
CPU time 0.72 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:04 PM PDT 24
Peak memory 198892 kb
Host smart-bd614b75-da83-4f3e-bfa6-b07dfb888ed4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872198530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.872198530
Directory /workspace/11.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup_reset.463808980
Short name T973
Test name
Test status
Simulation time 213204804 ps
CPU time 1.18 seconds
Started Jul 05 05:51:03 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 199908 kb
Host smart-258d01c1-16bc-4643-ac38-b2a10c80bd87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463808980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.463808980
Directory /workspace/11.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.3852601345
Short name T788
Test name
Test status
Simulation time 88403256 ps
CPU time 0.72 seconds
Started Jul 05 05:51:08 PM PDT 24
Finished Jul 05 05:51:11 PM PDT 24
Peak memory 198564 kb
Host smart-4ae45b51-7b50-43fd-b9e1-9feb309cab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852601345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.3852601345
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.1510429382
Short name T813
Test name
Test status
Simulation time 105031790 ps
CPU time 0.7 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:28 PM PDT 24
Peak memory 198332 kb
Host smart-ae03521a-8e74-4d71-aed2-07d651af31d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510429382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.1510429382
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3175301451
Short name T758
Test name
Test status
Simulation time 37333479 ps
CPU time 0.61 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:05 PM PDT 24
Peak memory 197788 kb
Host smart-c248dd00-0547-47d0-b834-6651f3beff9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175301451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.3175301451
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.1788809797
Short name T987
Test name
Test status
Simulation time 610913780 ps
CPU time 1.02 seconds
Started Jul 05 05:51:22 PM PDT 24
Finished Jul 05 05:51:24 PM PDT 24
Peak memory 198164 kb
Host smart-391adf66-d156-4e5c-a4a3-51d4aeae2658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788809797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.1788809797
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.2451808992
Short name T578
Test name
Test status
Simulation time 47484617 ps
CPU time 0.68 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:08 PM PDT 24
Peak memory 197188 kb
Host smart-27e8a00a-eaff-4bb2-b939-8dbc92a73b38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451808992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.2451808992
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.1359253644
Short name T576
Test name
Test status
Simulation time 24261327 ps
CPU time 0.6 seconds
Started Jul 05 05:51:12 PM PDT 24
Finished Jul 05 05:51:13 PM PDT 24
Peak memory 197864 kb
Host smart-2961c330-0d85-409c-9b31-11e6ccc63c2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359253644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.1359253644
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.2654167066
Short name T684
Test name
Test status
Simulation time 86984635 ps
CPU time 0.67 seconds
Started Jul 05 05:51:15 PM PDT 24
Finished Jul 05 05:51:16 PM PDT 24
Peak memory 201332 kb
Host smart-96fd1899-7167-462f-97bb-df3a1e3b1cd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654167066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.2654167066
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.3369724551
Short name T579
Test name
Test status
Simulation time 305712796 ps
CPU time 0.86 seconds
Started Jul 05 05:51:07 PM PDT 24
Finished Jul 05 05:51:09 PM PDT 24
Peak memory 199228 kb
Host smart-e5467fc6-bfbc-4e50-9a02-73a7f03be453
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369724551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_w
akeup_race.3369724551
Directory /workspace/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.4275949197
Short name T762
Test name
Test status
Simulation time 38971660 ps
CPU time 0.81 seconds
Started Jul 05 05:51:18 PM PDT 24
Finished Jul 05 05:51:20 PM PDT 24
Peak memory 198940 kb
Host smart-0b9456f0-bcd6-4399-9328-750b0ba143bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275949197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.4275949197
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.188191265
Short name T577
Test name
Test status
Simulation time 104458592 ps
CPU time 0.91 seconds
Started Jul 05 05:51:19 PM PDT 24
Finished Jul 05 05:51:20 PM PDT 24
Peak memory 201064 kb
Host smart-841225e3-409c-4b6c-b8b2-06ea3936702d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188191265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.188191265
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.945744554
Short name T328
Test name
Test status
Simulation time 260062782 ps
CPU time 1.06 seconds
Started Jul 05 05:51:03 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 199904 kb
Host smart-9f38e366-7ccf-4924-93cf-b05c01a5a519
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945744554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_c
m_ctrl_config_regwen.945744554
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3611633108
Short name T707
Test name
Test status
Simulation time 818541849 ps
CPU time 2.88 seconds
Started Jul 05 05:51:23 PM PDT 24
Finished Jul 05 05:51:26 PM PDT 24
Peak memory 200872 kb
Host smart-1e915097-dbc9-4c0d-80d1-623be2789f76
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611633108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3611633108
Directory /workspace/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4247367703
Short name T495
Test name
Test status
Simulation time 1068715276 ps
CPU time 2.55 seconds
Started Jul 05 05:51:02 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 200920 kb
Host smart-6450ff3f-8ad4-4bc2-9e49-9225c657192f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247367703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4247367703
Directory /workspace/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3314443894
Short name T924
Test name
Test status
Simulation time 181224484 ps
CPU time 0.91 seconds
Started Jul 05 05:51:17 PM PDT 24
Finished Jul 05 05:51:19 PM PDT 24
Peak memory 199156 kb
Host smart-3f340b25-5cd5-4d8a-a798-53c23d1111cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314443894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3314443894
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.299627763
Short name T768
Test name
Test status
Simulation time 29085927 ps
CPU time 0.7 seconds
Started Jul 05 05:51:18 PM PDT 24
Finished Jul 05 05:51:19 PM PDT 24
Peak memory 199140 kb
Host smart-f6371ca0-e3ef-48e4-b140-788c4577842e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299627763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.299627763
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all.3368925529
Short name T268
Test name
Test status
Simulation time 1464708348 ps
CPU time 5.18 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:13 PM PDT 24
Peak memory 200920 kb
Host smart-4fefb3ac-72fa-4af2-ab3a-592fb3637939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368925529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.3368925529
Directory /workspace/12.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all_with_rand_reset.1493774966
Short name T967
Test name
Test status
Simulation time 17787897376 ps
CPU time 17.07 seconds
Started Jul 05 05:51:25 PM PDT 24
Finished Jul 05 05:51:42 PM PDT 24
Peak memory 201328 kb
Host smart-0b6f7c10-193b-490e-b8da-cf8bfce28dca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493774966 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all_with_rand_reset.1493774966
Directory /workspace/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup.1225612272
Short name T692
Test name
Test status
Simulation time 219084620 ps
CPU time 0.84 seconds
Started Jul 05 05:51:17 PM PDT 24
Finished Jul 05 05:51:19 PM PDT 24
Peak memory 198204 kb
Host smart-2971232c-e340-4c9e-a21f-25ba9ff4258c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225612272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.1225612272
Directory /workspace/12.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup_reset.3125325538
Short name T552
Test name
Test status
Simulation time 109893902 ps
CPU time 0.95 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:05 PM PDT 24
Peak memory 198952 kb
Host smart-8bf65e5c-d7ad-4a6e-8a4e-81169e5d23ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125325538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.3125325538
Directory /workspace/12.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.3894630569
Short name T13
Test name
Test status
Simulation time 25870805 ps
CPU time 0.74 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:09 PM PDT 24
Peak memory 198408 kb
Host smart-2a2b0876-ad8a-4ac4-afed-1495860e24a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894630569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.3894630569
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.2081861100
Short name T178
Test name
Test status
Simulation time 58787533 ps
CPU time 0.84 seconds
Started Jul 05 05:51:25 PM PDT 24
Finished Jul 05 05:51:26 PM PDT 24
Peak memory 198408 kb
Host smart-ad076002-37df-45da-8069-f91907192adc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081861100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.2081861100
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.2870408453
Short name T380
Test name
Test status
Simulation time 32303965 ps
CPU time 0.62 seconds
Started Jul 05 05:51:07 PM PDT 24
Finished Jul 05 05:51:10 PM PDT 24
Peak memory 197072 kb
Host smart-36224186-72f4-4035-9c71-b5ca2d2ea50b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870408453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.2870408453
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.3867454885
Short name T15
Test name
Test status
Simulation time 71545604 ps
CPU time 0.62 seconds
Started Jul 05 05:51:09 PM PDT 24
Finished Jul 05 05:51:11 PM PDT 24
Peak memory 197828 kb
Host smart-c1f51686-c629-4983-8e8b-29fdcb601e27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867454885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.3867454885
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.4024236444
Short name T569
Test name
Test status
Simulation time 44076758 ps
CPU time 0.66 seconds
Started Jul 05 05:51:07 PM PDT 24
Finished Jul 05 05:51:10 PM PDT 24
Peak memory 197828 kb
Host smart-56748012-e4a2-4b65-b407-924a903f5830
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024236444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.4024236444
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.2948302279
Short name T663
Test name
Test status
Simulation time 39202443 ps
CPU time 0.7 seconds
Started Jul 05 05:51:25 PM PDT 24
Finished Jul 05 05:51:27 PM PDT 24
Peak memory 201172 kb
Host smart-2b8ff4d4-a408-4b71-805a-5e093fe66e1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948302279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.2948302279
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_wakeup_race.3599538075
Short name T832
Test name
Test status
Simulation time 49761315 ps
CPU time 0.69 seconds
Started Jul 05 05:51:15 PM PDT 24
Finished Jul 05 05:51:17 PM PDT 24
Peak memory 198936 kb
Host smart-252645f1-9a8f-4564-b429-fcb414a53d66
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599538075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_w
akeup_race.3599538075
Directory /workspace/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.2186633194
Short name T752
Test name
Test status
Simulation time 87242895 ps
CPU time 0.99 seconds
Started Jul 05 05:51:20 PM PDT 24
Finished Jul 05 05:51:22 PM PDT 24
Peak memory 199656 kb
Host smart-9456ad84-03ff-4e1d-a735-1998474e5297
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186633194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.2186633194
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.1770557072
Short name T519
Test name
Test status
Simulation time 145396988 ps
CPU time 0.83 seconds
Started Jul 05 05:51:07 PM PDT 24
Finished Jul 05 05:51:10 PM PDT 24
Peak memory 209224 kb
Host smart-c0939034-957c-43cb-938e-90199a195e6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770557072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.1770557072
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.3381917046
Short name T742
Test name
Test status
Simulation time 334036336 ps
CPU time 0.97 seconds
Started Jul 05 05:51:08 PM PDT 24
Finished Jul 05 05:51:11 PM PDT 24
Peak memory 199840 kb
Host smart-39b77628-8f86-4736-8a93-d9929662b779
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381917046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_
cm_ctrl_config_regwen.3381917046
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2711863986
Short name T950
Test name
Test status
Simulation time 1201691164 ps
CPU time 2.11 seconds
Started Jul 05 05:51:24 PM PDT 24
Finished Jul 05 05:51:27 PM PDT 24
Peak memory 201008 kb
Host smart-6f7852e2-fbf4-4c9e-b9e8-3e27de46324e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711863986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2711863986
Directory /workspace/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1428819385
Short name T981
Test name
Test status
Simulation time 1237061392 ps
CPU time 2.3 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:29 PM PDT 24
Peak memory 200676 kb
Host smart-f9e07504-6bfd-4824-a036-68f17bfc50a2
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428819385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1428819385
Directory /workspace/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2785268888
Short name T709
Test name
Test status
Simulation time 97621554 ps
CPU time 0.87 seconds
Started Jul 05 05:51:10 PM PDT 24
Finished Jul 05 05:51:11 PM PDT 24
Peak memory 199000 kb
Host smart-980ed7a9-5540-40fe-952f-31091fff991e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785268888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2785268888
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.1657085597
Short name T764
Test name
Test status
Simulation time 32581630 ps
CPU time 0.67 seconds
Started Jul 05 05:51:12 PM PDT 24
Finished Jul 05 05:51:13 PM PDT 24
Peak memory 198292 kb
Host smart-30cc12d1-0079-43b1-8d5e-a098be82b316
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657085597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.1657085597
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all.2182643921
Short name T298
Test name
Test status
Simulation time 1003513701 ps
CPU time 2.36 seconds
Started Jul 05 05:51:25 PM PDT 24
Finished Jul 05 05:51:28 PM PDT 24
Peak memory 200944 kb
Host smart-e97fea72-da2b-4350-9f53-48d0d74d60f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182643921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.2182643921
Directory /workspace/13.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup.114443483
Short name T913
Test name
Test status
Simulation time 184258761 ps
CPU time 1.04 seconds
Started Jul 05 05:51:10 PM PDT 24
Finished Jul 05 05:51:11 PM PDT 24
Peak memory 199316 kb
Host smart-4455eac4-46bb-428d-a6a3-dfebd98e49e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114443483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.114443483
Directory /workspace/13.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup_reset.2914371152
Short name T787
Test name
Test status
Simulation time 358124663 ps
CPU time 0.9 seconds
Started Jul 05 05:51:08 PM PDT 24
Finished Jul 05 05:51:10 PM PDT 24
Peak memory 200144 kb
Host smart-441adf42-817e-49ca-bc89-eae68736d8d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914371152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.2914371152
Directory /workspace/13.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.1425235103
Short name T44
Test name
Test status
Simulation time 97419252 ps
CPU time 0.86 seconds
Started Jul 05 05:51:27 PM PDT 24
Finished Jul 05 05:51:29 PM PDT 24
Peak memory 199864 kb
Host smart-6c1845a5-634e-492d-a500-9a9e655e5540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425235103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1425235103
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.355646786
Short name T765
Test name
Test status
Simulation time 76625293 ps
CPU time 0.76 seconds
Started Jul 05 05:51:15 PM PDT 24
Finished Jul 05 05:51:17 PM PDT 24
Peak memory 198488 kb
Host smart-b53e1a2d-2c23-4a5a-a569-14e1719a92f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355646786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disa
ble_rom_integrity_check.355646786
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2013333050
Short name T944
Test name
Test status
Simulation time 30297742 ps
CPU time 0.64 seconds
Started Jul 05 05:51:30 PM PDT 24
Finished Jul 05 05:51:31 PM PDT 24
Peak memory 197052 kb
Host smart-6f26d84b-3c24-4230-80bf-336c0298def8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013333050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.2013333050
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.3491335895
Short name T699
Test name
Test status
Simulation time 609085820 ps
CPU time 0.95 seconds
Started Jul 05 05:51:30 PM PDT 24
Finished Jul 05 05:51:32 PM PDT 24
Peak memory 197816 kb
Host smart-21e2f945-b1af-4c21-abc8-32dc76753084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491335895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.3491335895
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.1840638707
Short name T841
Test name
Test status
Simulation time 67240144 ps
CPU time 0.62 seconds
Started Jul 05 05:51:16 PM PDT 24
Finished Jul 05 05:51:17 PM PDT 24
Peak memory 197848 kb
Host smart-a09a9444-4f0f-467c-866e-8aa6027611bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840638707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.1840638707
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.3277500851
Short name T808
Test name
Test status
Simulation time 24404579 ps
CPU time 0.63 seconds
Started Jul 05 05:51:15 PM PDT 24
Finished Jul 05 05:51:16 PM PDT 24
Peak memory 197868 kb
Host smart-2daa873d-f6f7-43e9-be1a-0133895115c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277500851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.3277500851
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.760198878
Short name T661
Test name
Test status
Simulation time 68722991 ps
CPU time 0.67 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:28 PM PDT 24
Peak memory 201064 kb
Host smart-be7b8b6e-962a-4cbe-9de8-09a3b7261c9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760198878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invali
d.760198878
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.4087128622
Short name T756
Test name
Test status
Simulation time 352228860 ps
CPU time 0.99 seconds
Started Jul 05 05:51:20 PM PDT 24
Finished Jul 05 05:51:22 PM PDT 24
Peak memory 199300 kb
Host smart-303da471-dd98-4e46-a93a-5dd964ac1376
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087128622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_w
akeup_race.4087128622
Directory /workspace/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.1056158635
Short name T984
Test name
Test status
Simulation time 47346023 ps
CPU time 0.76 seconds
Started Jul 05 05:51:12 PM PDT 24
Finished Jul 05 05:51:13 PM PDT 24
Peak memory 198888 kb
Host smart-22490b68-0250-4a98-b5a4-b8cfd3f8be86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056158635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.1056158635
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.711537870
Short name T770
Test name
Test status
Simulation time 119674968 ps
CPU time 0.87 seconds
Started Jul 05 05:51:25 PM PDT 24
Finished Jul 05 05:51:26 PM PDT 24
Peak memory 209296 kb
Host smart-f58ca5ad-aaa7-4336-93c0-95b6eb90b14e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711537870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.711537870
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.2184631901
Short name T605
Test name
Test status
Simulation time 209620592 ps
CPU time 1 seconds
Started Jul 05 05:51:27 PM PDT 24
Finished Jul 05 05:51:29 PM PDT 24
Peak memory 199716 kb
Host smart-c365ab39-ea7d-46c3-9333-0305828f8032
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184631901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_
cm_ctrl_config_regwen.2184631901
Directory /workspace/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.236386262
Short name T464
Test name
Test status
Simulation time 1024278466 ps
CPU time 2.56 seconds
Started Jul 05 05:51:15 PM PDT 24
Finished Jul 05 05:51:19 PM PDT 24
Peak memory 200876 kb
Host smart-27cd1b76-bc8f-48c4-bc92-5934590c609a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236386262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.236386262
Directory /workspace/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.995867759
Short name T700
Test name
Test status
Simulation time 1234234772 ps
CPU time 2.27 seconds
Started Jul 05 05:51:30 PM PDT 24
Finished Jul 05 05:51:33 PM PDT 24
Peak memory 200800 kb
Host smart-5336a302-5918-42c2-b5e2-c353d1bc49ed
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995867759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.995867759
Directory /workspace/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.844848673
Short name T896
Test name
Test status
Simulation time 140827557 ps
CPU time 0.86 seconds
Started Jul 05 05:51:16 PM PDT 24
Finished Jul 05 05:51:17 PM PDT 24
Peak memory 199156 kb
Host smart-1011c3c9-16ed-4f1c-8944-16ceb0be872c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844848673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_
mubi.844848673
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.1366340050
Short name T347
Test name
Test status
Simulation time 55188107 ps
CPU time 0.67 seconds
Started Jul 05 05:51:07 PM PDT 24
Finished Jul 05 05:51:10 PM PDT 24
Peak memory 199100 kb
Host smart-59919abf-45e9-4410-b81f-2238170fcd13
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366340050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.1366340050
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all.3307239144
Short name T293
Test name
Test status
Simulation time 723082465 ps
CPU time 1.83 seconds
Started Jul 05 05:51:25 PM PDT 24
Finished Jul 05 05:51:28 PM PDT 24
Peak memory 200952 kb
Host smart-5fe0e677-75b8-47b7-8dd9-b31b98116124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307239144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.3307239144
Directory /workspace/14.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all_with_rand_reset.3631033670
Short name T74
Test name
Test status
Simulation time 1510053704 ps
CPU time 2.96 seconds
Started Jul 05 05:51:31 PM PDT 24
Finished Jul 05 05:51:34 PM PDT 24
Peak memory 201068 kb
Host smart-966da362-5ba5-432e-859b-47250c5ddd31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631033670 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all_with_rand_reset.3631033670
Directory /workspace/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup.3020701762
Short name T778
Test name
Test status
Simulation time 64089302 ps
CPU time 0.72 seconds
Started Jul 05 05:51:20 PM PDT 24
Finished Jul 05 05:51:21 PM PDT 24
Peak memory 198088 kb
Host smart-28b3c70d-506c-4cb3-b432-0e4ac7138251
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020701762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.3020701762
Directory /workspace/14.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup_reset.3342132702
Short name T678
Test name
Test status
Simulation time 204656896 ps
CPU time 1.19 seconds
Started Jul 05 05:51:15 PM PDT 24
Finished Jul 05 05:51:17 PM PDT 24
Peak memory 199976 kb
Host smart-987d6848-f975-484c-b6cb-88df9d1fbe6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342132702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.3342132702
Directory /workspace/14.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.1584100
Short name T473
Test name
Test status
Simulation time 33461560 ps
CPU time 0.78 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:28 PM PDT 24
Peak memory 199844 kb
Host smart-e816cb3e-868d-4ff4-8d3a-91440ab860f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1584100
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.3821032977
Short name T953
Test name
Test status
Simulation time 69664276 ps
CPU time 0.69 seconds
Started Jul 05 05:51:23 PM PDT 24
Finished Jul 05 05:51:25 PM PDT 24
Peak memory 198356 kb
Host smart-63fa2bc3-dd82-4afb-9986-d8ac144f6925
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821032977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.3821032977
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.1739833370
Short name T685
Test name
Test status
Simulation time 39773374 ps
CPU time 0.63 seconds
Started Jul 05 05:51:27 PM PDT 24
Finished Jul 05 05:51:29 PM PDT 24
Peak memory 197736 kb
Host smart-3edf7cd4-4c8b-4071-88ad-8074e15dcbee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739833370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.1739833370
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.4079091319
Short name T170
Test name
Test status
Simulation time 305158894 ps
CPU time 0.96 seconds
Started Jul 05 05:51:17 PM PDT 24
Finished Jul 05 05:51:18 PM PDT 24
Peak memory 197848 kb
Host smart-1745f030-d41b-4d06-a986-10d4782c9ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079091319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.4079091319
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.3780458344
Short name T547
Test name
Test status
Simulation time 38327448 ps
CPU time 0.6 seconds
Started Jul 05 05:51:14 PM PDT 24
Finished Jul 05 05:51:15 PM PDT 24
Peak memory 197832 kb
Host smart-f47663e0-1462-485f-8df1-d67042fdde81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780458344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.3780458344
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.4009995807
Short name T212
Test name
Test status
Simulation time 129491744 ps
CPU time 0.61 seconds
Started Jul 05 05:51:25 PM PDT 24
Finished Jul 05 05:51:26 PM PDT 24
Peak memory 197860 kb
Host smart-5502d8ce-c853-40c4-81e9-0b9995c4d4f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009995807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.4009995807
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.2426183243
Short name T629
Test name
Test status
Simulation time 51559770 ps
CPU time 0.69 seconds
Started Jul 05 05:51:14 PM PDT 24
Finished Jul 05 05:51:15 PM PDT 24
Peak memory 200980 kb
Host smart-923d055f-baf9-42c0-b960-cfd3d3cdfd9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426183243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.2426183243
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.3552174469
Short name T85
Test name
Test status
Simulation time 62634662 ps
CPU time 0.65 seconds
Started Jul 05 05:51:13 PM PDT 24
Finished Jul 05 05:51:14 PM PDT 24
Peak memory 198944 kb
Host smart-76b71e70-09f2-4ad7-ba75-2d5c3031d3d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552174469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_w
akeup_race.3552174469
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.542658113
Short name T574
Test name
Test status
Simulation time 82111033 ps
CPU time 0.95 seconds
Started Jul 05 05:51:30 PM PDT 24
Finished Jul 05 05:51:32 PM PDT 24
Peak memory 199488 kb
Host smart-1957989f-c0a1-4307-ac0a-535bd2578733
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542658113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.542658113
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.2709442104
Short name T910
Test name
Test status
Simulation time 119021489 ps
CPU time 0.82 seconds
Started Jul 05 05:51:19 PM PDT 24
Finished Jul 05 05:51:20 PM PDT 24
Peak memory 209480 kb
Host smart-2cbe5c31-f582-4dcc-8f01-73532f22dd52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709442104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.2709442104
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.858992423
Short name T292
Test name
Test status
Simulation time 160209476 ps
CPU time 0.94 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:28 PM PDT 24
Peak memory 198684 kb
Host smart-42c2af52-03c0-4f45-8f0a-6ee71f7747ca
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858992423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_c
m_ctrl_config_regwen.858992423
Directory /workspace/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.153917254
Short name T96
Test name
Test status
Simulation time 834868049 ps
CPU time 3.01 seconds
Started Jul 05 05:51:21 PM PDT 24
Finished Jul 05 05:51:25 PM PDT 24
Peak memory 200952 kb
Host smart-c5b33181-d10e-4fbb-90dc-23c91d5b46fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153917254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.153917254
Directory /workspace/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2764943355
Short name T994
Test name
Test status
Simulation time 896088355 ps
CPU time 3.31 seconds
Started Jul 05 05:51:14 PM PDT 24
Finished Jul 05 05:51:17 PM PDT 24
Peak memory 200944 kb
Host smart-9b113bd2-1975-49bd-bc69-320af8a1dd40
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764943355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2764943355
Directory /workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.68840215
Short name T454
Test name
Test status
Simulation time 76966188 ps
CPU time 0.94 seconds
Started Jul 05 05:51:14 PM PDT 24
Finished Jul 05 05:51:15 PM PDT 24
Peak memory 199204 kb
Host smart-1ff6e49e-451e-4ed2-97e8-bbf7db65bb77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68840215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.68840215
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.1391465745
Short name T889
Test name
Test status
Simulation time 197449284 ps
CPU time 0.63 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:28 PM PDT 24
Peak memory 198332 kb
Host smart-b1597042-2f3a-4a09-acbc-8e933c50395f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391465745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.1391465745
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all.3923524255
Short name T595
Test name
Test status
Simulation time 1969194294 ps
CPU time 2.94 seconds
Started Jul 05 05:51:25 PM PDT 24
Finished Jul 05 05:51:28 PM PDT 24
Peak memory 200948 kb
Host smart-1c29699d-b166-4aa6-a7f8-2562854e13f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923524255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.3923524255
Directory /workspace/15.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all_with_rand_reset.1650037285
Short name T57
Test name
Test status
Simulation time 9320847319 ps
CPU time 27.99 seconds
Started Jul 05 05:51:25 PM PDT 24
Finished Jul 05 05:51:54 PM PDT 24
Peak memory 201132 kb
Host smart-2f2e68b3-fcf2-448a-a759-5dea8e5b4372
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650037285 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all_with_rand_reset.1650037285
Directory /workspace/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup.1919494800
Short name T336
Test name
Test status
Simulation time 160830742 ps
CPU time 0.78 seconds
Started Jul 05 05:51:15 PM PDT 24
Finished Jul 05 05:51:16 PM PDT 24
Peak memory 198928 kb
Host smart-b3fa488c-c1ad-4372-907c-35d97618ead3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919494800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.1919494800
Directory /workspace/15.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup_reset.1433487814
Short name T224
Test name
Test status
Simulation time 352691694 ps
CPU time 1.45 seconds
Started Jul 05 05:51:27 PM PDT 24
Finished Jul 05 05:51:29 PM PDT 24
Peak memory 200768 kb
Host smart-0c251040-682d-462c-8caf-008959c96f46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433487814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.1433487814
Directory /workspace/15.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.1589467048
Short name T494
Test name
Test status
Simulation time 70970107 ps
CPU time 0.76 seconds
Started Jul 05 05:51:23 PM PDT 24
Finished Jul 05 05:51:25 PM PDT 24
Peak memory 198284 kb
Host smart-0e5ac470-15a6-4dff-9da3-5917777c75a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589467048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.1589467048
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.392736587
Short name T308
Test name
Test status
Simulation time 69035057 ps
CPU time 0.71 seconds
Started Jul 05 05:51:28 PM PDT 24
Finished Jul 05 05:51:30 PM PDT 24
Peak memory 198944 kb
Host smart-1097ebe2-8725-4891-a798-da676fc42770
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392736587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disa
ble_rom_integrity_check.392736587
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.4040701686
Short name T374
Test name
Test status
Simulation time 49312696 ps
CPU time 0.58 seconds
Started Jul 05 05:51:38 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 197792 kb
Host smart-f405bbd9-1d5b-4ffd-b37f-9b9ded12b1d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040701686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.4040701686
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.303060719
Short name T535
Test name
Test status
Simulation time 692472057 ps
CPU time 0.95 seconds
Started Jul 05 05:51:39 PM PDT 24
Finished Jul 05 05:51:41 PM PDT 24
Peak memory 197860 kb
Host smart-9124f2ed-cfef-4a2a-9a39-141e9cf66b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303060719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.303060719
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.659278059
Short name T645
Test name
Test status
Simulation time 38996748 ps
CPU time 0.62 seconds
Started Jul 05 05:51:37 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 197788 kb
Host smart-f54e23c9-1b5f-4352-9499-7ee4dbc4aec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659278059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.659278059
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.3401913175
Short name T230
Test name
Test status
Simulation time 60210447 ps
CPU time 0.66 seconds
Started Jul 05 05:51:27 PM PDT 24
Finished Jul 05 05:51:29 PM PDT 24
Peak memory 198172 kb
Host smart-c07e5cf2-8cbd-42d6-aa56-7bd6f39aea28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401913175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.3401913175
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.2243574256
Short name T677
Test name
Test status
Simulation time 58479556 ps
CPU time 0.67 seconds
Started Jul 05 05:51:23 PM PDT 24
Finished Jul 05 05:51:24 PM PDT 24
Peak memory 201100 kb
Host smart-d446a593-1514-42e6-b462-74acbd7acecd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243574256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.2243574256
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_wakeup_race.3778374594
Short name T241
Test name
Test status
Simulation time 136108729 ps
CPU time 0.89 seconds
Started Jul 05 05:51:33 PM PDT 24
Finished Jul 05 05:51:36 PM PDT 24
Peak memory 198084 kb
Host smart-0104a354-6b1f-434d-9746-c596b00de972
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778374594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_w
akeup_race.3778374594
Directory /workspace/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.2614230662
Short name T724
Test name
Test status
Simulation time 136299566 ps
CPU time 0.78 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:28 PM PDT 24
Peak memory 198328 kb
Host smart-24237706-e917-462e-a838-edff7fa9187e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614230662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.2614230662
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.3637564345
Short name T872
Test name
Test status
Simulation time 144335926 ps
CPU time 0.82 seconds
Started Jul 05 05:51:29 PM PDT 24
Finished Jul 05 05:51:31 PM PDT 24
Peak memory 209260 kb
Host smart-bd254a06-1bcc-48e2-87a6-d154cf66036c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637564345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.3637564345
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.1392586722
Short name T717
Test name
Test status
Simulation time 251200074 ps
CPU time 0.9 seconds
Started Jul 05 05:51:41 PM PDT 24
Finished Jul 05 05:51:42 PM PDT 24
Peak memory 199668 kb
Host smart-501f780b-c533-4da8-a992-eb758a88dea2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392586722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_
cm_ctrl_config_regwen.1392586722
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1312786729
Short name T754
Test name
Test status
Simulation time 810138058 ps
CPU time 2.76 seconds
Started Jul 05 05:51:34 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 200860 kb
Host smart-3e1baeed-3098-4010-8a53-8d4fd5997f8f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312786729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1312786729
Directory /workspace/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.539986661
Short name T627
Test name
Test status
Simulation time 884091008 ps
CPU time 2.66 seconds
Started Jul 05 05:51:36 PM PDT 24
Finished Jul 05 05:51:40 PM PDT 24
Peak memory 200848 kb
Host smart-ec99242c-4468-4dff-a0ae-9983d24139a4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539986661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.539986661
Directory /workspace/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2374266658
Short name T197
Test name
Test status
Simulation time 372944993 ps
CPU time 0.84 seconds
Started Jul 05 05:51:34 PM PDT 24
Finished Jul 05 05:51:36 PM PDT 24
Peak memory 198976 kb
Host smart-0f0f12ee-5f09-4069-ba72-25f540e6f9fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374266658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2374266658
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.3709171716
Short name T957
Test name
Test status
Simulation time 129838100 ps
CPU time 0.65 seconds
Started Jul 05 05:51:27 PM PDT 24
Finished Jul 05 05:51:29 PM PDT 24
Peak memory 198328 kb
Host smart-03c47ab2-5c2c-45cf-90a4-adb892120fc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709171716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3709171716
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all.3400058034
Short name T124
Test name
Test status
Simulation time 1097905249 ps
CPU time 3.27 seconds
Started Jul 05 05:51:23 PM PDT 24
Finished Jul 05 05:51:27 PM PDT 24
Peak memory 200648 kb
Host smart-7abb0d1c-8da2-4c4b-952f-623adfcbf93c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400058034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.3400058034
Directory /workspace/16.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all_with_rand_reset.4071614541
Short name T99
Test name
Test status
Simulation time 8141917419 ps
CPU time 15.64 seconds
Started Jul 05 05:51:29 PM PDT 24
Finished Jul 05 05:51:45 PM PDT 24
Peak memory 201128 kb
Host smart-d0d82b8e-d605-476f-baf8-40b21a3f254b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071614541 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all_with_rand_reset.4071614541
Directory /workspace/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup.3885474149
Short name T261
Test name
Test status
Simulation time 204545824 ps
CPU time 1.07 seconds
Started Jul 05 05:52:23 PM PDT 24
Finished Jul 05 05:52:26 PM PDT 24
Peak memory 199428 kb
Host smart-e2606a54-46f4-453d-8e34-cc65fa99a9c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885474149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.3885474149
Directory /workspace/16.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup_reset.2093911022
Short name T526
Test name
Test status
Simulation time 202160028 ps
CPU time 1.11 seconds
Started Jul 05 05:51:28 PM PDT 24
Finished Jul 05 05:51:30 PM PDT 24
Peak memory 199944 kb
Host smart-7cd8d2d3-d13b-4a0a-b76e-726f4666322b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093911022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.2093911022
Directory /workspace/16.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.744991436
Short name T929
Test name
Test status
Simulation time 76455529 ps
CPU time 0.78 seconds
Started Jul 05 05:51:41 PM PDT 24
Finished Jul 05 05:51:43 PM PDT 24
Peak memory 198572 kb
Host smart-d64c7e95-e112-4385-9120-fb564e239123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744991436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.744991436
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.3671730657
Short name T389
Test name
Test status
Simulation time 54498597 ps
CPU time 0.75 seconds
Started Jul 05 05:51:29 PM PDT 24
Finished Jul 05 05:51:30 PM PDT 24
Peak memory 198276 kb
Host smart-8f78deee-4cdd-4558-9b0c-0baa8861f188
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671730657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.3671730657
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.3837830643
Short name T486
Test name
Test status
Simulation time 30374808 ps
CPU time 0.67 seconds
Started Jul 05 05:51:54 PM PDT 24
Finished Jul 05 05:51:57 PM PDT 24
Peak memory 197076 kb
Host smart-50643358-9d1c-45a1-871f-583c030e02a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837830643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.3837830643
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.1440839982
Short name T647
Test name
Test status
Simulation time 162347840 ps
CPU time 0.96 seconds
Started Jul 05 05:51:28 PM PDT 24
Finished Jul 05 05:51:30 PM PDT 24
Peak memory 197852 kb
Host smart-9f646f2d-6e45-41c1-a24c-4e8254bf23d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440839982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.1440839982
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.349069812
Short name T475
Test name
Test status
Simulation time 57600115 ps
CPU time 0.61 seconds
Started Jul 05 05:51:17 PM PDT 24
Finished Jul 05 05:51:18 PM PDT 24
Peak memory 197768 kb
Host smart-13a6e64b-e821-49f4-aa2d-af6957fe18ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349069812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.349069812
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.1462279930
Short name T654
Test name
Test status
Simulation time 82172599 ps
CPU time 0.62 seconds
Started Jul 05 05:51:29 PM PDT 24
Finished Jul 05 05:51:30 PM PDT 24
Peak memory 198172 kb
Host smart-c50fde62-1a5c-439c-b9c3-a37238b8cb59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462279930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.1462279930
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.2676227922
Short name T887
Test name
Test status
Simulation time 67439960 ps
CPU time 0.71 seconds
Started Jul 05 05:51:28 PM PDT 24
Finished Jul 05 05:51:30 PM PDT 24
Peak memory 201136 kb
Host smart-b14a025a-9c18-4bbb-89ed-acbd83530c2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676227922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.2676227922
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.2845823311
Short name T662
Test name
Test status
Simulation time 105903932 ps
CPU time 0.68 seconds
Started Jul 05 05:51:37 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 198120 kb
Host smart-f4cf4bf8-150b-4ca3-8714-02154df08a53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845823311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_w
akeup_race.2845823311
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.3073618891
Short name T651
Test name
Test status
Simulation time 75758452 ps
CPU time 0.86 seconds
Started Jul 05 05:51:46 PM PDT 24
Finished Jul 05 05:51:47 PM PDT 24
Peak memory 198820 kb
Host smart-6131ad12-ca66-47ad-aed6-b2e4a620c3c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073618891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.3073618891
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.3031185541
Short name T809
Test name
Test status
Simulation time 126404020 ps
CPU time 0.84 seconds
Started Jul 05 05:51:31 PM PDT 24
Finished Jul 05 05:51:32 PM PDT 24
Peak memory 209208 kb
Host smart-01a6a0f5-b5ca-444c-8738-b483c86efc2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031185541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.3031185541
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.3449161150
Short name T608
Test name
Test status
Simulation time 251136746 ps
CPU time 1.02 seconds
Started Jul 05 05:51:31 PM PDT 24
Finished Jul 05 05:51:33 PM PDT 24
Peak memory 199892 kb
Host smart-181ca058-e25d-47b8-a89e-af71f54b8f44
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449161150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_
cm_ctrl_config_regwen.3449161150
Directory /workspace/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2589723104
Short name T721
Test name
Test status
Simulation time 859819454 ps
CPU time 3.11 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:30 PM PDT 24
Peak memory 200852 kb
Host smart-25af4bc7-2711-47b9-8b21-3136ef3fc5c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589723104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2589723104
Directory /workspace/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3427068605
Short name T702
Test name
Test status
Simulation time 1350923011 ps
CPU time 2.4 seconds
Started Jul 05 05:51:34 PM PDT 24
Finished Jul 05 05:51:37 PM PDT 24
Peak memory 200908 kb
Host smart-10305fb1-7207-44b3-b639-9065a5e8baa9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427068605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3427068605
Directory /workspace/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1034136662
Short name T497
Test name
Test status
Simulation time 142851365 ps
CPU time 0.87 seconds
Started Jul 05 05:51:41 PM PDT 24
Finished Jul 05 05:51:43 PM PDT 24
Peak memory 199152 kb
Host smart-f1d3577d-c50e-48cd-98f6-4909c3a63154
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034136662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1034136662
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.1291068227
Short name T238
Test name
Test status
Simulation time 85234595 ps
CPU time 0.65 seconds
Started Jul 05 05:51:18 PM PDT 24
Finished Jul 05 05:51:19 PM PDT 24
Peak memory 198280 kb
Host smart-5043404f-f003-40b0-b30e-9a2f4333a3b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291068227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.1291068227
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all.2953771055
Short name T39
Test name
Test status
Simulation time 3678805018 ps
CPU time 4.31 seconds
Started Jul 05 05:51:29 PM PDT 24
Finished Jul 05 05:51:35 PM PDT 24
Peak memory 201060 kb
Host smart-2484032f-fd6c-4db0-bcc7-c1a4fb9f72a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953771055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.2953771055
Directory /workspace/17.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all_with_rand_reset.391876775
Short name T51
Test name
Test status
Simulation time 1970085708 ps
CPU time 7.13 seconds
Started Jul 05 05:51:29 PM PDT 24
Finished Jul 05 05:51:37 PM PDT 24
Peak memory 201084 kb
Host smart-7762dd54-ab4d-4119-8065-ec64463acb67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391876775 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all_with_rand_reset.391876775
Directory /workspace/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup.2825206897
Short name T773
Test name
Test status
Simulation time 110005887 ps
CPU time 0.78 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:32 PM PDT 24
Peak memory 198228 kb
Host smart-9f5079e9-4d28-4a84-8a61-bc4efde4bcb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825206897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.2825206897
Directory /workspace/17.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup_reset.826158141
Short name T912
Test name
Test status
Simulation time 331320928 ps
CPU time 1.35 seconds
Started Jul 05 05:51:29 PM PDT 24
Finished Jul 05 05:51:32 PM PDT 24
Peak memory 200656 kb
Host smart-72635067-5ee8-4355-bd26-88a9a27f5f10
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826158141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.826158141
Directory /workspace/17.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.1603705514
Short name T113
Test name
Test status
Simulation time 68939529 ps
CPU time 0.86 seconds
Started Jul 05 05:51:23 PM PDT 24
Finished Jul 05 05:51:25 PM PDT 24
Peak memory 200080 kb
Host smart-20da7585-2813-452c-99a2-a2328aa5a324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603705514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.1603705514
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.3802378291
Short name T921
Test name
Test status
Simulation time 70243040 ps
CPU time 0.72 seconds
Started Jul 05 05:51:36 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 198856 kb
Host smart-1a020e82-0c4e-4cc6-8a7e-423cf24541f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802378291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.3802378291
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.3865697203
Short name T407
Test name
Test status
Simulation time 38048005 ps
CPU time 0.59 seconds
Started Jul 05 05:51:36 PM PDT 24
Finished Jul 05 05:51:38 PM PDT 24
Peak memory 197760 kb
Host smart-c837cedb-3dd4-4516-b8b4-2ecaed293976
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865697203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.3865697203
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.80388062
Short name T404
Test name
Test status
Simulation time 650075574 ps
CPU time 0.97 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:28 PM PDT 24
Peak memory 197896 kb
Host smart-27d3a62b-06e1-485d-9e25-68802bf5dcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80388062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.80388062
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.4281678498
Short name T753
Test name
Test status
Simulation time 62026238 ps
CPU time 0.61 seconds
Started Jul 05 05:51:29 PM PDT 24
Finished Jul 05 05:51:31 PM PDT 24
Peak memory 197184 kb
Host smart-84dbeaf6-17a0-47cb-9019-1225c8257492
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281678498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.4281678498
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.3728574374
Short name T603
Test name
Test status
Simulation time 30751291 ps
CPU time 0.6 seconds
Started Jul 05 05:51:29 PM PDT 24
Finished Jul 05 05:51:30 PM PDT 24
Peak memory 197848 kb
Host smart-a7a2b646-1fbc-4e32-bb66-358fa4762bcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728574374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.3728574374
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.72478738
Short name T542
Test name
Test status
Simulation time 67332477 ps
CPU time 0.67 seconds
Started Jul 05 05:51:32 PM PDT 24
Finished Jul 05 05:51:34 PM PDT 24
Peak memory 201164 kb
Host smart-25591d5a-a3e2-4d7e-bba8-b3634d894980
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72478738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invalid
.72478738
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.3129700160
Short name T836
Test name
Test status
Simulation time 230807024 ps
CPU time 0.98 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:28 PM PDT 24
Peak memory 199464 kb
Host smart-9142cd60-5011-44a4-a5e2-ce54a43eccb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129700160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_w
akeup_race.3129700160
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.541896938
Short name T586
Test name
Test status
Simulation time 104629863 ps
CPU time 0.93 seconds
Started Jul 05 05:51:30 PM PDT 24
Finished Jul 05 05:51:32 PM PDT 24
Peak memory 199584 kb
Host smart-e2af2cb8-dea8-4b01-bdf5-68d6d7ccbab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541896938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.541896938
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.228034193
Short name T508
Test name
Test status
Simulation time 158191320 ps
CPU time 0.84 seconds
Started Jul 05 05:51:26 PM PDT 24
Finished Jul 05 05:51:27 PM PDT 24
Peak memory 209312 kb
Host smart-89dbde40-2517-4cb0-a253-6c67b51f8c77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228034193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.228034193
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.296259424
Short name T619
Test name
Test status
Simulation time 219871724 ps
CPU time 1.15 seconds
Started Jul 05 05:51:29 PM PDT 24
Finished Jul 05 05:51:32 PM PDT 24
Peak memory 199888 kb
Host smart-df33eb75-5932-4f4f-bbfb-98f18f47e749
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296259424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_c
m_ctrl_config_regwen.296259424
Directory /workspace/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2580688088
Short name T704
Test name
Test status
Simulation time 1144757771 ps
CPU time 2.2 seconds
Started Jul 05 05:51:49 PM PDT 24
Finished Jul 05 05:51:52 PM PDT 24
Peak memory 200924 kb
Host smart-b46b6721-1ab3-4189-8181-33137d803d3e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580688088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2580688088
Directory /workspace/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2901355806
Short name T503
Test name
Test status
Simulation time 1066186288 ps
CPU time 2.1 seconds
Started Jul 05 05:51:37 PM PDT 24
Finished Jul 05 05:51:40 PM PDT 24
Peak memory 200952 kb
Host smart-3786d6c2-e64b-40f6-b921-4ec7cd560a97
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901355806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2901355806
Directory /workspace/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.2609141249
Short name T322
Test name
Test status
Simulation time 91733463 ps
CPU time 0.84 seconds
Started Jul 05 05:51:33 PM PDT 24
Finished Jul 05 05:51:35 PM PDT 24
Peak memory 198936 kb
Host smart-10a120fb-dbfb-4891-b594-28237395b047
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609141249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2609141249
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.1364645315
Short name T689
Test name
Test status
Simulation time 26866442 ps
CPU time 0.69 seconds
Started Jul 05 05:51:34 PM PDT 24
Finished Jul 05 05:51:37 PM PDT 24
Peak memory 199136 kb
Host smart-6ebbf0bf-ddf0-43d6-8c4e-8b2971a5f60a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364645315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.1364645315
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all.1885631192
Short name T152
Test name
Test status
Simulation time 904075406 ps
CPU time 2.7 seconds
Started Jul 05 05:51:30 PM PDT 24
Finished Jul 05 05:51:33 PM PDT 24
Peak memory 200972 kb
Host smart-a0d9f0e1-7ed0-403c-8dbe-af9c60cdd4b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885631192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.1885631192
Directory /workspace/18.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.3983060271
Short name T262
Test name
Test status
Simulation time 179980382 ps
CPU time 1.05 seconds
Started Jul 05 05:51:39 PM PDT 24
Finished Jul 05 05:51:40 PM PDT 24
Peak memory 198364 kb
Host smart-24a31ba2-8b9f-4984-a6bb-a556eb4cb246
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983060271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.3983060271
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup_reset.3421620038
Short name T348
Test name
Test status
Simulation time 208439327 ps
CPU time 0.98 seconds
Started Jul 05 05:51:46 PM PDT 24
Finished Jul 05 05:51:47 PM PDT 24
Peak memory 199896 kb
Host smart-375ae334-9843-4687-913b-f77d560d0e00
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421620038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.3421620038
Directory /workspace/18.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.1441861335
Short name T266
Test name
Test status
Simulation time 206818417 ps
CPU time 0.8 seconds
Started Jul 05 05:51:37 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 199732 kb
Host smart-5f4ce98f-0f56-4031-9da4-94a52c19520c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441861335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.1441861335
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.2559542685
Short name T192
Test name
Test status
Simulation time 69610941 ps
CPU time 0.68 seconds
Started Jul 05 05:51:34 PM PDT 24
Finished Jul 05 05:51:37 PM PDT 24
Peak memory 198852 kb
Host smart-9b567397-d644-4f95-b9e6-676bce67b4a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559542685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.2559542685
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1325140589
Short name T540
Test name
Test status
Simulation time 28337600 ps
CPU time 0.68 seconds
Started Jul 05 05:51:35 PM PDT 24
Finished Jul 05 05:51:38 PM PDT 24
Peak memory 197036 kb
Host smart-b8065ea6-606a-41e2-9b51-626dc0546c8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325140589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.1325140589
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.4087639824
Short name T590
Test name
Test status
Simulation time 598179934 ps
CPU time 0.95 seconds
Started Jul 05 05:51:40 PM PDT 24
Finished Jul 05 05:51:42 PM PDT 24
Peak memory 198148 kb
Host smart-641bc6e4-703a-45dd-b4d0-9d6ab05f5adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087639824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.4087639824
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.435800377
Short name T388
Test name
Test status
Simulation time 58143375 ps
CPU time 0.6 seconds
Started Jul 05 05:51:32 PM PDT 24
Finished Jul 05 05:51:34 PM PDT 24
Peak memory 197136 kb
Host smart-dd5a2245-0011-43be-af1f-08192e9db03a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435800377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.435800377
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.4045429130
Short name T899
Test name
Test status
Simulation time 50152602 ps
CPU time 0.68 seconds
Started Jul 05 05:51:42 PM PDT 24
Finished Jul 05 05:51:43 PM PDT 24
Peak memory 197848 kb
Host smart-3421be5d-2ae7-4573-a97e-292f8a875351
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045429130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.4045429130
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.2625167135
Short name T277
Test name
Test status
Simulation time 67139108 ps
CPU time 0.66 seconds
Started Jul 05 05:51:32 PM PDT 24
Finished Jul 05 05:51:33 PM PDT 24
Peak memory 201092 kb
Host smart-4bb90896-1481-4f6f-b294-18c6960834fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625167135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.2625167135
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.3082623046
Short name T615
Test name
Test status
Simulation time 264311713 ps
CPU time 0.84 seconds
Started Jul 05 05:51:37 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 199180 kb
Host smart-92a5b6df-da20-4d1d-9357-4d507d7e1497
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082623046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_w
akeup_race.3082623046
Directory /workspace/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.2343021226
Short name T804
Test name
Test status
Simulation time 180435829 ps
CPU time 0.87 seconds
Started Jul 05 05:51:36 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 199620 kb
Host smart-d0ee2155-f47d-4e07-b831-934a8047a311
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343021226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.2343021226
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.3281704587
Short name T305
Test name
Test status
Simulation time 172180687 ps
CPU time 0.78 seconds
Started Jul 05 05:51:48 PM PDT 24
Finished Jul 05 05:51:50 PM PDT 24
Peak memory 209308 kb
Host smart-8e63e03c-46da-4424-a9b0-fc6d67e8af68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281704587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.3281704587
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.3337257559
Short name T968
Test name
Test status
Simulation time 160153122 ps
CPU time 0.98 seconds
Started Jul 05 05:51:39 PM PDT 24
Finished Jul 05 05:51:41 PM PDT 24
Peak memory 198908 kb
Host smart-adee6c33-d78b-4389-8b12-29171db03f6e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337257559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_
cm_ctrl_config_regwen.3337257559
Directory /workspace/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3268676671
Short name T333
Test name
Test status
Simulation time 711276547 ps
CPU time 2.99 seconds
Started Jul 05 05:51:34 PM PDT 24
Finished Jul 05 05:51:43 PM PDT 24
Peak memory 200888 kb
Host smart-cf6f3624-9d31-48a8-be7a-b39a36edf1fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268676671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3268676671
Directory /workspace/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.385569491
Short name T936
Test name
Test status
Simulation time 856623502 ps
CPU time 3.11 seconds
Started Jul 05 05:51:37 PM PDT 24
Finished Jul 05 05:51:41 PM PDT 24
Peak memory 200844 kb
Host smart-a1d54e66-c56e-4097-a960-39eba0cba1bf
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385569491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.385569491
Directory /workspace/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3141072575
Short name T291
Test name
Test status
Simulation time 174523787 ps
CPU time 0.91 seconds
Started Jul 05 05:51:34 PM PDT 24
Finished Jul 05 05:51:37 PM PDT 24
Peak memory 199080 kb
Host smart-b6c554e7-493d-4676-9634-9823c2885394
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141072575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3141072575
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.600111012
Short name T345
Test name
Test status
Simulation time 31269742 ps
CPU time 0.7 seconds
Started Jul 05 05:51:29 PM PDT 24
Finished Jul 05 05:51:31 PM PDT 24
Peak memory 199184 kb
Host smart-3372ecb0-d9b5-4af4-bf85-317af6518e78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600111012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.600111012
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all.2762556404
Short name T733
Test name
Test status
Simulation time 354717225 ps
CPU time 0.95 seconds
Started Jul 05 05:51:32 PM PDT 24
Finished Jul 05 05:51:34 PM PDT 24
Peak memory 199924 kb
Host smart-e447868f-7637-4ce4-9cfc-fc1fbf5badb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762556404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.2762556404
Directory /workspace/19.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all_with_rand_reset.2541435360
Short name T91
Test name
Test status
Simulation time 4011228603 ps
CPU time 12.8 seconds
Started Jul 05 05:51:35 PM PDT 24
Finished Jul 05 05:51:49 PM PDT 24
Peak memory 201144 kb
Host smart-030392bc-702f-4491-9778-a65078892a97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541435360 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all_with_rand_reset.2541435360
Directory /workspace/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup.2924462647
Short name T679
Test name
Test status
Simulation time 257239067 ps
CPU time 0.87 seconds
Started Jul 05 05:51:37 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 199432 kb
Host smart-c3b407c9-2652-42fe-bcd7-8ae4d847a30e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924462647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.2924462647
Directory /workspace/19.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup_reset.2329670166
Short name T825
Test name
Test status
Simulation time 177511575 ps
CPU time 0.94 seconds
Started Jul 05 05:51:34 PM PDT 24
Finished Jul 05 05:51:37 PM PDT 24
Peak memory 199952 kb
Host smart-ea3c4164-6fee-4e59-abef-b38cf40bf99d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329670166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.2329670166
Directory /workspace/19.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.2477747948
Short name T14
Test name
Test status
Simulation time 36692153 ps
CPU time 0.86 seconds
Started Jul 05 05:50:46 PM PDT 24
Finished Jul 05 05:50:48 PM PDT 24
Peak memory 199752 kb
Host smart-26f0e864-5fc9-4570-931b-6c2ee8cffb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477747948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.2477747948
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.3445561269
Short name T560
Test name
Test status
Simulation time 69377871 ps
CPU time 0.68 seconds
Started Jul 05 05:50:51 PM PDT 24
Finished Jul 05 05:50:54 PM PDT 24
Peak memory 198868 kb
Host smart-07ef4400-733a-4a7f-9670-b17068bcd9a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445561269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.3445561269
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1672424970
Short name T173
Test name
Test status
Simulation time 33039432 ps
CPU time 0.63 seconds
Started Jul 05 05:50:43 PM PDT 24
Finished Jul 05 05:50:44 PM PDT 24
Peak memory 197820 kb
Host smart-959702ac-e011-48c0-b63d-9bca1201c8e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672424970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.1672424970
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.959414619
Short name T434
Test name
Test status
Simulation time 2132879588 ps
CPU time 0.95 seconds
Started Jul 05 05:50:51 PM PDT 24
Finished Jul 05 05:50:54 PM PDT 24
Peak memory 198140 kb
Host smart-c1925245-b48e-4827-8065-a4216b061b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959414619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.959414619
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.736703073
Short name T820
Test name
Test status
Simulation time 36140489 ps
CPU time 0.6 seconds
Started Jul 05 05:50:48 PM PDT 24
Finished Jul 05 05:50:50 PM PDT 24
Peak memory 197812 kb
Host smart-2f065a39-2c7c-4472-970a-e7d093e38adb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736703073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.736703073
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.1183610251
Short name T726
Test name
Test status
Simulation time 32435481 ps
CPU time 0.65 seconds
Started Jul 05 05:50:48 PM PDT 24
Finished Jul 05 05:50:51 PM PDT 24
Peak memory 197828 kb
Host smart-ec63cb7f-ad86-4b7a-9e26-9066cba81e28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183610251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1183610251
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2360082446
Short name T961
Test name
Test status
Simulation time 44594508 ps
CPU time 0.71 seconds
Started Jul 05 05:50:40 PM PDT 24
Finished Jul 05 05:50:43 PM PDT 24
Peak memory 201128 kb
Host smart-8af551fe-2199-470f-bbea-ca9e84b07bd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360082446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2360082446
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.2309094946
Short name T693
Test name
Test status
Simulation time 306789235 ps
CPU time 0.82 seconds
Started Jul 05 05:50:49 PM PDT 24
Finished Jul 05 05:50:52 PM PDT 24
Peak memory 199316 kb
Host smart-bbace1e5-1077-4399-bb54-c39c38fa3f3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309094946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wa
keup_race.2309094946
Directory /workspace/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.2969140216
Short name T455
Test name
Test status
Simulation time 155176832 ps
CPU time 0.82 seconds
Started Jul 05 05:50:50 PM PDT 24
Finished Jul 05 05:50:53 PM PDT 24
Peak memory 199604 kb
Host smart-4d64ba63-be50-47f3-8100-1da1a2d93167
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969140216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.2969140216
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.3416963130
Short name T246
Test name
Test status
Simulation time 117641279 ps
CPU time 0.91 seconds
Started Jul 05 05:50:53 PM PDT 24
Finished Jul 05 05:50:56 PM PDT 24
Peak memory 209288 kb
Host smart-ff3a8fd8-12bb-434f-8e78-1c56360c03b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416963130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.3416963130
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.2844825715
Short name T26
Test name
Test status
Simulation time 1022641915 ps
CPU time 1.45 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:50:57 PM PDT 24
Peak memory 218300 kb
Host smart-7bce3ef6-668c-43c6-acf9-6aba7bf8a698
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844825715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.2844825715
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.2953210723
Short name T316
Test name
Test status
Simulation time 114928007 ps
CPU time 0.68 seconds
Started Jul 05 05:50:51 PM PDT 24
Finished Jul 05 05:50:54 PM PDT 24
Peak memory 198928 kb
Host smart-afbdb0c7-da1d-483e-9b07-548f8e7624e1
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953210723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_c
m_ctrl_config_regwen.2953210723
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.555211153
Short name T611
Test name
Test status
Simulation time 782725678 ps
CPU time 3.23 seconds
Started Jul 05 05:50:48 PM PDT 24
Finished Jul 05 05:50:53 PM PDT 24
Peak memory 200940 kb
Host smart-e27abafb-5b62-46ac-a178-129e74ac3f27
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555211153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.555211153
Directory /workspace/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.3249534254
Short name T205
Test name
Test status
Simulation time 147871133 ps
CPU time 0.83 seconds
Started Jul 05 05:50:38 PM PDT 24
Finished Jul 05 05:50:41 PM PDT 24
Peak memory 199268 kb
Host smart-25f7c52e-b163-4a52-a061-3c59896b0bbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249534254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3249534254
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.3095936678
Short name T537
Test name
Test status
Simulation time 28306777 ps
CPU time 0.7 seconds
Started Jul 05 05:50:48 PM PDT 24
Finished Jul 05 05:50:51 PM PDT 24
Peak memory 199144 kb
Host smart-fd9cb204-54d3-47ad-843d-4f0a0838abe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095936678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3095936678
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all.542557694
Short name T307
Test name
Test status
Simulation time 1832544227 ps
CPU time 6.2 seconds
Started Jul 05 05:50:43 PM PDT 24
Finished Jul 05 05:50:49 PM PDT 24
Peak memory 200964 kb
Host smart-773d3f78-dbe5-4438-8561-acd388a389be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542557694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.542557694
Directory /workspace/2.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all_with_rand_reset.337145401
Short name T101
Test name
Test status
Simulation time 6736118855 ps
CPU time 13.83 seconds
Started Jul 05 05:50:53 PM PDT 24
Finished Jul 05 05:51:09 PM PDT 24
Peak memory 201072 kb
Host smart-e65a80d4-a2b1-40f9-a915-87094757bb3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337145401 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all_with_rand_reset.337145401
Directory /workspace/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup.1448422454
Short name T686
Test name
Test status
Simulation time 114549365 ps
CPU time 0.7 seconds
Started Jul 05 05:50:45 PM PDT 24
Finished Jul 05 05:50:46 PM PDT 24
Peak memory 198044 kb
Host smart-2fa458bb-a518-4850-b910-a53d607e309c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448422454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.1448422454
Directory /workspace/2.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup_reset.1744284208
Short name T972
Test name
Test status
Simulation time 93145802 ps
CPU time 0.76 seconds
Started Jul 05 05:50:53 PM PDT 24
Finished Jul 05 05:50:56 PM PDT 24
Peak memory 199112 kb
Host smart-1cc9840f-ff53-409b-bce6-8f5d3cc23300
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744284208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.1744284208
Directory /workspace/2.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.504943850
Short name T339
Test name
Test status
Simulation time 35369785 ps
CPU time 1.05 seconds
Started Jul 05 05:51:32 PM PDT 24
Finished Jul 05 05:51:33 PM PDT 24
Peak memory 200720 kb
Host smart-e0026156-16cb-43a6-81d7-7ee34ee95e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504943850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.504943850
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3339505486
Short name T174
Test name
Test status
Simulation time 30480267 ps
CPU time 0.66 seconds
Started Jul 05 05:51:37 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 197648 kb
Host smart-3eb1c161-1463-46fd-b995-2eab1e1d54a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339505486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.3339505486
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.2815090846
Short name T169
Test name
Test status
Simulation time 308916253 ps
CPU time 1.02 seconds
Started Jul 05 05:51:37 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 197848 kb
Host smart-ee76bf16-ed14-481d-b8e8-358612209659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815090846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2815090846
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.2839370703
Short name T416
Test name
Test status
Simulation time 36064755 ps
CPU time 0.6 seconds
Started Jul 05 05:51:37 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 197696 kb
Host smart-369a534c-054f-4ed3-8110-7049cb8ff598
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839370703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.2839370703
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.173677773
Short name T885
Test name
Test status
Simulation time 45466288 ps
CPU time 0.6 seconds
Started Jul 05 05:51:46 PM PDT 24
Finished Jul 05 05:51:47 PM PDT 24
Peak memory 197848 kb
Host smart-ef8241c8-04bc-4fcc-ac4f-62b5cedec98c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173677773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.173677773
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.393575970
Short name T837
Test name
Test status
Simulation time 211799141 ps
CPU time 0.7 seconds
Started Jul 05 05:51:33 PM PDT 24
Finished Jul 05 05:51:34 PM PDT 24
Peak memory 201128 kb
Host smart-36b032e2-d030-4291-8cbb-fa6a4777e43d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393575970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_invali
d.393575970
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.915229129
Short name T830
Test name
Test status
Simulation time 305786048 ps
CPU time 0.98 seconds
Started Jul 05 05:51:40 PM PDT 24
Finished Jul 05 05:51:42 PM PDT 24
Peak memory 199584 kb
Host smart-cd126fe4-a792-4b3b-a6b1-409ab91c857a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915229129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_wa
keup_race.915229129
Directory /workspace/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.727511728
Short name T493
Test name
Test status
Simulation time 64022766 ps
CPU time 0.87 seconds
Started Jul 05 05:51:32 PM PDT 24
Finished Jul 05 05:51:33 PM PDT 24
Peak memory 199644 kb
Host smart-afc52b30-9045-4e46-b797-16810c7fe21c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727511728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.727511728
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.837674967
Short name T646
Test name
Test status
Simulation time 116606590 ps
CPU time 0.97 seconds
Started Jul 05 05:51:48 PM PDT 24
Finished Jul 05 05:51:49 PM PDT 24
Peak memory 209300 kb
Host smart-1640a570-ac33-44bc-a58a-dd6f5c8e3bb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837674967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.837674967
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.4033291462
Short name T842
Test name
Test status
Simulation time 130808280 ps
CPU time 0.91 seconds
Started Jul 05 05:51:35 PM PDT 24
Finished Jul 05 05:51:37 PM PDT 24
Peak memory 198608 kb
Host smart-c82edaef-83ec-4be2-8d21-1cbdb48fff2e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033291462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_
cm_ctrl_config_regwen.4033291462
Directory /workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.133475065
Short name T447
Test name
Test status
Simulation time 1270866102 ps
CPU time 2.28 seconds
Started Jul 05 05:51:32 PM PDT 24
Finished Jul 05 05:51:35 PM PDT 24
Peak memory 200816 kb
Host smart-89c87782-e1b1-4166-a84d-013e819b46ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133475065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.133475065
Directory /workspace/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2270761246
Short name T499
Test name
Test status
Simulation time 1372410532 ps
CPU time 2.17 seconds
Started Jul 05 05:51:51 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 200916 kb
Host smart-a94c0bd6-5de0-43a3-bb6b-82643beb4383
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270761246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2270761246
Directory /workspace/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.3657022566
Short name T890
Test name
Test status
Simulation time 103470409 ps
CPU time 0.81 seconds
Started Jul 05 05:51:33 PM PDT 24
Finished Jul 05 05:51:35 PM PDT 24
Peak memory 199144 kb
Host smart-531e4eb2-4dc2-4368-9ea7-bdb7fa908e69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657022566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3657022566
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.3077711969
Short name T652
Test name
Test status
Simulation time 35963006 ps
CPU time 0.67 seconds
Started Jul 05 05:51:43 PM PDT 24
Finished Jul 05 05:51:44 PM PDT 24
Peak memory 199096 kb
Host smart-9fb039ef-bc85-4d7a-9fe2-b1ba3b5617fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077711969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.3077711969
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all.1604259778
Short name T556
Test name
Test status
Simulation time 2419762070 ps
CPU time 4.54 seconds
Started Jul 05 05:51:33 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 200984 kb
Host smart-45bd6e0d-9d1d-4330-a71a-acd31b4cd58a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604259778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.1604259778
Directory /workspace/20.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all_with_rand_reset.1240626267
Short name T160
Test name
Test status
Simulation time 4971960387 ps
CPU time 7.09 seconds
Started Jul 05 05:51:28 PM PDT 24
Finished Jul 05 05:51:35 PM PDT 24
Peak memory 201136 kb
Host smart-a9343e83-ab57-4742-8d6d-77a41b01774c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240626267 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all_with_rand_reset.1240626267
Directory /workspace/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup.2553147701
Short name T683
Test name
Test status
Simulation time 254446000 ps
CPU time 0.76 seconds
Started Jul 05 05:51:42 PM PDT 24
Finished Jul 05 05:51:43 PM PDT 24
Peak memory 198140 kb
Host smart-fedbd2e2-a3e6-4905-8512-9d21ccedd395
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553147701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.2553147701
Directory /workspace/20.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup_reset.4012706084
Short name T226
Test name
Test status
Simulation time 188045535 ps
CPU time 1.06 seconds
Started Jul 05 05:51:35 PM PDT 24
Finished Jul 05 05:51:37 PM PDT 24
Peak memory 200708 kb
Host smart-04a49bff-4e1f-4e54-9bf5-973f8b4f4e6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012706084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.4012706084
Directory /workspace/20.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.3282057890
Short name T103
Test name
Test status
Simulation time 69371279 ps
CPU time 0.91 seconds
Started Jul 05 05:51:42 PM PDT 24
Finished Jul 05 05:51:44 PM PDT 24
Peak memory 200000 kb
Host smart-76d62d1b-04b9-4b37-a9d0-8cc24dd430c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282057890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.3282057890
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.971505658
Short name T796
Test name
Test status
Simulation time 56628878 ps
CPU time 0.79 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:51:53 PM PDT 24
Peak memory 198860 kb
Host smart-915c32b7-534a-4ec1-ac58-bccb603b39c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971505658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disa
ble_rom_integrity_check.971505658
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.3568105700
Short name T893
Test name
Test status
Simulation time 31565889 ps
CPU time 0.64 seconds
Started Jul 05 05:51:47 PM PDT 24
Finished Jul 05 05:51:48 PM PDT 24
Peak memory 197788 kb
Host smart-30d9ef02-a7ea-4555-9b5a-d077ab19dee7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568105700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.3568105700
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.654463297
Short name T153
Test name
Test status
Simulation time 165425292 ps
CPU time 0.98 seconds
Started Jul 05 05:52:03 PM PDT 24
Finished Jul 05 05:52:05 PM PDT 24
Peak memory 198112 kb
Host smart-6c49c44f-cbfa-48b5-bf38-f81878014ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654463297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.654463297
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.4187585480
Short name T432
Test name
Test status
Simulation time 26425594 ps
CPU time 0.64 seconds
Started Jul 05 05:51:46 PM PDT 24
Finished Jul 05 05:51:47 PM PDT 24
Peak memory 197860 kb
Host smart-baf4c0ae-7430-4d77-a530-d7347996e94f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187585480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.4187585480
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.4029884322
Short name T584
Test name
Test status
Simulation time 102896017 ps
CPU time 0.63 seconds
Started Jul 05 05:51:44 PM PDT 24
Finished Jul 05 05:51:45 PM PDT 24
Peak memory 197852 kb
Host smart-0f3abeef-cffb-4279-beb2-a4d362ac3e5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029884322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.4029884322
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.2843595432
Short name T928
Test name
Test status
Simulation time 75904924 ps
CPU time 0.7 seconds
Started Jul 05 05:52:01 PM PDT 24
Finished Jul 05 05:52:03 PM PDT 24
Peak memory 201124 kb
Host smart-2278b4c3-3215-4dbd-88e0-4315115e8571
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843595432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.2843595432
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.3642309459
Short name T881
Test name
Test status
Simulation time 50454031 ps
CPU time 0.65 seconds
Started Jul 05 05:51:35 PM PDT 24
Finished Jul 05 05:51:38 PM PDT 24
Peak memory 198284 kb
Host smart-5df49e07-fc25-43cd-8cb0-2721db6d77f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642309459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_w
akeup_race.3642309459
Directory /workspace/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.4046824039
Short name T98
Test name
Test status
Simulation time 106947197 ps
CPU time 0.79 seconds
Started Jul 05 05:51:32 PM PDT 24
Finished Jul 05 05:51:34 PM PDT 24
Peak memory 198888 kb
Host smart-4db840b7-7679-420e-8ff3-a3deda865f7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046824039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.4046824039
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.2350928867
Short name T653
Test name
Test status
Simulation time 97457041 ps
CPU time 0.93 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 209292 kb
Host smart-934b4990-1991-41f5-b4fb-76b22d1db1c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350928867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.2350928867
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.3877065232
Short name T960
Test name
Test status
Simulation time 139562755 ps
CPU time 0.73 seconds
Started Jul 05 05:51:35 PM PDT 24
Finished Jul 05 05:51:38 PM PDT 24
Peak memory 198404 kb
Host smart-299c06df-c031-46ab-840f-895e2c591ac9
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877065232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_
cm_ctrl_config_regwen.3877065232
Directory /workspace/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4026139740
Short name T525
Test name
Test status
Simulation time 1282882266 ps
CPU time 2.22 seconds
Started Jul 05 05:51:34 PM PDT 24
Finished Jul 05 05:51:37 PM PDT 24
Peak memory 200892 kb
Host smart-7b0f78f6-eed5-4633-9e2b-c30f79b35b6b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026139740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4026139740
Directory /workspace/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1754634632
Short name T864
Test name
Test status
Simulation time 904347660 ps
CPU time 3.16 seconds
Started Jul 05 05:51:34 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 200760 kb
Host smart-0e952102-add6-4a28-ba50-5ae16e5ac615
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754634632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1754634632
Directory /workspace/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.1886208292
Short name T604
Test name
Test status
Simulation time 143797003 ps
CPU time 0.92 seconds
Started Jul 05 05:52:04 PM PDT 24
Finished Jul 05 05:52:06 PM PDT 24
Peak memory 199324 kb
Host smart-add2fd4a-8463-46ea-8c60-bdde70090627
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886208292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1886208292
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.3269967604
Short name T82
Test name
Test status
Simulation time 55335602 ps
CPU time 0.63 seconds
Started Jul 05 05:51:32 PM PDT 24
Finished Jul 05 05:51:33 PM PDT 24
Peak memory 198320 kb
Host smart-79c03fa5-33b1-4267-be56-f6db84e4f561
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269967604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.3269967604
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all.2339231305
Short name T844
Test name
Test status
Simulation time 486518539 ps
CPU time 1.34 seconds
Started Jul 05 05:51:40 PM PDT 24
Finished Jul 05 05:51:42 PM PDT 24
Peak memory 200720 kb
Host smart-3235ba74-70c1-49f9-a464-cdd4c87820f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339231305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.2339231305
Directory /workspace/21.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all_with_rand_reset.2388746304
Short name T162
Test name
Test status
Simulation time 10147918722 ps
CPU time 33.97 seconds
Started Jul 05 05:52:07 PM PDT 24
Finished Jul 05 05:52:41 PM PDT 24
Peak memory 201164 kb
Host smart-6b8c9a29-a664-45f7-a6a4-a54086d8903c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388746304 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all_with_rand_reset.2388746304
Directory /workspace/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup.584937803
Short name T195
Test name
Test status
Simulation time 61617040 ps
CPU time 0.86 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 198300 kb
Host smart-ae0d5ec1-0fb0-4123-832c-addfe73cd494
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584937803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.584937803
Directory /workspace/21.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup_reset.3511610461
Short name T988
Test name
Test status
Simulation time 698186596 ps
CPU time 0.91 seconds
Started Jul 05 05:51:39 PM PDT 24
Finished Jul 05 05:51:41 PM PDT 24
Peak memory 199928 kb
Host smart-98569a08-7fa6-4ced-ac31-24e7257fcbbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511610461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.3511610461
Directory /workspace/21.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.3325007910
Short name T477
Test name
Test status
Simulation time 39803244 ps
CPU time 0.74 seconds
Started Jul 05 05:51:49 PM PDT 24
Finished Jul 05 05:51:52 PM PDT 24
Peak memory 198656 kb
Host smart-8ce4e230-978b-4040-8ca8-69497e546ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325007910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.3325007910
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.1565411372
Short name T379
Test name
Test status
Simulation time 81882892 ps
CPU time 0.67 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:56 PM PDT 24
Peak memory 198240 kb
Host smart-d3b45cc2-dd01-4151-8fad-458f745a38a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565411372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.1565411372
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.2756783827
Short name T321
Test name
Test status
Simulation time 28572195 ps
CPU time 0.62 seconds
Started Jul 05 05:51:44 PM PDT 24
Finished Jul 05 05:51:45 PM PDT 24
Peak memory 197000 kb
Host smart-c79c51d7-64fc-4e46-8576-1c387c573f38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756783827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.2756783827
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.932186626
Short name T387
Test name
Test status
Simulation time 635194905 ps
CPU time 0.93 seconds
Started Jul 05 05:52:14 PM PDT 24
Finished Jul 05 05:52:16 PM PDT 24
Peak memory 197852 kb
Host smart-05cf65b4-afdb-41c8-ad84-42fb5210c488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932186626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.932186626
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.3878706240
Short name T902
Test name
Test status
Simulation time 55543887 ps
CPU time 0.61 seconds
Started Jul 05 05:51:55 PM PDT 24
Finished Jul 05 05:51:57 PM PDT 24
Peak memory 197868 kb
Host smart-44c665b0-f3e4-4b91-9776-c71bc0792f14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878706240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.3878706240
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.1581228699
Short name T429
Test name
Test status
Simulation time 23761441 ps
CPU time 0.59 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:51:52 PM PDT 24
Peak memory 198164 kb
Host smart-de1d235d-e9fc-433a-916c-821ea04dbc46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581228699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.1581228699
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.1708642898
Short name T422
Test name
Test status
Simulation time 53346354 ps
CPU time 0.68 seconds
Started Jul 05 05:51:54 PM PDT 24
Finished Jul 05 05:51:57 PM PDT 24
Peak memory 201128 kb
Host smart-a7c3443c-a97b-4322-946b-ec9b0663ccaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708642898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.1708642898
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_wakeup_race.2790434812
Short name T358
Test name
Test status
Simulation time 269700135 ps
CPU time 1.11 seconds
Started Jul 05 05:51:56 PM PDT 24
Finished Jul 05 05:51:59 PM PDT 24
Peak memory 199472 kb
Host smart-fb55e7e2-011d-4f3b-b3ce-db3a0ae7070a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790434812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_w
akeup_race.2790434812
Directory /workspace/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.2708474870
Short name T3
Test name
Test status
Simulation time 34248071 ps
CPU time 0.67 seconds
Started Jul 05 05:51:43 PM PDT 24
Finished Jul 05 05:51:44 PM PDT 24
Peak memory 198076 kb
Host smart-159b428a-0bfe-4d1b-96cd-52da3782416b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708474870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.2708474870
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.3684535784
Short name T405
Test name
Test status
Simulation time 207253948 ps
CPU time 0.78 seconds
Started Jul 05 05:51:54 PM PDT 24
Finished Jul 05 05:51:57 PM PDT 24
Peak memory 209280 kb
Host smart-f192d873-a565-49c9-b8bc-baa1b68ffaf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684535784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.3684535784
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.3804445110
Short name T991
Test name
Test status
Simulation time 187816105 ps
CPU time 1.14 seconds
Started Jul 05 05:52:00 PM PDT 24
Finished Jul 05 05:52:02 PM PDT 24
Peak memory 199828 kb
Host smart-5597750e-5016-4742-b4c1-9c3dea52aab4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804445110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_
cm_ctrl_config_regwen.3804445110
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3144587273
Short name T264
Test name
Test status
Simulation time 1236434358 ps
CPU time 2.33 seconds
Started Jul 05 05:51:35 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 200980 kb
Host smart-c11a71c3-8197-4dfa-a31a-b8cb64f71023
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144587273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3144587273
Directory /workspace/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2702633342
Short name T118
Test name
Test status
Simulation time 849865726 ps
CPU time 2.98 seconds
Started Jul 05 05:51:46 PM PDT 24
Finished Jul 05 05:51:50 PM PDT 24
Peak memory 200988 kb
Host smart-4697e7e0-755a-481d-8674-7ae56251665f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702633342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2702633342
Directory /workspace/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.345973448
Short name T320
Test name
Test status
Simulation time 55364247 ps
CPU time 0.87 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:51:53 PM PDT 24
Peak memory 199068 kb
Host smart-46abffa0-bc4f-49ae-ba55-2227f1738fa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345973448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_
mubi.345973448
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.3872021362
Short name T738
Test name
Test status
Simulation time 198736930 ps
CPU time 0.64 seconds
Started Jul 05 05:51:45 PM PDT 24
Finished Jul 05 05:51:46 PM PDT 24
Peak memory 198176 kb
Host smart-f28d5377-43e9-432a-b765-bec2d5d54bb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872021362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.3872021362
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all.3673913786
Short name T127
Test name
Test status
Simulation time 2378034347 ps
CPU time 8.02 seconds
Started Jul 05 05:51:59 PM PDT 24
Finished Jul 05 05:52:08 PM PDT 24
Peak memory 201056 kb
Host smart-a5e8efbb-c36e-428c-bfc7-ad7e5d52f0d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673913786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.3673913786
Directory /workspace/22.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all_with_rand_reset.3807891313
Short name T482
Test name
Test status
Simulation time 13375511409 ps
CPU time 19.78 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:52:12 PM PDT 24
Peak memory 201176 kb
Host smart-4a030299-6f11-4539-bf6d-ebe2c5d1f7c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807891313 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all_with_rand_reset.3807891313
Directory /workspace/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup.3698383951
Short name T5
Test name
Test status
Simulation time 102419001 ps
CPU time 0.85 seconds
Started Jul 05 05:51:54 PM PDT 24
Finished Jul 05 05:51:57 PM PDT 24
Peak memory 198900 kb
Host smart-cb731378-003c-4bf2-a01d-3fda6e0f298b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698383951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.3698383951
Directory /workspace/22.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup_reset.1710617165
Short name T532
Test name
Test status
Simulation time 129709387 ps
CPU time 0.79 seconds
Started Jul 05 05:51:39 PM PDT 24
Finished Jul 05 05:51:41 PM PDT 24
Peak memory 199128 kb
Host smart-11900dd4-7521-49d5-8380-18447aca8b22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710617165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.1710617165
Directory /workspace/22.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.3154166580
Short name T735
Test name
Test status
Simulation time 79969050 ps
CPU time 0.73 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 198620 kb
Host smart-e0e37160-7b99-4ee7-a26b-47d1861b569f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154166580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.3154166580
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.4091371505
Short name T288
Test name
Test status
Simulation time 140123510 ps
CPU time 0.7 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 198916 kb
Host smart-cc871188-c6c6-436e-b87d-a7c6dcdbb8e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091371505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.4091371505
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.292114544
Short name T34
Test name
Test status
Simulation time 30354830 ps
CPU time 0.65 seconds
Started Jul 05 05:51:55 PM PDT 24
Finished Jul 05 05:51:58 PM PDT 24
Peak memory 197800 kb
Host smart-2e5acdec-9e93-45a2-90cb-461422372490
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292114544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_
malfunc.292114544
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.1022819048
Short name T817
Test name
Test status
Simulation time 299719992 ps
CPU time 0.92 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:51:53 PM PDT 24
Peak memory 197848 kb
Host smart-66109ea9-cc47-4606-baa7-40f118f9547f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022819048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.1022819048
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.1886063178
Short name T915
Test name
Test status
Simulation time 52266320 ps
CPU time 0.67 seconds
Started Jul 05 05:51:42 PM PDT 24
Finished Jul 05 05:51:43 PM PDT 24
Peak memory 197128 kb
Host smart-0da94843-8b4d-4e15-88ac-bc99424948c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886063178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.1886063178
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.2749634067
Short name T504
Test name
Test status
Simulation time 31596468 ps
CPU time 0.62 seconds
Started Jul 05 05:52:09 PM PDT 24
Finished Jul 05 05:52:10 PM PDT 24
Peak memory 197836 kb
Host smart-f9355c22-f802-4f10-9fbb-7d1afca40c52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749634067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.2749634067
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.4142520607
Short name T746
Test name
Test status
Simulation time 289119414 ps
CPU time 0.69 seconds
Started Jul 05 05:51:42 PM PDT 24
Finished Jul 05 05:51:44 PM PDT 24
Peak memory 201132 kb
Host smart-bd2ce634-64fe-4e68-879d-a6174514668a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142520607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.4142520607
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.3300498881
Short name T720
Test name
Test status
Simulation time 302887035 ps
CPU time 1.32 seconds
Started Jul 05 05:51:49 PM PDT 24
Finished Jul 05 05:51:52 PM PDT 24
Peak memory 199376 kb
Host smart-96f434dd-e3d6-48ff-893b-a62302865a00
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300498881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_w
akeup_race.3300498881
Directory /workspace/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.761386877
Short name T297
Test name
Test status
Simulation time 127171809 ps
CPU time 0.93 seconds
Started Jul 05 05:51:43 PM PDT 24
Finished Jul 05 05:51:44 PM PDT 24
Peak memory 199520 kb
Host smart-02abc441-f65e-46f1-b608-4eae24709a61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761386877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.761386877
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.740350909
Short name T428
Test name
Test status
Simulation time 97111341 ps
CPU time 1.08 seconds
Started Jul 05 05:51:56 PM PDT 24
Finished Jul 05 05:51:59 PM PDT 24
Peak memory 209324 kb
Host smart-aa86e8c4-c4a8-4db6-a0ec-ede59e40b7dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740350909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.740350909
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.315621521
Short name T767
Test name
Test status
Simulation time 326176428 ps
CPU time 1 seconds
Started Jul 05 05:51:51 PM PDT 24
Finished Jul 05 05:51:59 PM PDT 24
Peak memory 199956 kb
Host smart-1291dcec-2866-4b44-9f1c-0fb7bde499f3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315621521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_c
m_ctrl_config_regwen.315621521
Directory /workspace/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2810258845
Short name T908
Test name
Test status
Simulation time 992748476 ps
CPU time 2.04 seconds
Started Jul 05 05:51:48 PM PDT 24
Finished Jul 05 05:51:50 PM PDT 24
Peak memory 200760 kb
Host smart-50c32ceb-7e60-4dae-9b72-45bd1eac279a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810258845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2810258845
Directory /workspace/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1086844993
Short name T784
Test name
Test status
Simulation time 1176164390 ps
CPU time 2.13 seconds
Started Jul 05 05:51:49 PM PDT 24
Finished Jul 05 05:51:52 PM PDT 24
Peak memory 200600 kb
Host smart-918ac15d-4509-4be3-a5bd-d6e23a6b4b94
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086844993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1086844993
Directory /workspace/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3851684395
Short name T501
Test name
Test status
Simulation time 98040650 ps
CPU time 0.89 seconds
Started Jul 05 05:51:44 PM PDT 24
Finished Jul 05 05:51:46 PM PDT 24
Peak memory 198948 kb
Host smart-dd236169-4512-4c6b-8410-c4893ae9a4b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851684395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3851684395
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.3723830854
Short name T570
Test name
Test status
Simulation time 31144776 ps
CPU time 0.66 seconds
Started Jul 05 05:51:45 PM PDT 24
Finished Jul 05 05:51:46 PM PDT 24
Peak memory 198304 kb
Host smart-33ba6d02-9684-48c7-afb2-08f2774af094
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723830854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.3723830854
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all.308818228
Short name T626
Test name
Test status
Simulation time 1356494458 ps
CPU time 6.32 seconds
Started Jul 05 05:51:46 PM PDT 24
Finished Jul 05 05:51:53 PM PDT 24
Peak memory 200928 kb
Host smart-9d5f4da8-9349-4672-8d90-01ccddfb8571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308818228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.308818228
Directory /workspace/23.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all_with_rand_reset.2613360018
Short name T378
Test name
Test status
Simulation time 7124964481 ps
CPU time 21.41 seconds
Started Jul 05 05:51:39 PM PDT 24
Finished Jul 05 05:52:01 PM PDT 24
Peak memory 201076 kb
Host smart-f05aa0b5-15d6-4c50-a929-4924b8813bc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613360018 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all_with_rand_reset.2613360018
Directory /workspace/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.700899541
Short name T111
Test name
Test status
Simulation time 237141179 ps
CPU time 0.98 seconds
Started Jul 05 05:51:45 PM PDT 24
Finished Jul 05 05:51:52 PM PDT 24
Peak memory 199404 kb
Host smart-ae60d133-fdd5-4efe-a655-e105c6964876
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700899541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.700899541
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup_reset.3785891180
Short name T244
Test name
Test status
Simulation time 400759667 ps
CPU time 1.27 seconds
Started Jul 05 05:51:45 PM PDT 24
Finished Jul 05 05:51:47 PM PDT 24
Peak memory 200600 kb
Host smart-307cfdca-b1f5-4c9a-98b0-6c7b9dfdba48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785891180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.3785891180
Directory /workspace/23.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.1607708719
Short name T846
Test name
Test status
Simulation time 22904949 ps
CPU time 0.86 seconds
Started Jul 05 05:51:44 PM PDT 24
Finished Jul 05 05:51:46 PM PDT 24
Peak memory 199808 kb
Host smart-7f390fbd-a914-473d-a40a-35642b652386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607708719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.1607708719
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.1021176335
Short name T824
Test name
Test status
Simulation time 99960084 ps
CPU time 0.69 seconds
Started Jul 05 05:51:44 PM PDT 24
Finished Jul 05 05:51:46 PM PDT 24
Peak memory 198944 kb
Host smart-ae90651a-6236-41c1-b7b6-de39a291b9d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021176335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.1021176335
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.2296119185
Short name T487
Test name
Test status
Simulation time 29621097 ps
CPU time 0.67 seconds
Started Jul 05 05:51:51 PM PDT 24
Finished Jul 05 05:51:54 PM PDT 24
Peak memory 197772 kb
Host smart-bb2dd974-2034-48f1-be83-26883bcc9cfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296119185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.2296119185
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.404525584
Short name T33
Test name
Test status
Simulation time 632987425 ps
CPU time 0.98 seconds
Started Jul 05 05:51:44 PM PDT 24
Finished Jul 05 05:51:45 PM PDT 24
Peak memory 197864 kb
Host smart-d8033a27-74f0-4c20-b0de-cdea43132210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404525584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.404525584
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.4159357770
Short name T594
Test name
Test status
Simulation time 125925205 ps
CPU time 0.58 seconds
Started Jul 05 05:51:48 PM PDT 24
Finished Jul 05 05:51:50 PM PDT 24
Peak memory 197852 kb
Host smart-68dcdb94-1eed-4ae9-948b-ed1b02d9650f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159357770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.4159357770
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.457471746
Short name T763
Test name
Test status
Simulation time 41923389 ps
CPU time 0.64 seconds
Started Jul 05 05:51:48 PM PDT 24
Finished Jul 05 05:51:49 PM PDT 24
Peak memory 198164 kb
Host smart-82c9cde5-d90f-410a-a0c4-7448e7dcadfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457471746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.457471746
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.60136960
Short name T871
Test name
Test status
Simulation time 77477188 ps
CPU time 0.68 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:54 PM PDT 24
Peak memory 201168 kb
Host smart-7f0b61fc-2504-4fb0-a8e4-2903d2a552d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60136960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invalid
.60136960
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_wakeup_race.1839949114
Short name T517
Test name
Test status
Simulation time 347797473 ps
CPU time 1.14 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:51:53 PM PDT 24
Peak memory 199660 kb
Host smart-6e483ec8-5f07-4b58-be80-d1834a901e29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839949114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_w
akeup_race.1839949114
Directory /workspace/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.335469415
Short name T695
Test name
Test status
Simulation time 73317351 ps
CPU time 0.82 seconds
Started Jul 05 05:51:51 PM PDT 24
Finished Jul 05 05:51:54 PM PDT 24
Peak memory 198792 kb
Host smart-d51d8840-6c54-4371-a6e5-073daf7efc59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335469415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.335469415
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.3125795248
Short name T410
Test name
Test status
Simulation time 165068038 ps
CPU time 0.79 seconds
Started Jul 05 05:51:46 PM PDT 24
Finished Jul 05 05:51:47 PM PDT 24
Peak memory 209252 kb
Host smart-7effb6eb-c133-4e88-99ed-0a1df262a25b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125795248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.3125795248
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1118484308
Short name T558
Test name
Test status
Simulation time 333846676 ps
CPU time 1.24 seconds
Started Jul 05 05:51:40 PM PDT 24
Finished Jul 05 05:51:42 PM PDT 24
Peak memory 199836 kb
Host smart-a96ee93e-5a48-49a8-9dce-2642c650d530
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118484308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_
cm_ctrl_config_regwen.1118484308
Directory /workspace/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.663397253
Short name T858
Test name
Test status
Simulation time 879782838 ps
CPU time 2.6 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:51:54 PM PDT 24
Peak memory 200944 kb
Host smart-b42b279b-455c-4a6d-902e-d04045ccb41b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663397253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.663397253
Directory /workspace/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1365388813
Short name T737
Test name
Test status
Simulation time 892740505 ps
CPU time 3.25 seconds
Started Jul 05 05:52:04 PM PDT 24
Finished Jul 05 05:52:08 PM PDT 24
Peak memory 200860 kb
Host smart-22d052c3-89ba-4e30-870a-7b7baca2f9ac
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365388813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1365388813
Directory /workspace/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.126187128
Short name T222
Test name
Test status
Simulation time 63406640 ps
CPU time 0.83 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 199172 kb
Host smart-96bd0a4a-3671-422b-a1ce-2ee765e061fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126187128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_
mubi.126187128
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.3508281257
Short name T954
Test name
Test status
Simulation time 31746919 ps
CPU time 0.69 seconds
Started Jul 05 05:51:42 PM PDT 24
Finished Jul 05 05:51:43 PM PDT 24
Peak memory 198252 kb
Host smart-d5f5839d-4b95-42c5-8756-0435d8963461
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508281257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.3508281257
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all.49980592
Short name T979
Test name
Test status
Simulation time 1738730917 ps
CPU time 2.53 seconds
Started Jul 05 05:51:49 PM PDT 24
Finished Jul 05 05:51:52 PM PDT 24
Peak memory 200948 kb
Host smart-b80d92eb-915f-4177-ae4b-dab628c8eab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49980592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.49980592
Directory /workspace/24.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all_with_rand_reset.204248518
Short name T478
Test name
Test status
Simulation time 7498297619 ps
CPU time 23.3 seconds
Started Jul 05 05:51:55 PM PDT 24
Finished Jul 05 05:52:20 PM PDT 24
Peak memory 201104 kb
Host smart-16fc2217-9742-464f-a194-b9d0d16b1985
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204248518 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all_with_rand_reset.204248518
Directory /workspace/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup.1415848900
Short name T327
Test name
Test status
Simulation time 523628659 ps
CPU time 0.96 seconds
Started Jul 05 05:51:43 PM PDT 24
Finished Jul 05 05:51:44 PM PDT 24
Peak memory 199436 kb
Host smart-034ab192-c34e-4c63-9b73-0ab10810c237
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415848900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.1415848900
Directory /workspace/24.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup_reset.2315975063
Short name T276
Test name
Test status
Simulation time 328706271 ps
CPU time 1.07 seconds
Started Jul 05 05:51:48 PM PDT 24
Finished Jul 05 05:51:50 PM PDT 24
Peak memory 200648 kb
Host smart-72034c82-1a8a-4700-b799-66266374f134
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315975063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.2315975063
Directory /workspace/24.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.2593113905
Short name T126
Test name
Test status
Simulation time 26596442 ps
CPU time 0.75 seconds
Started Jul 05 05:52:13 PM PDT 24
Finished Jul 05 05:52:14 PM PDT 24
Peak memory 198572 kb
Host smart-96635ae8-325c-48fe-8639-da1155732a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593113905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.2593113905
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.1841080024
Short name T272
Test name
Test status
Simulation time 71099455 ps
CPU time 0.71 seconds
Started Jul 05 05:52:03 PM PDT 24
Finished Jul 05 05:52:05 PM PDT 24
Peak memory 198928 kb
Host smart-e2a635e4-70c8-4c06-88e2-1682aadc6247
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841080024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.1841080024
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.1483014596
Short name T287
Test name
Test status
Simulation time 47103776 ps
CPU time 0.6 seconds
Started Jul 05 05:52:10 PM PDT 24
Finished Jul 05 05:52:11 PM PDT 24
Peak memory 197772 kb
Host smart-d85ed30e-ce10-4885-88fc-4fca7e0aee15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483014596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.1483014596
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.2242613773
Short name T172
Test name
Test status
Simulation time 166528677 ps
CPU time 0.96 seconds
Started Jul 05 05:51:51 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 197748 kb
Host smart-36f76dff-8ab2-4485-a97a-5b70ac96bdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242613773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2242613773
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.3987693650
Short name T781
Test name
Test status
Simulation time 60607711 ps
CPU time 0.69 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:51:52 PM PDT 24
Peak memory 197840 kb
Host smart-af65f00e-6e0e-4370-bec1-d2dd448def5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987693650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.3987693650
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.288413806
Short name T920
Test name
Test status
Simulation time 33426849 ps
CPU time 0.61 seconds
Started Jul 05 05:51:49 PM PDT 24
Finished Jul 05 05:51:51 PM PDT 24
Peak memory 197780 kb
Host smart-e5a7eb83-c6e4-4ac1-a6eb-c60a9becc5d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288413806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.288413806
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.3579824635
Short name T546
Test name
Test status
Simulation time 77478284 ps
CPU time 0.67 seconds
Started Jul 05 05:51:49 PM PDT 24
Finished Jul 05 05:51:51 PM PDT 24
Peak memory 201136 kb
Host smart-8a4db1f9-65d4-419e-9daf-cd0a825aad39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579824635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.3579824635
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.483735485
Short name T279
Test name
Test status
Simulation time 164966732 ps
CPU time 0.97 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:51:53 PM PDT 24
Peak memory 198304 kb
Host smart-02ef27d4-6767-4822-b392-ab779193374d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483735485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wa
keup_race.483735485
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.2456399982
Short name T41
Test name
Test status
Simulation time 61658508 ps
CPU time 0.68 seconds
Started Jul 05 05:51:41 PM PDT 24
Finished Jul 05 05:51:42 PM PDT 24
Peak memory 198876 kb
Host smart-27b95481-384d-4462-8cb0-5d04a6414864
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456399982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.2456399982
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.4175279258
Short name T47
Test name
Test status
Simulation time 119701547 ps
CPU time 0.81 seconds
Started Jul 05 05:51:51 PM PDT 24
Finished Jul 05 05:51:54 PM PDT 24
Peak memory 209184 kb
Host smart-2eb67e43-1193-4b8c-9b27-ac3b8f30618b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175279258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.4175279258
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.1387484911
Short name T324
Test name
Test status
Simulation time 171471619 ps
CPU time 0.89 seconds
Started Jul 05 05:52:04 PM PDT 24
Finished Jul 05 05:52:06 PM PDT 24
Peak memory 199700 kb
Host smart-e70b237e-de8e-48f9-bad8-0f0368648cca
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387484911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_
cm_ctrl_config_regwen.1387484911
Directory /workspace/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1568880989
Short name T589
Test name
Test status
Simulation time 825492230 ps
CPU time 2.94 seconds
Started Jul 05 05:51:45 PM PDT 24
Finished Jul 05 05:51:49 PM PDT 24
Peak memory 200924 kb
Host smart-0d2372bd-19f2-4e52-b79b-d0dd260d7fff
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568880989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1568880989
Directory /workspace/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.341243603
Short name T845
Test name
Test status
Simulation time 1452671070 ps
CPU time 2.27 seconds
Started Jul 05 05:52:04 PM PDT 24
Finished Jul 05 05:52:07 PM PDT 24
Peak memory 200936 kb
Host smart-3702eb90-402f-4692-975c-85dd226a776a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341243603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.341243603
Directory /workspace/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1887063499
Short name T210
Test name
Test status
Simulation time 88339948 ps
CPU time 0.94 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 198832 kb
Host smart-2524f1d8-07f7-4ad0-9ad8-5cfe6f27c4d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887063499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1887063499
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.1014391236
Short name T865
Test name
Test status
Simulation time 32054007 ps
CPU time 0.74 seconds
Started Jul 05 05:51:58 PM PDT 24
Finished Jul 05 05:52:00 PM PDT 24
Peak memory 198296 kb
Host smart-7080b384-77bc-4486-8ca8-b08b843ba137
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014391236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.1014391236
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all.1090868232
Short name T551
Test name
Test status
Simulation time 1207045208 ps
CPU time 4.41 seconds
Started Jul 05 05:51:59 PM PDT 24
Finished Jul 05 05:52:04 PM PDT 24
Peak memory 200936 kb
Host smart-ca2344b9-a6bc-4e83-aac7-dd92a46d42dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090868232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.1090868232
Directory /workspace/25.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all_with_rand_reset.2045667016
Short name T92
Test name
Test status
Simulation time 5230589678 ps
CPU time 8.31 seconds
Started Jul 05 05:52:08 PM PDT 24
Finished Jul 05 05:52:17 PM PDT 24
Peak memory 201124 kb
Host smart-4d672c8f-d6fd-4517-8204-fd450412fa17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045667016 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all_with_rand_reset.2045667016
Directory /workspace/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup.2096188301
Short name T359
Test name
Test status
Simulation time 111560418 ps
CPU time 0.91 seconds
Started Jul 05 05:52:04 PM PDT 24
Finished Jul 05 05:52:06 PM PDT 24
Peak memory 198892 kb
Host smart-3f2c314e-9833-4a0d-9240-4e6472dce467
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096188301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.2096188301
Directory /workspace/25.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup_reset.1251372007
Short name T914
Test name
Test status
Simulation time 349045198 ps
CPU time 1.26 seconds
Started Jul 05 05:52:15 PM PDT 24
Finished Jul 05 05:52:18 PM PDT 24
Peak memory 200792 kb
Host smart-200784b6-aeae-4d9a-884e-840047b81fd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251372007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.1251372007
Directory /workspace/25.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.3202953
Short name T659
Test name
Test status
Simulation time 20591519 ps
CPU time 0.75 seconds
Started Jul 05 05:52:13 PM PDT 24
Finished Jul 05 05:52:14 PM PDT 24
Peak memory 198876 kb
Host smart-4e53157f-770f-4a03-8cf5-93b83008e14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.3202953
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.397371975
Short name T349
Test name
Test status
Simulation time 79201955 ps
CPU time 0.74 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:51:53 PM PDT 24
Peak memory 198924 kb
Host smart-62d8e034-42e8-4609-83aa-1999131dfe2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397371975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disa
ble_rom_integrity_check.397371975
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.4139974212
Short name T940
Test name
Test status
Simulation time 38472785 ps
CPU time 0.6 seconds
Started Jul 05 05:51:45 PM PDT 24
Finished Jul 05 05:51:46 PM PDT 24
Peak memory 197768 kb
Host smart-2b5041b1-c104-4651-b2fd-2c53709c3967
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139974212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.4139974212
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.602836638
Short name T634
Test name
Test status
Simulation time 165761856 ps
CPU time 0.99 seconds
Started Jul 05 05:51:57 PM PDT 24
Finished Jul 05 05:52:00 PM PDT 24
Peak memory 197836 kb
Host smart-71a28935-a303-4eb3-945b-12a0c8ff3236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602836638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.602836638
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.1884492536
Short name T682
Test name
Test status
Simulation time 35026694 ps
CPU time 0.63 seconds
Started Jul 05 05:51:44 PM PDT 24
Finished Jul 05 05:51:45 PM PDT 24
Peak memory 197924 kb
Host smart-2666e9e7-7a93-4a4e-9c90-70c9d70d00e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884492536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.1884492536
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.3582430963
Short name T648
Test name
Test status
Simulation time 29939722 ps
CPU time 0.62 seconds
Started Jul 05 05:51:57 PM PDT 24
Finished Jul 05 05:51:59 PM PDT 24
Peak memory 197848 kb
Host smart-35530242-358f-4cb2-aacd-697248575019
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582430963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.3582430963
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.406722224
Short name T962
Test name
Test status
Simulation time 40622977 ps
CPU time 0.71 seconds
Started Jul 05 05:51:51 PM PDT 24
Finished Jul 05 05:51:53 PM PDT 24
Peak memory 201180 kb
Host smart-af401b16-38ab-4cba-8889-ed819e608fa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406722224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invali
d.406722224
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_wakeup_race.35931624
Short name T697
Test name
Test status
Simulation time 285052576 ps
CPU time 1.11 seconds
Started Jul 05 05:52:02 PM PDT 24
Finished Jul 05 05:52:04 PM PDT 24
Peak memory 199376 kb
Host smart-0d874a67-b0d2-4a8e-b3df-0780936046fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35931624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup
_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_wak
eup_race.35931624
Directory /workspace/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.743197954
Short name T524
Test name
Test status
Simulation time 32580857 ps
CPU time 0.74 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 198896 kb
Host smart-22fe6661-161c-4019-8f62-65bca1da7016
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743197954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.743197954
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.45296391
Short name T926
Test name
Test status
Simulation time 112316937 ps
CPU time 0.87 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:51:53 PM PDT 24
Peak memory 209296 kb
Host smart-f67107f2-5750-4468-991f-bf9309235095
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45296391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.45296391
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.187710975
Short name T203
Test name
Test status
Simulation time 84474371 ps
CPU time 0.75 seconds
Started Jul 05 05:51:49 PM PDT 24
Finished Jul 05 05:51:52 PM PDT 24
Peak memory 198360 kb
Host smart-a2e27a35-8acb-4e7e-a5ba-827085744c03
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187710975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_c
m_ctrl_config_regwen.187710975
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.806018419
Short name T180
Test name
Test status
Simulation time 755187005 ps
CPU time 2.81 seconds
Started Jul 05 05:51:49 PM PDT 24
Finished Jul 05 05:51:53 PM PDT 24
Peak memory 200888 kb
Host smart-33623cef-db4e-4072-8663-738689f12a0a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806018419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.806018419
Directory /workspace/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3110110393
Short name T829
Test name
Test status
Simulation time 1060564770 ps
CPU time 2.02 seconds
Started Jul 05 05:51:54 PM PDT 24
Finished Jul 05 05:51:58 PM PDT 24
Peak memory 200648 kb
Host smart-53c2fac5-a531-402f-bf03-bee37751723f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110110393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3110110393
Directory /workspace/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.4003845573
Short name T555
Test name
Test status
Simulation time 102633895 ps
CPU time 0.92 seconds
Started Jul 05 05:52:07 PM PDT 24
Finished Jul 05 05:52:08 PM PDT 24
Peak memory 199156 kb
Host smart-c478f7bc-2ffd-400d-86cf-128b8c9874a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003845573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4003845573
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.1933865877
Short name T334
Test name
Test status
Simulation time 53762629 ps
CPU time 0.65 seconds
Started Jul 05 05:52:03 PM PDT 24
Finished Jul 05 05:52:04 PM PDT 24
Peak memory 198308 kb
Host smart-e39c6889-d6df-4353-a90f-44a8d71aeda6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933865877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1933865877
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all.1636378213
Short name T992
Test name
Test status
Simulation time 535919201 ps
CPU time 1.73 seconds
Started Jul 05 05:52:00 PM PDT 24
Finished Jul 05 05:52:03 PM PDT 24
Peak memory 201016 kb
Host smart-f76b308e-38b8-44c1-916a-b6c05c09c08c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636378213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.1636378213
Directory /workspace/26.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all_with_rand_reset.1390939524
Short name T660
Test name
Test status
Simulation time 5640915790 ps
CPU time 17.16 seconds
Started Jul 05 05:51:57 PM PDT 24
Finished Jul 05 05:52:16 PM PDT 24
Peak memory 201128 kb
Host smart-ddf8fe47-c27f-41f2-8877-fa631ce2949d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390939524 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all_with_rand_reset.1390939524
Directory /workspace/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup.2971502610
Short name T822
Test name
Test status
Simulation time 269270733 ps
CPU time 1.02 seconds
Started Jul 05 05:51:49 PM PDT 24
Finished Jul 05 05:51:51 PM PDT 24
Peak memory 199588 kb
Host smart-7018c497-63f8-42f7-9fed-d7a1e3174b80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971502610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.2971502610
Directory /workspace/26.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup_reset.2984569118
Short name T776
Test name
Test status
Simulation time 337505168 ps
CPU time 1.19 seconds
Started Jul 05 05:51:56 PM PDT 24
Finished Jul 05 05:51:59 PM PDT 24
Peak memory 200192 kb
Host smart-1208be03-0a02-4c76-a4e9-288f9c9fd26a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984569118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.2984569118
Directory /workspace/26.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.156150740
Short name T990
Test name
Test status
Simulation time 98119399 ps
CPU time 0.73 seconds
Started Jul 05 05:52:10 PM PDT 24
Finished Jul 05 05:52:11 PM PDT 24
Peak memory 198484 kb
Host smart-7e202faf-3535-4a8f-a5d0-825a09a51314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156150740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.156150740
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.1356504054
Short name T734
Test name
Test status
Simulation time 58779819 ps
CPU time 0.79 seconds
Started Jul 05 05:52:12 PM PDT 24
Finished Jul 05 05:52:14 PM PDT 24
Peak memory 198916 kb
Host smart-b1f8e8ba-ee03-4659-b602-636340c2260e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356504054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.1356504054
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1785555728
Short name T863
Test name
Test status
Simulation time 29697952 ps
CPU time 0.67 seconds
Started Jul 05 05:51:51 PM PDT 24
Finished Jul 05 05:51:54 PM PDT 24
Peak memory 197792 kb
Host smart-b79ef695-0950-4187-b2d1-2a81075dc04d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785555728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.1785555728
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.3269750359
Short name T640
Test name
Test status
Simulation time 160722647 ps
CPU time 1.01 seconds
Started Jul 05 05:52:10 PM PDT 24
Finished Jul 05 05:52:12 PM PDT 24
Peak memory 197848 kb
Host smart-f2198f8f-2c76-4496-9ae3-45cefa228ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269750359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.3269750359
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.3260875276
Short name T592
Test name
Test status
Simulation time 52032016 ps
CPU time 0.67 seconds
Started Jul 05 05:52:11 PM PDT 24
Finished Jul 05 05:52:13 PM PDT 24
Peak memory 197840 kb
Host smart-95e396cc-9883-40bc-9d79-85ca625ea99f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260875276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.3260875276
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.4042817351
Short name T109
Test name
Test status
Simulation time 63707269 ps
CPU time 0.62 seconds
Started Jul 05 05:52:15 PM PDT 24
Finished Jul 05 05:52:16 PM PDT 24
Peak memory 197840 kb
Host smart-c8131411-fce2-4eb0-9aef-c88c6e235d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042817351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.4042817351
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.1411287519
Short name T438
Test name
Test status
Simulation time 46783244 ps
CPU time 0.74 seconds
Started Jul 05 05:52:08 PM PDT 24
Finished Jul 05 05:52:09 PM PDT 24
Peak memory 201124 kb
Host smart-4cace916-0f07-41a5-8e38-87dfb89bbce1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411287519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.1411287519
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_wakeup_race.2730184000
Short name T713
Test name
Test status
Simulation time 266342525 ps
CPU time 1.29 seconds
Started Jul 05 05:51:48 PM PDT 24
Finished Jul 05 05:51:50 PM PDT 24
Peak memory 199500 kb
Host smart-51120210-8827-40e9-8e66-833c1d17bf3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730184000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_w
akeup_race.2730184000
Directory /workspace/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.1562736636
Short name T751
Test name
Test status
Simulation time 168945337 ps
CPU time 0.95 seconds
Started Jul 05 05:52:01 PM PDT 24
Finished Jul 05 05:52:03 PM PDT 24
Peak memory 199736 kb
Host smart-ba790292-23da-4d2f-8980-4f0ac4a1cfce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562736636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.1562736636
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.1687079603
Short name T209
Test name
Test status
Simulation time 104371445 ps
CPU time 1.02 seconds
Started Jul 05 05:51:51 PM PDT 24
Finished Jul 05 05:51:54 PM PDT 24
Peak memory 209252 kb
Host smart-f07152a6-0ce9-4d41-aaad-7ef14473259d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687079603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.1687079603
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.2623832718
Short name T554
Test name
Test status
Simulation time 257676402 ps
CPU time 1.25 seconds
Started Jul 05 05:52:04 PM PDT 24
Finished Jul 05 05:52:06 PM PDT 24
Peak memory 199876 kb
Host smart-91882b86-eb22-4d2c-bcfe-1bf9cc32c354
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623832718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_
cm_ctrl_config_regwen.2623832718
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.480529393
Short name T449
Test name
Test status
Simulation time 1095949659 ps
CPU time 2.23 seconds
Started Jul 05 05:51:48 PM PDT 24
Finished Jul 05 05:51:50 PM PDT 24
Peak memory 200852 kb
Host smart-ced8ca29-bf5d-4cdf-abb2-91022707b86a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480529393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.480529393
Directory /workspace/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3758830076
Short name T917
Test name
Test status
Simulation time 1049694928 ps
CPU time 2.53 seconds
Started Jul 05 05:52:10 PM PDT 24
Finished Jul 05 05:52:13 PM PDT 24
Peak memory 200844 kb
Host smart-5e72585f-0ac1-4ec9-ae9d-cca945530408
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758830076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3758830076
Directory /workspace/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.178487451
Short name T543
Test name
Test status
Simulation time 51914725 ps
CPU time 0.92 seconds
Started Jul 05 05:52:10 PM PDT 24
Finished Jul 05 05:52:12 PM PDT 24
Peak memory 198968 kb
Host smart-98128426-d47a-4fe8-8310-b0f47deda05d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178487451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_
mubi.178487451
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.234871789
Short name T366
Test name
Test status
Simulation time 42064840 ps
CPU time 0.64 seconds
Started Jul 05 05:51:48 PM PDT 24
Finished Jul 05 05:51:49 PM PDT 24
Peak memory 199132 kb
Host smart-592466df-8817-4530-adf8-2b0fdf004f33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234871789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.234871789
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all.1040797110
Short name T115
Test name
Test status
Simulation time 891802585 ps
CPU time 3.25 seconds
Started Jul 05 05:51:49 PM PDT 24
Finished Jul 05 05:51:54 PM PDT 24
Peak memory 200928 kb
Host smart-66eebb54-834e-459d-a9e0-b0e183c7bac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040797110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.1040797110
Directory /workspace/27.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all_with_rand_reset.3238252284
Short name T859
Test name
Test status
Simulation time 16273242068 ps
CPU time 19.87 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:52:12 PM PDT 24
Peak memory 201100 kb
Host smart-4c35bc0a-8457-449d-b5fb-505c16403791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238252284 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all_with_rand_reset.3238252284
Directory /workspace/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup.4221533978
Short name T748
Test name
Test status
Simulation time 160170959 ps
CPU time 1.08 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:56 PM PDT 24
Peak memory 199432 kb
Host smart-62c34234-36e4-4db1-a311-dd620fbebdd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221533978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.4221533978
Directory /workspace/27.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup_reset.1219946802
Short name T862
Test name
Test status
Simulation time 362471558 ps
CPU time 1.05 seconds
Started Jul 05 05:51:55 PM PDT 24
Finished Jul 05 05:51:58 PM PDT 24
Peak memory 199988 kb
Host smart-232e262c-e492-4cf6-9c47-335e870b54ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219946802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.1219946802
Directory /workspace/27.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.2503644166
Short name T772
Test name
Test status
Simulation time 38693991 ps
CPU time 0.83 seconds
Started Jul 05 05:51:49 PM PDT 24
Finished Jul 05 05:51:51 PM PDT 24
Peak memory 199780 kb
Host smart-48682b13-d8ec-41b0-9dc6-5e1df1c339dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503644166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.2503644166
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.2921620448
Short name T194
Test name
Test status
Simulation time 239195751 ps
CPU time 0.7 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:20 PM PDT 24
Peak memory 198920 kb
Host smart-d3fa1c57-488a-409a-9270-297681e979a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921620448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.2921620448
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.981810733
Short name T285
Test name
Test status
Simulation time 31180825 ps
CPU time 0.68 seconds
Started Jul 05 05:52:10 PM PDT 24
Finished Jul 05 05:52:11 PM PDT 24
Peak memory 197740 kb
Host smart-e96d68ad-601c-4473-9eff-46e6831a8b6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981810733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_
malfunc.981810733
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.988276076
Short name T573
Test name
Test status
Simulation time 313202629 ps
CPU time 1 seconds
Started Jul 05 05:52:11 PM PDT 24
Finished Jul 05 05:52:12 PM PDT 24
Peak memory 197844 kb
Host smart-ff91000a-de25-439b-8fc8-b6523ac8bd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988276076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.988276076
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.4011326987
Short name T900
Test name
Test status
Simulation time 34276767 ps
CPU time 0.64 seconds
Started Jul 05 05:51:56 PM PDT 24
Finished Jul 05 05:51:58 PM PDT 24
Peak memory 197872 kb
Host smart-0602eec9-35fe-42ba-b876-d00430892a85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011326987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.4011326987
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.1692391968
Short name T332
Test name
Test status
Simulation time 48593732 ps
CPU time 0.6 seconds
Started Jul 05 05:51:55 PM PDT 24
Finished Jul 05 05:51:57 PM PDT 24
Peak memory 197824 kb
Host smart-c9d767dc-442d-458a-820d-6fad64ef1b84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692391968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.1692391968
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.4056552636
Short name T453
Test name
Test status
Simulation time 85279609 ps
CPU time 0.71 seconds
Started Jul 05 05:52:07 PM PDT 24
Finished Jul 05 05:52:09 PM PDT 24
Peak memory 201096 kb
Host smart-eb91f59f-3ffe-4807-9b77-31d21ab9ccef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056552636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.4056552636
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.2809887386
Short name T616
Test name
Test status
Simulation time 129977418 ps
CPU time 0.69 seconds
Started Jul 05 05:51:48 PM PDT 24
Finished Jul 05 05:51:50 PM PDT 24
Peak memory 198056 kb
Host smart-c75c4563-15be-4fe0-8520-ce51accd31d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809887386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_w
akeup_race.2809887386
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.2512282238
Short name T755
Test name
Test status
Simulation time 46509895 ps
CPU time 0.78 seconds
Started Jul 05 05:51:55 PM PDT 24
Finished Jul 05 05:51:58 PM PDT 24
Peak memory 198880 kb
Host smart-b12c2293-717b-40d6-ac97-95cddf3775cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512282238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.2512282238
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.450040687
Short name T622
Test name
Test status
Simulation time 151076373 ps
CPU time 0.78 seconds
Started Jul 05 05:51:57 PM PDT 24
Finished Jul 05 05:51:59 PM PDT 24
Peak memory 201084 kb
Host smart-c312c4a9-fe69-4e37-96ff-ac6b42110266
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450040687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.450040687
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.2965226267
Short name T675
Test name
Test status
Simulation time 221717913 ps
CPU time 1.19 seconds
Started Jul 05 05:51:58 PM PDT 24
Finished Jul 05 05:52:01 PM PDT 24
Peak memory 199872 kb
Host smart-97246f7b-f190-4dd5-83ae-a9adb5c35309
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965226267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_
cm_ctrl_config_regwen.2965226267
Directory /workspace/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1847290950
Short name T964
Test name
Test status
Simulation time 926536239 ps
CPU time 2.38 seconds
Started Jul 05 05:52:12 PM PDT 24
Finished Jul 05 05:52:16 PM PDT 24
Peak memory 200908 kb
Host smart-fba7038d-d8f1-466c-9b70-f43d61886ce4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847290950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1847290950
Directory /workspace/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2750691250
Short name T536
Test name
Test status
Simulation time 1240740913 ps
CPU time 2.21 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:21 PM PDT 24
Peak memory 200884 kb
Host smart-dac71522-5a87-4b79-8e3f-03343955325a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750691250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2750691250
Directory /workspace/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2159514602
Short name T630
Test name
Test status
Simulation time 96541640 ps
CPU time 0.8 seconds
Started Jul 05 05:51:55 PM PDT 24
Finished Jul 05 05:51:58 PM PDT 24
Peak memory 199144 kb
Host smart-9bd1953c-a65a-4e87-b077-26a3caf9b6ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159514602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2159514602
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.207133590
Short name T382
Test name
Test status
Simulation time 52647065 ps
CPU time 0.63 seconds
Started Jul 05 05:52:11 PM PDT 24
Finished Jul 05 05:52:13 PM PDT 24
Peak memory 198284 kb
Host smart-4eb35ff0-ad2c-40e1-b57e-eb3a026a43f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207133590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.207133590
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all_with_rand_reset.2352226762
Short name T164
Test name
Test status
Simulation time 17236171799 ps
CPU time 36.86 seconds
Started Jul 05 05:51:57 PM PDT 24
Finished Jul 05 05:52:35 PM PDT 24
Peak memory 201132 kb
Host smart-0a417bb7-0995-420a-ac83-d1ec45d11cc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352226762 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all_with_rand_reset.2352226762
Directory /workspace/28.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup.1185449419
Short name T861
Test name
Test status
Simulation time 269202511 ps
CPU time 1.02 seconds
Started Jul 05 05:51:59 PM PDT 24
Finished Jul 05 05:52:01 PM PDT 24
Peak memory 199316 kb
Host smart-5e47e483-7569-4dc7-9c53-c882bc985159
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185449419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.1185449419
Directory /workspace/28.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup_reset.2804849864
Short name T886
Test name
Test status
Simulation time 379352619 ps
CPU time 1.03 seconds
Started Jul 05 05:52:08 PM PDT 24
Finished Jul 05 05:52:10 PM PDT 24
Peak memory 199784 kb
Host smart-9efe3006-063c-4383-8474-ff6426cf53e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804849864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.2804849864
Directory /workspace/28.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.1394194567
Short name T254
Test name
Test status
Simulation time 120817158 ps
CPU time 0.87 seconds
Started Jul 05 05:52:10 PM PDT 24
Finished Jul 05 05:52:11 PM PDT 24
Peak memory 199872 kb
Host smart-a55d8100-234e-442c-8d74-e58b4e905921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394194567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.1394194567
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.1697302648
Short name T539
Test name
Test status
Simulation time 72476787 ps
CPU time 0.74 seconds
Started Jul 05 05:52:14 PM PDT 24
Finished Jul 05 05:52:15 PM PDT 24
Peak memory 198848 kb
Host smart-dd64d8f4-b5bc-41a5-ae1b-0347d67a7419
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697302648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.1697302648
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2796134766
Short name T688
Test name
Test status
Simulation time 29001579 ps
CPU time 0.64 seconds
Started Jul 05 05:51:54 PM PDT 24
Finished Jul 05 05:51:57 PM PDT 24
Peak memory 197764 kb
Host smart-9f3fada0-389b-413a-9e42-7d7173a2c23f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796134766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.2796134766
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.613803219
Short name T766
Test name
Test status
Simulation time 317299595 ps
CPU time 0.92 seconds
Started Jul 05 05:51:51 PM PDT 24
Finished Jul 05 05:51:58 PM PDT 24
Peak memory 197852 kb
Host smart-3db94778-2bd4-4f11-853b-039d75f6b018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613803219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.613803219
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.2491690406
Short name T870
Test name
Test status
Simulation time 46462816 ps
CPU time 0.61 seconds
Started Jul 05 05:51:55 PM PDT 24
Finished Jul 05 05:51:57 PM PDT 24
Peak memory 197108 kb
Host smart-a81569bc-e8b8-42b1-bce2-7c2e06b9664a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491690406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.2491690406
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.238684707
Short name T745
Test name
Test status
Simulation time 30504784 ps
CPU time 0.63 seconds
Started Jul 05 05:51:56 PM PDT 24
Finished Jul 05 05:51:58 PM PDT 24
Peak memory 197860 kb
Host smart-a3cdf989-8d7e-4754-8eb3-9b2014755a4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238684707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.238684707
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.2732252636
Short name T580
Test name
Test status
Simulation time 284201099 ps
CPU time 1.06 seconds
Started Jul 05 05:52:17 PM PDT 24
Finished Jul 05 05:52:19 PM PDT 24
Peak memory 199396 kb
Host smart-47f5a4a2-e9ba-4b9c-8db7-8e38b1d37823
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732252636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_w
akeup_race.2732252636
Directory /workspace/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.2285827941
Short name T606
Test name
Test status
Simulation time 104106263 ps
CPU time 0.84 seconds
Started Jul 05 05:51:53 PM PDT 24
Finished Jul 05 05:51:56 PM PDT 24
Peak memory 199372 kb
Host smart-217da6a5-d084-44b3-bb85-116acbcd5669
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285827941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.2285827941
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.3020775417
Short name T505
Test name
Test status
Simulation time 116577234 ps
CPU time 0.81 seconds
Started Jul 05 05:52:07 PM PDT 24
Finished Jul 05 05:52:09 PM PDT 24
Peak memory 209324 kb
Host smart-edb909a7-bfb1-48d0-bbb9-a137d5512d6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020775417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.3020775417
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.386532475
Short name T368
Test name
Test status
Simulation time 228982300 ps
CPU time 1.24 seconds
Started Jul 05 05:52:11 PM PDT 24
Finished Jul 05 05:52:13 PM PDT 24
Peak memory 199816 kb
Host smart-053c1356-0485-4ec1-b53b-79cfb21c3350
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386532475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_c
m_ctrl_config_regwen.386532475
Directory /workspace/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2505385721
Short name T342
Test name
Test status
Simulation time 1058917668 ps
CPU time 2.13 seconds
Started Jul 05 05:52:13 PM PDT 24
Finished Jul 05 05:52:16 PM PDT 24
Peak memory 200920 kb
Host smart-f2cb3280-95c7-4542-9903-19f36d21ad9c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505385721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2505385721
Directory /workspace/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.499822913
Short name T395
Test name
Test status
Simulation time 784505999 ps
CPU time 2.86 seconds
Started Jul 05 05:51:58 PM PDT 24
Finished Jul 05 05:52:12 PM PDT 24
Peak memory 200908 kb
Host smart-6d9fe77f-f0b4-4fff-8576-9c0acf9af8b0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499822913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.499822913
Directory /workspace/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.3189248134
Short name T785
Test name
Test status
Simulation time 123996287 ps
CPU time 0.81 seconds
Started Jul 05 05:52:15 PM PDT 24
Finished Jul 05 05:52:17 PM PDT 24
Peak memory 198956 kb
Host smart-23048104-e144-468f-b8a3-cc4aaae164ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189248134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3189248134
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.1357184556
Short name T593
Test name
Test status
Simulation time 225059802 ps
CPU time 0.64 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:20 PM PDT 24
Peak memory 198352 kb
Host smart-8bdd4397-f602-486c-8719-2933dfa33580
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357184556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1357184556
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all.779065732
Short name T602
Test name
Test status
Simulation time 924611904 ps
CPU time 3.98 seconds
Started Jul 05 05:51:58 PM PDT 24
Finished Jul 05 05:52:04 PM PDT 24
Peak memory 200956 kb
Host smart-d77d82f7-fe9e-42ba-8d04-47fe8a15d0e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779065732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.779065732
Directory /workspace/29.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all_with_rand_reset.1657323136
Short name T21
Test name
Test status
Simulation time 10268916855 ps
CPU time 31.18 seconds
Started Jul 05 05:52:16 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 201128 kb
Host smart-51890a91-4130-4512-acc6-3bc06822afa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657323136 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all_with_rand_reset.1657323136
Directory /workspace/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup.2533321478
Short name T760
Test name
Test status
Simulation time 288954857 ps
CPU time 1.05 seconds
Started Jul 05 05:51:51 PM PDT 24
Finished Jul 05 05:51:54 PM PDT 24
Peak memory 199360 kb
Host smart-1afeb573-3356-470a-9106-db460f3a2f60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533321478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.2533321478
Directory /workspace/29.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup_reset.2861829093
Short name T656
Test name
Test status
Simulation time 303373057 ps
CPU time 1.47 seconds
Started Jul 05 05:52:05 PM PDT 24
Finished Jul 05 05:52:07 PM PDT 24
Peak memory 200704 kb
Host smart-83cc0a6c-96d5-42e6-ad2c-f373b9e7c70e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861829093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.2861829093
Directory /workspace/29.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.4238177692
Short name T227
Test name
Test status
Simulation time 25941346 ps
CPU time 0.92 seconds
Started Jul 05 05:50:47 PM PDT 24
Finished Jul 05 05:50:49 PM PDT 24
Peak memory 200068 kb
Host smart-298ba23f-b683-4e23-bce3-cb8e85b73235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238177692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.4238177692
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.3626338136
Short name T314
Test name
Test status
Simulation time 141398862 ps
CPU time 0.69 seconds
Started Jul 05 05:50:46 PM PDT 24
Finished Jul 05 05:50:47 PM PDT 24
Peak memory 198816 kb
Host smart-f55ae962-0ecf-4ed1-861f-3888cae03f09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626338136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.3626338136
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3649906776
Short name T470
Test name
Test status
Simulation time 30173381 ps
CPU time 0.62 seconds
Started Jul 05 05:50:51 PM PDT 24
Finished Jul 05 05:50:54 PM PDT 24
Peak memory 197060 kb
Host smart-3f16245b-3c10-4d8e-b931-cd02b776fce7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649906776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.3649906776
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.2200607641
Short name T860
Test name
Test status
Simulation time 161076389 ps
CPU time 1 seconds
Started Jul 05 05:50:48 PM PDT 24
Finished Jul 05 05:50:50 PM PDT 24
Peak memory 198160 kb
Host smart-c20991b3-dc5c-4f70-97a7-79ef5161a690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200607641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.2200607641
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.3633745607
Short name T591
Test name
Test status
Simulation time 76185388 ps
CPU time 0.62 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:50:57 PM PDT 24
Peak memory 197108 kb
Host smart-092ed947-70c2-4e27-b4df-26cec77c8f49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633745607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.3633745607
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.2380847582
Short name T621
Test name
Test status
Simulation time 34367638 ps
CPU time 0.65 seconds
Started Jul 05 05:50:45 PM PDT 24
Finished Jul 05 05:50:46 PM PDT 24
Peak memory 197880 kb
Host smart-4c5a3214-4eb8-4a80-986b-05e34d659fc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380847582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.2380847582
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1802534169
Short name T649
Test name
Test status
Simulation time 42668494 ps
CPU time 0.72 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:03 PM PDT 24
Peak memory 201176 kb
Host smart-db6736c4-fab3-4a92-a0c7-8481b53c015c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802534169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1802534169
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.1933077958
Short name T294
Test name
Test status
Simulation time 182313218 ps
CPU time 0.77 seconds
Started Jul 05 05:50:47 PM PDT 24
Finished Jul 05 05:50:49 PM PDT 24
Peak memory 198204 kb
Host smart-222037ee-a110-48d1-a04b-c2c481e7b70a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933077958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wa
keup_race.1933077958
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.2113062115
Short name T436
Test name
Test status
Simulation time 101724417 ps
CPU time 0.74 seconds
Started Jul 05 05:50:51 PM PDT 24
Finished Jul 05 05:50:54 PM PDT 24
Peak memory 198892 kb
Host smart-36cd4f33-098b-416f-a536-9e612860375a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113062115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.2113062115
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.1481346272
Short name T201
Test name
Test status
Simulation time 148648447 ps
CPU time 0.83 seconds
Started Jul 05 05:50:56 PM PDT 24
Finished Jul 05 05:50:58 PM PDT 24
Peak memory 209276 kb
Host smart-208718cd-3b15-4663-a772-4d360303af6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481346272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.1481346272
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.1635129565
Short name T18
Test name
Test status
Simulation time 333022973 ps
CPU time 1.42 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:03 PM PDT 24
Peak memory 217088 kb
Host smart-074bff1e-e7e4-48b1-978e-b905c70f1f02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635129565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.1635129565
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.3991468510
Short name T228
Test name
Test status
Simulation time 87342092 ps
CPU time 0.6 seconds
Started Jul 05 05:50:47 PM PDT 24
Finished Jul 05 05:50:48 PM PDT 24
Peak memory 199220 kb
Host smart-f02d6f45-9612-4a1a-8fce-93e5465c480e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991468510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_c
m_ctrl_config_regwen.3991468510
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2325597055
Short name T956
Test name
Test status
Simulation time 852976570 ps
CPU time 3.02 seconds
Started Jul 05 05:50:45 PM PDT 24
Finished Jul 05 05:50:48 PM PDT 24
Peak memory 200956 kb
Host smart-bb693c39-8173-4a73-a9cf-32c65c4233b6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325597055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2325597055
Directory /workspace/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1796846973
Short name T821
Test name
Test status
Simulation time 1298537027 ps
CPU time 2.32 seconds
Started Jul 05 05:50:49 PM PDT 24
Finished Jul 05 05:50:54 PM PDT 24
Peak memory 200944 kb
Host smart-3d7ffc78-8b1b-48e0-acaf-041764fffb97
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796846973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1796846973
Directory /workspace/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2955900673
Short name T609
Test name
Test status
Simulation time 150832314 ps
CPU time 0.89 seconds
Started Jul 05 05:50:48 PM PDT 24
Finished Jul 05 05:50:51 PM PDT 24
Peak memory 198976 kb
Host smart-3b826414-5c4d-4de0-aca2-61d4393d7ceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955900673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2955900673
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.1056874198
Short name T670
Test name
Test status
Simulation time 39617059 ps
CPU time 0.65 seconds
Started Jul 05 05:50:49 PM PDT 24
Finished Jul 05 05:50:52 PM PDT 24
Peak memory 198276 kb
Host smart-4b6016d3-a9c1-4e86-91df-a14c1ab17147
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056874198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.1056874198
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all.3354009467
Short name T122
Test name
Test status
Simulation time 3191519049 ps
CPU time 4.02 seconds
Started Jul 05 05:50:57 PM PDT 24
Finished Jul 05 05:51:03 PM PDT 24
Peak memory 200872 kb
Host smart-d6a2b5b3-e701-4c78-b6bc-a7a869442511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354009467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.3354009467
Directory /workspace/3.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3322644394
Short name T749
Test name
Test status
Simulation time 2630461475 ps
CPU time 9.56 seconds
Started Jul 05 05:50:50 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 201128 kb
Host smart-7acae84f-23f6-470d-844f-9deccfe68b8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322644394 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all_with_rand_reset.3322644394
Directory /workspace/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup.4093039496
Short name T406
Test name
Test status
Simulation time 315783962 ps
CPU time 0.84 seconds
Started Jul 05 05:50:43 PM PDT 24
Finished Jul 05 05:50:44 PM PDT 24
Peak memory 199292 kb
Host smart-bf0c59eb-6dbf-41ec-834b-2159401f721b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093039496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.4093039496
Directory /workspace/3.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup_reset.322166675
Short name T420
Test name
Test status
Simulation time 241701662 ps
CPU time 1.18 seconds
Started Jul 05 05:50:58 PM PDT 24
Finished Jul 05 05:51:01 PM PDT 24
Peak memory 200752 kb
Host smart-eca08fd7-550d-479b-bc81-494bfc5545c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322166675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.322166675
Directory /workspace/3.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.436308226
Short name T243
Test name
Test status
Simulation time 110564923 ps
CPU time 0.74 seconds
Started Jul 05 05:52:22 PM PDT 24
Finished Jul 05 05:52:24 PM PDT 24
Peak memory 198492 kb
Host smart-6ea1f94b-7029-43bc-af94-533d78ac3e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436308226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.436308226
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.571867220
Short name T190
Test name
Test status
Simulation time 83542777 ps
CPU time 0.73 seconds
Started Jul 05 05:51:59 PM PDT 24
Finished Jul 05 05:52:01 PM PDT 24
Peak memory 198840 kb
Host smart-2ed1acf1-3bf9-45d0-b902-e281bfdea955
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571867220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disa
ble_rom_integrity_check.571867220
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.1963375974
Short name T12
Test name
Test status
Simulation time 30856858 ps
CPU time 0.62 seconds
Started Jul 05 05:52:14 PM PDT 24
Finished Jul 05 05:52:16 PM PDT 24
Peak memory 197076 kb
Host smart-73db82ea-a1d9-4c52-ab6b-7079d665dcd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963375974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.1963375974
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.2744234052
Short name T446
Test name
Test status
Simulation time 636621653 ps
CPU time 0.95 seconds
Started Jul 05 05:52:08 PM PDT 24
Finished Jul 05 05:52:09 PM PDT 24
Peak memory 198108 kb
Host smart-957f3ac4-0019-4e24-b66d-50dd448c02d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744234052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.2744234052
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.346799081
Short name T206
Test name
Test status
Simulation time 39795368 ps
CPU time 0.66 seconds
Started Jul 05 05:52:00 PM PDT 24
Finished Jul 05 05:52:02 PM PDT 24
Peak memory 197800 kb
Host smart-80d6602b-6209-4fec-94b7-d571ac480af9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346799081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.346799081
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.1967916388
Short name T911
Test name
Test status
Simulation time 36596327 ps
CPU time 0.65 seconds
Started Jul 05 05:52:19 PM PDT 24
Finished Jul 05 05:52:21 PM PDT 24
Peak memory 197860 kb
Host smart-f4042808-d82a-4005-aeae-cacb6ade55c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967916388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.1967916388
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.1574792004
Short name T309
Test name
Test status
Simulation time 37004083 ps
CPU time 0.73 seconds
Started Jul 05 05:51:59 PM PDT 24
Finished Jul 05 05:52:01 PM PDT 24
Peak memory 201172 kb
Host smart-e4e90307-019b-4a19-b381-958252c980c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574792004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.1574792004
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.3821982481
Short name T831
Test name
Test status
Simulation time 330303010 ps
CPU time 1.21 seconds
Started Jul 05 05:51:58 PM PDT 24
Finished Jul 05 05:52:01 PM PDT 24
Peak memory 199388 kb
Host smart-d772fa35-c9ab-48cb-80bb-a99591db5992
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821982481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_w
akeup_race.3821982481
Directory /workspace/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.1599529447
Short name T628
Test name
Test status
Simulation time 122741438 ps
CPU time 0.81 seconds
Started Jul 05 05:51:50 PM PDT 24
Finished Jul 05 05:51:53 PM PDT 24
Peak memory 199520 kb
Host smart-1632650f-c7b6-4351-851f-0fdd7fd07920
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599529447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.1599529447
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.2289154100
Short name T463
Test name
Test status
Simulation time 153908670 ps
CPU time 0.86 seconds
Started Jul 05 05:52:15 PM PDT 24
Finished Jul 05 05:52:16 PM PDT 24
Peak memory 209264 kb
Host smart-7fccdce2-4239-42fa-ad5f-2a2707d9bb12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289154100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.2289154100
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.2824076264
Short name T643
Test name
Test status
Simulation time 315706042 ps
CPU time 1.4 seconds
Started Jul 05 05:52:02 PM PDT 24
Finished Jul 05 05:52:04 PM PDT 24
Peak memory 200048 kb
Host smart-d6cbc8ab-c763-45fa-bfc6-ae0d305bb822
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824076264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_
cm_ctrl_config_regwen.2824076264
Directory /workspace/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4264345591
Short name T485
Test name
Test status
Simulation time 887260824 ps
CPU time 3.02 seconds
Started Jul 05 05:52:12 PM PDT 24
Finished Jul 05 05:52:16 PM PDT 24
Peak memory 200840 kb
Host smart-bafcdb27-cb15-4b7a-9428-dd4aee5aa277
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264345591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4264345591
Directory /workspace/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.549179251
Short name T909
Test name
Test status
Simulation time 878392746 ps
CPU time 3.03 seconds
Started Jul 05 05:52:03 PM PDT 24
Finished Jul 05 05:52:07 PM PDT 24
Peak memory 200872 kb
Host smart-65f1408b-7b84-48b4-804f-a37571010f16
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549179251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.549179251
Directory /workspace/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.480517802
Short name T799
Test name
Test status
Simulation time 104000280 ps
CPU time 0.82 seconds
Started Jul 05 05:52:16 PM PDT 24
Finished Jul 05 05:52:18 PM PDT 24
Peak memory 199004 kb
Host smart-540c3a13-539c-4e0b-b19d-2e2b0b9abe0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480517802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_
mubi.480517802
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.3095211109
Short name T833
Test name
Test status
Simulation time 52958521 ps
CPU time 0.67 seconds
Started Jul 05 05:52:03 PM PDT 24
Finished Jul 05 05:52:05 PM PDT 24
Peak memory 199156 kb
Host smart-d729bdde-0d88-4f6b-9d95-2d72cc184aa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095211109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3095211109
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all_with_rand_reset.3276162453
Short name T369
Test name
Test status
Simulation time 6730580258 ps
CPU time 14.34 seconds
Started Jul 05 05:51:59 PM PDT 24
Finished Jul 05 05:52:14 PM PDT 24
Peak memory 201100 kb
Host smart-18ccf2de-ea83-4e27-92ef-bff4733961db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276162453 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all_with_rand_reset.3276162453
Directory /workspace/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup.2252342753
Short name T215
Test name
Test status
Simulation time 291564032 ps
CPU time 1.34 seconds
Started Jul 05 05:51:53 PM PDT 24
Finished Jul 05 05:51:56 PM PDT 24
Peak memory 199504 kb
Host smart-0e4a1471-fd92-4595-91bc-556f3d6cffdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252342753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.2252342753
Directory /workspace/30.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.2928050912
Short name T398
Test name
Test status
Simulation time 373208776 ps
CPU time 1.32 seconds
Started Jul 05 05:52:09 PM PDT 24
Finished Jul 05 05:52:11 PM PDT 24
Peak memory 200936 kb
Host smart-854754cf-5968-4056-abfb-68df9b7e1bda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928050912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.2928050912
Directory /workspace/30.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.4249708192
Short name T427
Test name
Test status
Simulation time 48621865 ps
CPU time 0.72 seconds
Started Jul 05 05:52:03 PM PDT 24
Finished Jul 05 05:52:05 PM PDT 24
Peak memory 198880 kb
Host smart-b49bc865-2c41-4e27-92d1-063540e8a852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249708192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.4249708192
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.1895479517
Short name T448
Test name
Test status
Simulation time 67663881 ps
CPU time 0.73 seconds
Started Jul 05 05:51:57 PM PDT 24
Finished Jul 05 05:51:59 PM PDT 24
Peak memory 198468 kb
Host smart-859ed46a-10ec-4fe9-bb26-2844dba382c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895479517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.1895479517
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2788783057
Short name T711
Test name
Test status
Simulation time 30903047 ps
CPU time 0.64 seconds
Started Jul 05 05:51:58 PM PDT 24
Finished Jul 05 05:52:00 PM PDT 24
Peak memory 197776 kb
Host smart-b00070d6-7f7b-4670-92dd-29fac5698769
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788783057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.2788783057
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.3224661804
Short name T884
Test name
Test status
Simulation time 162027493 ps
CPU time 0.99 seconds
Started Jul 05 05:52:14 PM PDT 24
Finished Jul 05 05:52:15 PM PDT 24
Peak memory 198164 kb
Host smart-a3d496dd-15e0-4e16-8f9e-e1c8987b9c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224661804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.3224661804
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.228665313
Short name T399
Test name
Test status
Simulation time 39802280 ps
CPU time 0.6 seconds
Started Jul 05 05:51:54 PM PDT 24
Finished Jul 05 05:51:57 PM PDT 24
Peak memory 197876 kb
Host smart-c5ee9523-c46a-4330-a9ef-7518e4cd9fdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228665313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.228665313
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.1699470021
Short name T932
Test name
Test status
Simulation time 121513743 ps
CPU time 0.6 seconds
Started Jul 05 05:52:03 PM PDT 24
Finished Jul 05 05:52:04 PM PDT 24
Peak memory 197812 kb
Host smart-60390f62-55c2-475a-a979-81fb403aec48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699470021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.1699470021
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.2556809544
Short name T49
Test name
Test status
Simulation time 43885587 ps
CPU time 0.72 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 201164 kb
Host smart-8079ce77-81db-4ec0-930d-3f8cd981ce61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556809544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.2556809544
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.1159079219
Short name T999
Test name
Test status
Simulation time 241296608 ps
CPU time 1.2 seconds
Started Jul 05 05:51:54 PM PDT 24
Finished Jul 05 05:51:57 PM PDT 24
Peak memory 199372 kb
Host smart-dff67670-04d4-4f09-a0f8-6e22e362ceed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159079219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_w
akeup_race.1159079219
Directory /workspace/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.3748356152
Short name T516
Test name
Test status
Simulation time 80009000 ps
CPU time 0.82 seconds
Started Jul 05 05:51:52 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 198328 kb
Host smart-1de99efd-b6fa-4f43-8b94-a18024c21daa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748356152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.3748356152
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.1035297285
Short name T256
Test name
Test status
Simulation time 99560635 ps
CPU time 0.99 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 209252 kb
Host smart-60798200-0a34-45b0-87a7-2a4b6476151f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035297285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.1035297285
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.723818941
Short name T460
Test name
Test status
Simulation time 812884793 ps
CPU time 3.14 seconds
Started Jul 05 05:52:03 PM PDT 24
Finished Jul 05 05:52:08 PM PDT 24
Peak memory 200868 kb
Host smart-2af9526c-83e1-430d-a3af-b2a9c1d1e444
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723818941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.723818941
Directory /workspace/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2465883034
Short name T311
Test name
Test status
Simulation time 933677879 ps
CPU time 2.52 seconds
Started Jul 05 05:52:05 PM PDT 24
Finished Jul 05 05:52:08 PM PDT 24
Peak memory 200612 kb
Host smart-36706cb9-45fc-4412-a421-68aaa06cf5f0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465883034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2465883034
Directory /workspace/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3241881754
Short name T107
Test name
Test status
Simulation time 188647360 ps
CPU time 0.87 seconds
Started Jul 05 05:52:14 PM PDT 24
Finished Jul 05 05:52:16 PM PDT 24
Peak memory 199164 kb
Host smart-c37780f5-5cdf-4936-ae7e-37da8e477378
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241881754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3241881754
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.173283088
Short name T81
Test name
Test status
Simulation time 40140924 ps
CPU time 0.71 seconds
Started Jul 05 05:51:54 PM PDT 24
Finished Jul 05 05:51:56 PM PDT 24
Peak memory 199144 kb
Host smart-c709c505-f0e0-4e89-bf16-975138aeb131
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173283088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.173283088
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all.306769819
Short name T240
Test name
Test status
Simulation time 5151692131 ps
CPU time 3.49 seconds
Started Jul 05 05:52:21 PM PDT 24
Finished Jul 05 05:52:26 PM PDT 24
Peak memory 201024 kb
Host smart-15c4e1bf-9c1e-475c-8bd7-866cabacd154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306769819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.306769819
Directory /workspace/31.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all_with_rand_reset.3626153326
Short name T23
Test name
Test status
Simulation time 6812896824 ps
CPU time 15.78 seconds
Started Jul 05 05:51:58 PM PDT 24
Finished Jul 05 05:52:15 PM PDT 24
Peak memory 201140 kb
Host smart-90226e9f-c1e1-44a7-ac75-f3916c82fa63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626153326 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all_with_rand_reset.3626153326
Directory /workspace/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup.1375201949
Short name T723
Test name
Test status
Simulation time 197497106 ps
CPU time 0.78 seconds
Started Jul 05 05:51:58 PM PDT 24
Finished Jul 05 05:52:01 PM PDT 24
Peak memory 198196 kb
Host smart-71943c8f-5a7e-40ad-9529-03afd646acce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375201949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.1375201949
Directory /workspace/31.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup_reset.3369011662
Short name T942
Test name
Test status
Simulation time 357069258 ps
CPU time 0.99 seconds
Started Jul 05 05:51:53 PM PDT 24
Finished Jul 05 05:51:56 PM PDT 24
Peak memory 200076 kb
Host smart-d4ad0def-dc5b-476d-b27f-2bbef4854c8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369011662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.3369011662
Directory /workspace/31.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.2443873199
Short name T150
Test name
Test status
Simulation time 24751650 ps
CPU time 0.69 seconds
Started Jul 05 05:52:16 PM PDT 24
Finished Jul 05 05:52:18 PM PDT 24
Peak memory 198404 kb
Host smart-a34a4cdf-080f-48a9-8d92-9b096731f61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443873199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.2443873199
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.659673806
Short name T177
Test name
Test status
Simulation time 56565459 ps
CPU time 0.8 seconds
Started Jul 05 05:52:07 PM PDT 24
Finished Jul 05 05:52:08 PM PDT 24
Peak memory 198828 kb
Host smart-d9294737-7423-4c80-a535-f0bca619fa2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659673806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disa
ble_rom_integrity_check.659673806
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.3081575949
Short name T666
Test name
Test status
Simulation time 34893221 ps
CPU time 0.6 seconds
Started Jul 05 05:52:17 PM PDT 24
Finished Jul 05 05:52:19 PM PDT 24
Peak memory 197076 kb
Host smart-7602fa42-e317-404f-9426-d7962ea16e2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081575949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.3081575949
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.4094181150
Short name T312
Test name
Test status
Simulation time 166178698 ps
CPU time 0.96 seconds
Started Jul 05 05:51:59 PM PDT 24
Finished Jul 05 05:52:01 PM PDT 24
Peak memory 198148 kb
Host smart-768d6c7a-a9e4-464b-9eb8-77e8d6079420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094181150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.4094181150
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.378522154
Short name T795
Test name
Test status
Simulation time 56397836 ps
CPU time 0.62 seconds
Started Jul 05 05:51:58 PM PDT 24
Finished Jul 05 05:52:00 PM PDT 24
Peak memory 197872 kb
Host smart-55c6a6c0-c112-4746-9e5f-719b886ebe86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378522154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.378522154
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.1978848256
Short name T273
Test name
Test status
Simulation time 72691196 ps
CPU time 0.63 seconds
Started Jul 05 05:52:17 PM PDT 24
Finished Jul 05 05:52:18 PM PDT 24
Peak memory 197864 kb
Host smart-ec08aee4-a329-4889-8c15-2bb1286aa2a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978848256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.1978848256
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.678589544
Short name T414
Test name
Test status
Simulation time 57369427 ps
CPU time 0.68 seconds
Started Jul 05 05:51:55 PM PDT 24
Finished Jul 05 05:51:58 PM PDT 24
Peak memory 201016 kb
Host smart-0335a0ba-8fd5-4303-a1db-d10f4b42dc05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678589544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invali
d.678589544
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_wakeup_race.2619921355
Short name T952
Test name
Test status
Simulation time 91256149 ps
CPU time 0.83 seconds
Started Jul 05 05:52:00 PM PDT 24
Finished Jul 05 05:52:02 PM PDT 24
Peak memory 198108 kb
Host smart-c2308807-313f-4239-bcfc-b7b9dda8533c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619921355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_w
akeup_race.2619921355
Directory /workspace/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.199922283
Short name T37
Test name
Test status
Simulation time 105578960 ps
CPU time 0.72 seconds
Started Jul 05 05:52:20 PM PDT 24
Finished Jul 05 05:52:22 PM PDT 24
Peak memory 198940 kb
Host smart-10d995b7-6727-4dcf-93b9-e3404b1e43a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199922283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.199922283
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.1981181950
Short name T676
Test name
Test status
Simulation time 106492533 ps
CPU time 0.96 seconds
Started Jul 05 05:51:56 PM PDT 24
Finished Jul 05 05:51:59 PM PDT 24
Peak memory 209328 kb
Host smart-fd5975ba-1c1f-41d6-bd6d-7c589903c24e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981181950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.1981181950
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.4205162858
Short name T465
Test name
Test status
Simulation time 96746134 ps
CPU time 0.82 seconds
Started Jul 05 05:52:00 PM PDT 24
Finished Jul 05 05:52:02 PM PDT 24
Peak memory 198452 kb
Host smart-a608225d-d0a7-40cb-9df8-8281dab4f02e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205162858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_
cm_ctrl_config_regwen.4205162858
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.429389419
Short name T112
Test name
Test status
Simulation time 1123640500 ps
CPU time 2.24 seconds
Started Jul 05 05:52:02 PM PDT 24
Finished Jul 05 05:52:05 PM PDT 24
Peak memory 200732 kb
Host smart-da5d3803-9390-4d29-bf65-d2509a19cbd8
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429389419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.429389419
Directory /workspace/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1871880446
Short name T250
Test name
Test status
Simulation time 1757914552 ps
CPU time 2.13 seconds
Started Jul 05 05:52:16 PM PDT 24
Finished Jul 05 05:52:19 PM PDT 24
Peak memory 200808 kb
Host smart-023d0192-68a5-4a57-b974-c73bb1c64fcc
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871880446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1871880446
Directory /workspace/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2531591351
Short name T116
Test name
Test status
Simulation time 200592719 ps
CPU time 0.8 seconds
Started Jul 05 05:51:56 PM PDT 24
Finished Jul 05 05:51:58 PM PDT 24
Peak memory 198980 kb
Host smart-bbd8a22c-ce3b-4b02-a39b-480e19e73ab2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531591351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2531591351
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.3215722505
Short name T819
Test name
Test status
Simulation time 106864362 ps
CPU time 0.64 seconds
Started Jul 05 05:52:12 PM PDT 24
Finished Jul 05 05:52:13 PM PDT 24
Peak memory 198288 kb
Host smart-912f1e90-f92a-4517-ba2a-98a8ce4b0a57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215722505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.3215722505
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all.2345251655
Short name T572
Test name
Test status
Simulation time 330610474 ps
CPU time 0.91 seconds
Started Jul 05 05:52:00 PM PDT 24
Finished Jul 05 05:52:02 PM PDT 24
Peak memory 199780 kb
Host smart-4dc74bc8-7e9a-42e7-86d7-f81c18bb72d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345251655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.2345251655
Directory /workspace/32.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all_with_rand_reset.4074373761
Short name T674
Test name
Test status
Simulation time 12801464520 ps
CPU time 17.23 seconds
Started Jul 05 05:51:54 PM PDT 24
Finished Jul 05 05:52:14 PM PDT 24
Peak memory 201136 kb
Host smart-c6d79869-26ff-4d9c-bfdd-93d06648a821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074373761 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all_with_rand_reset.4074373761
Directory /workspace/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.1036236310
Short name T216
Test name
Test status
Simulation time 264316750 ps
CPU time 1.05 seconds
Started Jul 05 05:52:22 PM PDT 24
Finished Jul 05 05:52:24 PM PDT 24
Peak memory 199404 kb
Host smart-5c3cc6be-a78a-4515-8ee1-04ff0727ce75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036236310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.1036236310
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup_reset.3642707771
Short name T213
Test name
Test status
Simulation time 401034269 ps
CPU time 1.06 seconds
Started Jul 05 05:51:56 PM PDT 24
Finished Jul 05 05:51:59 PM PDT 24
Peak memory 200744 kb
Host smart-942d542d-0905-454c-a98a-79826fc5d531
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642707771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.3642707771
Directory /workspace/32.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.563383827
Short name T232
Test name
Test status
Simulation time 158331172 ps
CPU time 0.96 seconds
Started Jul 05 05:52:12 PM PDT 24
Finished Jul 05 05:52:14 PM PDT 24
Peak memory 200000 kb
Host smart-6edb8a81-401e-4b29-b0ff-eecb6a2726b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563383827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.563383827
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.4128297066
Short name T365
Test name
Test status
Simulation time 48292795 ps
CPU time 0.78 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 198924 kb
Host smart-6fd41624-b64e-4998-a05b-cfe78eb7e83e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128297066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.4128297066
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2275622744
Short name T385
Test name
Test status
Simulation time 32215668 ps
CPU time 0.62 seconds
Started Jul 05 05:52:24 PM PDT 24
Finished Jul 05 05:52:26 PM PDT 24
Peak memory 197780 kb
Host smart-bee04282-c6a2-4ae1-bf2e-8d0d9ba28532
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275622744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.2275622744
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.2215373192
Short name T703
Test name
Test status
Simulation time 296007553 ps
CPU time 0.97 seconds
Started Jul 05 05:52:03 PM PDT 24
Finished Jul 05 05:52:05 PM PDT 24
Peak memory 198128 kb
Host smart-7191094b-e498-433f-a95c-743ec49c4680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215373192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2215373192
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.3830730684
Short name T868
Test name
Test status
Simulation time 90991976 ps
CPU time 0.59 seconds
Started Jul 05 05:52:20 PM PDT 24
Finished Jul 05 05:52:22 PM PDT 24
Peak memory 197852 kb
Host smart-d504c654-31a3-4a8e-9d74-d5f2761f8d7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830730684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.3830730684
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.1287268871
Short name T538
Test name
Test status
Simulation time 112909336 ps
CPU time 0.61 seconds
Started Jul 05 05:52:14 PM PDT 24
Finished Jul 05 05:52:15 PM PDT 24
Peak memory 197876 kb
Host smart-22a0abbd-2aa1-44a1-a90a-9218307f6142
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287268871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.1287268871
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.1930244279
Short name T154
Test name
Test status
Simulation time 76183312 ps
CPU time 0.69 seconds
Started Jul 05 05:52:19 PM PDT 24
Finished Jul 05 05:52:21 PM PDT 24
Peak memory 201116 kb
Host smart-6de6f528-0944-4403-bf53-a2ce88b81287
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930244279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.1930244279
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.1100519056
Short name T313
Test name
Test status
Simulation time 163468621 ps
CPU time 0.67 seconds
Started Jul 05 05:52:14 PM PDT 24
Finished Jul 05 05:52:15 PM PDT 24
Peak memory 198076 kb
Host smart-c831f60f-3ceb-450a-8150-8d28d3b70d39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100519056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_w
akeup_race.1100519056
Directory /workspace/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.965677103
Short name T340
Test name
Test status
Simulation time 76861247 ps
CPU time 0.99 seconds
Started Jul 05 05:52:16 PM PDT 24
Finished Jul 05 05:52:18 PM PDT 24
Peak memory 199744 kb
Host smart-14f1f93d-79a9-4966-83b9-cfc70c91312f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965677103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.965677103
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.4210958680
Short name T421
Test name
Test status
Simulation time 95870431 ps
CPU time 1.14 seconds
Started Jul 05 05:52:31 PM PDT 24
Finished Jul 05 05:52:33 PM PDT 24
Peak memory 209328 kb
Host smart-ee82cdbd-83ac-41eb-b8de-b5e729c0782d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210958680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.4210958680
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.2369237234
Short name T731
Test name
Test status
Simulation time 170459448 ps
CPU time 1.05 seconds
Started Jul 05 05:52:15 PM PDT 24
Finished Jul 05 05:52:18 PM PDT 24
Peak memory 199824 kb
Host smart-3712d0b3-30a9-4bb6-9a6c-258f1ee3267a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369237234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_
cm_ctrl_config_regwen.2369237234
Directory /workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4205635979
Short name T710
Test name
Test status
Simulation time 891792814 ps
CPU time 2.84 seconds
Started Jul 05 05:52:17 PM PDT 24
Finished Jul 05 05:52:21 PM PDT 24
Peak memory 200892 kb
Host smart-af7da28f-6ceb-442e-be15-8e7123e7efe8
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205635979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4205635979
Directory /workspace/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2280584059
Short name T360
Test name
Test status
Simulation time 1536308954 ps
CPU time 1.85 seconds
Started Jul 05 05:51:58 PM PDT 24
Finished Jul 05 05:52:01 PM PDT 24
Peak memory 200948 kb
Host smart-66345caa-936b-44bc-b09a-be21f1c0439e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280584059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2280584059
Directory /workspace/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.1396945668
Short name T97
Test name
Test status
Simulation time 60580520 ps
CPU time 0.86 seconds
Started Jul 05 05:52:19 PM PDT 24
Finished Jul 05 05:52:21 PM PDT 24
Peak memory 199044 kb
Host smart-0791c4a2-fa56-4c17-a492-13bccfb846c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396945668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1396945668
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.2390844779
Short name T963
Test name
Test status
Simulation time 171616261 ps
CPU time 0.62 seconds
Started Jul 05 05:51:58 PM PDT 24
Finished Jul 05 05:52:00 PM PDT 24
Peak memory 198364 kb
Host smart-3be41e9e-9159-482f-9485-7faecf1b40bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390844779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.2390844779
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all.1531740403
Short name T623
Test name
Test status
Simulation time 2517862307 ps
CPU time 5.85 seconds
Started Jul 05 05:52:22 PM PDT 24
Finished Jul 05 05:52:29 PM PDT 24
Peak memory 201028 kb
Host smart-d2291111-ef0d-41fb-bb1f-350c16cae2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531740403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.1531740403
Directory /workspace/33.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all_with_rand_reset.1847684760
Short name T22
Test name
Test status
Simulation time 14217039077 ps
CPU time 20.56 seconds
Started Jul 05 05:52:01 PM PDT 24
Finished Jul 05 05:52:22 PM PDT 24
Peak memory 201136 kb
Host smart-69c45525-dc53-49a7-8ff8-b719acbf8aab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847684760 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all_with_rand_reset.1847684760
Directory /workspace/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup.1772383483
Short name T500
Test name
Test status
Simulation time 120532489 ps
CPU time 0.71 seconds
Started Jul 05 05:52:16 PM PDT 24
Finished Jul 05 05:52:18 PM PDT 24
Peak memory 198084 kb
Host smart-284ce23e-7430-4cad-bd88-6624e8973c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772383483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.1772383483
Directory /workspace/33.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup_reset.944105206
Short name T730
Test name
Test status
Simulation time 48286989 ps
CPU time 0.63 seconds
Started Jul 05 05:52:12 PM PDT 24
Finished Jul 05 05:52:14 PM PDT 24
Peak memory 198696 kb
Host smart-8d2356d4-6c18-4ec5-8c66-4303ab938dbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944105206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.944105206
Directory /workspace/33.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.3977580054
Short name T468
Test name
Test status
Simulation time 138639223 ps
CPU time 0.87 seconds
Started Jul 05 05:52:20 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 200008 kb
Host smart-e60bfc76-9de3-4c00-afb6-00599d066615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977580054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.3977580054
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.2111298240
Short name T529
Test name
Test status
Simulation time 30066155 ps
CPU time 0.67 seconds
Started Jul 05 05:52:20 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 197076 kb
Host smart-aacb8ba3-5d1c-4507-9fc2-9abb9a07ef3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111298240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.2111298240
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.3017513622
Short name T341
Test name
Test status
Simulation time 161204005 ps
CPU time 0.94 seconds
Started Jul 05 05:52:07 PM PDT 24
Finished Jul 05 05:52:08 PM PDT 24
Peak memory 197868 kb
Host smart-a309aedd-c5e8-4f8e-879c-047325d14713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017513622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.3017513622
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.3189085713
Short name T528
Test name
Test status
Simulation time 35317709 ps
CPU time 0.62 seconds
Started Jul 05 05:52:26 PM PDT 24
Finished Jul 05 05:52:37 PM PDT 24
Peak memory 197820 kb
Host smart-1685d794-94fc-4a3a-9f58-39fc18a76b7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189085713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.3189085713
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.1782085069
Short name T680
Test name
Test status
Simulation time 35108150 ps
CPU time 0.61 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 197856 kb
Host smart-4df0da3f-28e0-405a-b39f-5f1a2c95ee3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782085069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.1782085069
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.2431038190
Short name T801
Test name
Test status
Simulation time 44851586 ps
CPU time 0.7 seconds
Started Jul 05 05:52:17 PM PDT 24
Finished Jul 05 05:52:19 PM PDT 24
Peak memory 201136 kb
Host smart-ec6296ca-33b6-4e2b-9d15-08c6f7346a6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431038190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.2431038190
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.1942109827
Short name T511
Test name
Test status
Simulation time 123368132 ps
CPU time 0.8 seconds
Started Jul 05 05:52:15 PM PDT 24
Finished Jul 05 05:52:17 PM PDT 24
Peak memory 198280 kb
Host smart-2e001c60-b6f6-4702-872e-0206891e4ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942109827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_w
akeup_race.1942109827
Directory /workspace/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.988082249
Short name T223
Test name
Test status
Simulation time 59157607 ps
CPU time 0.67 seconds
Started Jul 05 05:52:15 PM PDT 24
Finished Jul 05 05:52:17 PM PDT 24
Peak memory 198876 kb
Host smart-6e8cffda-634e-4db4-ac75-c6e8c40ea14d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988082249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.988082249
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.2336434795
Short name T530
Test name
Test status
Simulation time 94357583 ps
CPU time 0.99 seconds
Started Jul 05 05:52:26 PM PDT 24
Finished Jul 05 05:52:28 PM PDT 24
Peak memory 201088 kb
Host smart-67526481-835e-4280-997e-fe9bba49536a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336434795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.2336434795
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.2020635165
Short name T357
Test name
Test status
Simulation time 357347282 ps
CPU time 1.2 seconds
Started Jul 05 05:52:11 PM PDT 24
Finished Jul 05 05:52:12 PM PDT 24
Peak memory 199760 kb
Host smart-8a0d60a4-b145-4349-972a-275dd48a87c2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020635165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_
cm_ctrl_config_regwen.2020635165
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.891584213
Short name T971
Test name
Test status
Simulation time 830225084 ps
CPU time 2.41 seconds
Started Jul 05 05:52:16 PM PDT 24
Finished Jul 05 05:52:20 PM PDT 24
Peak memory 200884 kb
Host smart-5f2929bc-3cf0-4dcf-9a44-bf7523dd5bd9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891584213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.891584213
Directory /workspace/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.937641914
Short name T300
Test name
Test status
Simulation time 898027897 ps
CPU time 2.4 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:22 PM PDT 24
Peak memory 200988 kb
Host smart-2997d2f7-aab0-4d7f-9a71-bdc88937c2e0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937641914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.937641914
Directory /workspace/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1315095706
Short name T933
Test name
Test status
Simulation time 93523671 ps
CPU time 0.89 seconds
Started Jul 05 05:52:17 PM PDT 24
Finished Jul 05 05:52:22 PM PDT 24
Peak memory 198992 kb
Host smart-5a7263b6-582a-406a-8e56-16a9cf595c97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315095706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1315095706
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.2002826489
Short name T269
Test name
Test status
Simulation time 32562421 ps
CPU time 0.7 seconds
Started Jul 05 05:52:02 PM PDT 24
Finished Jul 05 05:52:04 PM PDT 24
Peak memory 198188 kb
Host smart-2d91b5b0-7071-4f2e-af43-33d75d2301b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002826489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.2002826489
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all.1445206293
Short name T891
Test name
Test status
Simulation time 1201707504 ps
CPU time 2.44 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:22 PM PDT 24
Peak memory 200912 kb
Host smart-0ec9787a-6f64-4621-b5e1-081c111ecde0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445206293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.1445206293
Directory /workspace/34.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all_with_rand_reset.13736520
Short name T458
Test name
Test status
Simulation time 7245029119 ps
CPU time 10.88 seconds
Started Jul 05 05:52:23 PM PDT 24
Finished Jul 05 05:52:36 PM PDT 24
Peak memory 201160 kb
Host smart-7e11ae35-f8bd-46a7-8565-07c096235d59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13736520 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all_with_rand_reset.13736520
Directory /workspace/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup.562709880
Short name T304
Test name
Test status
Simulation time 46095169 ps
CPU time 0.63 seconds
Started Jul 05 05:52:25 PM PDT 24
Finished Jul 05 05:52:27 PM PDT 24
Peak memory 198276 kb
Host smart-b8944a28-2312-4f21-bdd0-6e912f28921d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562709880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.562709880
Directory /workspace/34.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup_reset.1354439392
Short name T331
Test name
Test status
Simulation time 71573052 ps
CPU time 0.86 seconds
Started Jul 05 05:52:28 PM PDT 24
Finished Jul 05 05:52:30 PM PDT 24
Peak memory 198672 kb
Host smart-f2fa5603-708c-4dd8-bcfa-b2313bcfbc96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354439392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.1354439392
Directory /workspace/34.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.3145716093
Short name T777
Test name
Test status
Simulation time 26299992 ps
CPU time 0.72 seconds
Started Jul 05 05:52:25 PM PDT 24
Finished Jul 05 05:52:27 PM PDT 24
Peak memory 198912 kb
Host smart-e7e71c3b-a299-439f-ad3b-63b0de457d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145716093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.3145716093
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.2079106358
Short name T955
Test name
Test status
Simulation time 50551968 ps
CPU time 0.79 seconds
Started Jul 05 05:52:25 PM PDT 24
Finished Jul 05 05:52:28 PM PDT 24
Peak memory 198936 kb
Host smart-2527edba-b38a-4db5-99a6-3e7c9b066fcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079106358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.2079106358
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.3869721897
Short name T941
Test name
Test status
Simulation time 28860792 ps
CPU time 0.63 seconds
Started Jul 05 05:52:19 PM PDT 24
Finished Jul 05 05:52:21 PM PDT 24
Peak memory 197772 kb
Host smart-000d04c4-4020-45b7-84be-d83ed4a67ac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869721897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.3869721897
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.667644076
Short name T617
Test name
Test status
Simulation time 166544384 ps
CPU time 1.02 seconds
Started Jul 05 05:52:14 PM PDT 24
Finished Jul 05 05:52:16 PM PDT 24
Peak memory 197848 kb
Host smart-f45d8101-6825-44f6-b0b6-59bdec0145cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667644076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.667644076
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.2800283391
Short name T330
Test name
Test status
Simulation time 29540156 ps
CPU time 0.61 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:19 PM PDT 24
Peak memory 198028 kb
Host smart-f062ee40-9908-4c2d-aa81-456fa2a1dbdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800283391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.2800283391
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.72385592
Short name T641
Test name
Test status
Simulation time 37728390 ps
CPU time 0.65 seconds
Started Jul 05 05:52:21 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 197832 kb
Host smart-03eb2fff-8f6c-4bac-b29e-59e7576f62a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72385592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.72385592
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.1320020295
Short name T923
Test name
Test status
Simulation time 45177555 ps
CPU time 0.75 seconds
Started Jul 05 05:52:29 PM PDT 24
Finished Jul 05 05:52:30 PM PDT 24
Peak memory 201168 kb
Host smart-3eb5b7e6-a40d-41a5-bdc7-67d556754423
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320020295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.1320020295
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.3057995690
Short name T221
Test name
Test status
Simulation time 71740021 ps
CPU time 0.73 seconds
Started Jul 05 05:52:21 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 198088 kb
Host smart-afbbb948-c8aa-4453-a1f5-b02ac752ba74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057995690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_w
akeup_race.3057995690
Directory /workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.3928677691
Short name T698
Test name
Test status
Simulation time 53878618 ps
CPU time 0.86 seconds
Started Jul 05 05:52:28 PM PDT 24
Finished Jul 05 05:52:30 PM PDT 24
Peak memory 198952 kb
Host smart-b6162b4e-d414-4435-9bf1-473adec81809
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928677691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.3928677691
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.1845962610
Short name T637
Test name
Test status
Simulation time 170120986 ps
CPU time 0.82 seconds
Started Jul 05 05:52:22 PM PDT 24
Finished Jul 05 05:52:25 PM PDT 24
Peak memory 209332 kb
Host smart-41b09ef1-1715-4306-b808-463b2c8ba9d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845962610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.1845962610
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.3884800278
Short name T202
Test name
Test status
Simulation time 155831714 ps
CPU time 0.88 seconds
Started Jul 05 05:52:14 PM PDT 24
Finished Jul 05 05:52:15 PM PDT 24
Peak memory 198856 kb
Host smart-ce175e86-5e03-45df-b7fd-994c685e0e78
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884800278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_
cm_ctrl_config_regwen.3884800278
Directory /workspace/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.128468273
Short name T317
Test name
Test status
Simulation time 1255593064 ps
CPU time 2.2 seconds
Started Jul 05 05:52:20 PM PDT 24
Finished Jul 05 05:52:24 PM PDT 24
Peak memory 200884 kb
Host smart-04297c2e-2f98-499d-a12b-ee98dd9d62ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128468273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.128468273
Directory /workspace/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2239706267
Short name T36
Test name
Test status
Simulation time 980671832 ps
CPU time 2.06 seconds
Started Jul 05 05:52:20 PM PDT 24
Finished Jul 05 05:52:24 PM PDT 24
Peak memory 200896 kb
Host smart-7acd6434-b7bf-4836-8b1b-8f73ffc69068
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239706267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2239706267
Directory /workspace/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2692344913
Short name T632
Test name
Test status
Simulation time 75557631 ps
CPU time 0.95 seconds
Started Jul 05 05:52:21 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 199088 kb
Host smart-a0bc3f6b-565f-4e67-b4c2-fb12fe3285bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692344913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2692344913
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.1960874969
Short name T736
Test name
Test status
Simulation time 31950022 ps
CPU time 0.67 seconds
Started Jul 05 05:52:21 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 198272 kb
Host smart-015e3e1e-72d6-4a18-b43f-5a619aceee9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960874969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.1960874969
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all.3790390764
Short name T86
Test name
Test status
Simulation time 1228481781 ps
CPU time 4.62 seconds
Started Jul 05 05:52:25 PM PDT 24
Finished Jul 05 05:52:31 PM PDT 24
Peak memory 200952 kb
Host smart-62cbbc2f-9a37-48e5-b622-3a48fb67cc15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790390764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.3790390764
Directory /workspace/35.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all_with_rand_reset.432089714
Short name T151
Test name
Test status
Simulation time 9896299860 ps
CPU time 13.64 seconds
Started Jul 05 05:52:26 PM PDT 24
Finished Jul 05 05:52:41 PM PDT 24
Peak memory 201156 kb
Host smart-c14627c0-8a90-475c-acef-16d04e78e5f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432089714 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all_with_rand_reset.432089714
Directory /workspace/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup.664996998
Short name T725
Test name
Test status
Simulation time 127696889 ps
CPU time 0.72 seconds
Started Jul 05 05:52:16 PM PDT 24
Finished Jul 05 05:52:18 PM PDT 24
Peak memory 198264 kb
Host smart-6a3fdbdb-d29e-456e-9aeb-63977cfbc064
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664996998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.664996998
Directory /workspace/35.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup_reset.1044349782
Short name T612
Test name
Test status
Simulation time 254728978 ps
CPU time 1.32 seconds
Started Jul 05 05:52:23 PM PDT 24
Finished Jul 05 05:52:26 PM PDT 24
Peak memory 199724 kb
Host smart-5ff4a339-4809-40fa-b247-5f2a4f7da204
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044349782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.1044349782
Directory /workspace/35.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.860588424
Short name T88
Test name
Test status
Simulation time 104077148 ps
CPU time 0.81 seconds
Started Jul 05 05:52:22 PM PDT 24
Finished Jul 05 05:52:24 PM PDT 24
Peak memory 199800 kb
Host smart-0fdcde0c-0918-40e2-912b-79642ac8fb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860588424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.860588424
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.2875139709
Short name T274
Test name
Test status
Simulation time 56921814 ps
CPU time 0.84 seconds
Started Jul 05 05:52:25 PM PDT 24
Finished Jul 05 05:52:27 PM PDT 24
Peak memory 198284 kb
Host smart-2018835e-9cf9-41fd-aa65-6f71c744e4a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875139709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.2875139709
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.29515675
Short name T729
Test name
Test status
Simulation time 37500570 ps
CPU time 0.6 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:20 PM PDT 24
Peak memory 197796 kb
Host smart-9bac09f3-2d23-45d0-9a22-cd12f91920b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29515675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_m
alfunc.29515675
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.3640288765
Short name T815
Test name
Test status
Simulation time 759430612 ps
CPU time 0.97 seconds
Started Jul 05 05:52:25 PM PDT 24
Finished Jul 05 05:52:28 PM PDT 24
Peak memory 197856 kb
Host smart-6c51d807-90f4-457d-a710-89af59261c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640288765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.3640288765
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.530703337
Short name T17
Test name
Test status
Simulation time 61865070 ps
CPU time 0.65 seconds
Started Jul 05 05:52:22 PM PDT 24
Finished Jul 05 05:52:24 PM PDT 24
Peak memory 197184 kb
Host smart-9cce0aa6-06c0-4bf1-a415-a9322f8c19dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530703337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.530703337
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.767664496
Short name T665
Test name
Test status
Simulation time 30234129 ps
CPU time 0.63 seconds
Started Jul 05 05:52:20 PM PDT 24
Finished Jul 05 05:52:22 PM PDT 24
Peak memory 197852 kb
Host smart-ccecff11-aa1b-4e3a-8c77-c1bbdcc67726
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767664496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.767664496
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.1020838513
Short name T581
Test name
Test status
Simulation time 41451636 ps
CPU time 0.74 seconds
Started Jul 05 05:52:23 PM PDT 24
Finished Jul 05 05:52:25 PM PDT 24
Peak memory 200748 kb
Host smart-9032a52d-9e33-41fb-86b5-301382d62bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020838513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.1020838513
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.2770379992
Short name T948
Test name
Test status
Simulation time 63687141 ps
CPU time 0.67 seconds
Started Jul 05 05:52:20 PM PDT 24
Finished Jul 05 05:52:22 PM PDT 24
Peak memory 198280 kb
Host smart-4923680c-0224-4a20-934a-26bdd7ae10de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770379992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_w
akeup_race.2770379992
Directory /workspace/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.368487046
Short name T521
Test name
Test status
Simulation time 78788047 ps
CPU time 0.71 seconds
Started Jul 05 05:52:21 PM PDT 24
Finished Jul 05 05:52:24 PM PDT 24
Peak memory 198876 kb
Host smart-97a1b708-38db-4169-bedf-d2caff3c7aea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368487046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.368487046
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.280966863
Short name T267
Test name
Test status
Simulation time 109581627 ps
CPU time 1.06 seconds
Started Jul 05 05:52:26 PM PDT 24
Finished Jul 05 05:52:28 PM PDT 24
Peak memory 209268 kb
Host smart-760f89f7-2c79-4cf3-b2e4-572158bbbd26
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280966863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.280966863
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.2443006700
Short name T370
Test name
Test status
Simulation time 248010404 ps
CPU time 1.32 seconds
Started Jul 05 05:52:26 PM PDT 24
Finished Jul 05 05:52:29 PM PDT 24
Peak memory 199668 kb
Host smart-ce6f7217-774b-4791-90af-0a24b1945934
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443006700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_
cm_ctrl_config_regwen.2443006700
Directory /workspace/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1783849530
Short name T875
Test name
Test status
Simulation time 1161003621 ps
CPU time 2.12 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:22 PM PDT 24
Peak memory 200916 kb
Host smart-009c9734-50ee-40a6-8ac9-d54ea3f89e4a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783849530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1783849530
Directory /workspace/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1453926524
Short name T159
Test name
Test status
Simulation time 1307922969 ps
CPU time 2.34 seconds
Started Jul 05 05:52:16 PM PDT 24
Finished Jul 05 05:52:19 PM PDT 24
Peak memory 200820 kb
Host smart-27de90aa-e3a7-4efc-95c2-99850530d442
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453926524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1453926524
Directory /workspace/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.4170692111
Short name T198
Test name
Test status
Simulation time 111430341 ps
CPU time 0.83 seconds
Started Jul 05 05:52:23 PM PDT 24
Finished Jul 05 05:52:25 PM PDT 24
Peak memory 198932 kb
Host smart-efac7f80-6757-479d-8874-26a6d75cda5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170692111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4170692111
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.36090211
Short name T377
Test name
Test status
Simulation time 30457835 ps
CPU time 0.71 seconds
Started Jul 05 05:52:22 PM PDT 24
Finished Jul 05 05:52:24 PM PDT 24
Peak memory 199136 kb
Host smart-5d4aac98-51da-4002-bffe-522fbe5f8c1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36090211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.36090211
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all.1672593382
Short name T520
Test name
Test status
Simulation time 497852696 ps
CPU time 0.92 seconds
Started Jul 05 05:52:19 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 200772 kb
Host smart-69fce977-19af-4935-976e-d1d7dea2e606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672593382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.1672593382
Directory /workspace/36.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all_with_rand_reset.4125102451
Short name T951
Test name
Test status
Simulation time 16321745216 ps
CPU time 25.02 seconds
Started Jul 05 05:52:38 PM PDT 24
Finished Jul 05 05:53:04 PM PDT 24
Peak memory 201128 kb
Host smart-313a4e4b-d7e1-4779-aaca-6be5a20fa136
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125102451 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all_with_rand_reset.4125102451
Directory /workspace/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup.499977444
Short name T947
Test name
Test status
Simulation time 272636051 ps
CPU time 0.87 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:20 PM PDT 24
Peak memory 199384 kb
Host smart-148d8079-55dd-47e2-8d2f-7051610e9cac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499977444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.499977444
Directory /workspace/36.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup_reset.3612210837
Short name T258
Test name
Test status
Simulation time 325104880 ps
CPU time 0.92 seconds
Started Jul 05 05:52:17 PM PDT 24
Finished Jul 05 05:52:19 PM PDT 24
Peak memory 199992 kb
Host smart-544391cf-7afb-488e-9558-d4bdd4a8878f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612210837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.3612210837
Directory /workspace/36.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.3679114365
Short name T722
Test name
Test status
Simulation time 30585579 ps
CPU time 1.08 seconds
Started Jul 05 05:52:23 PM PDT 24
Finished Jul 05 05:52:26 PM PDT 24
Peak memory 200724 kb
Host smart-fd3a408c-e042-4fb9-866e-c208cfa6c229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679114365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.3679114365
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.451138995
Short name T319
Test name
Test status
Simulation time 68245348 ps
CPU time 0.92 seconds
Started Jul 05 05:52:30 PM PDT 24
Finished Jul 05 05:52:31 PM PDT 24
Peak memory 198828 kb
Host smart-d60e4b40-5c16-446d-ba54-8173891dbad6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451138995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disa
ble_rom_integrity_check.451138995
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.2626834691
Short name T613
Test name
Test status
Simulation time 33359464 ps
CPU time 0.6 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:20 PM PDT 24
Peak memory 197980 kb
Host smart-6f717f43-58d3-4f3c-8c82-96dbb675eec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626834691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.2626834691
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.639403885
Short name T989
Test name
Test status
Simulation time 322492483 ps
CPU time 0.98 seconds
Started Jul 05 05:52:21 PM PDT 24
Finished Jul 05 05:52:24 PM PDT 24
Peak memory 197856 kb
Host smart-fa4e92e4-8e50-40d5-a392-878f6ed13164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639403885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.639403885
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.2540967686
Short name T878
Test name
Test status
Simulation time 30741480 ps
CPU time 0.62 seconds
Started Jul 05 05:52:27 PM PDT 24
Finished Jul 05 05:52:29 PM PDT 24
Peak memory 197900 kb
Host smart-148c90fb-7b84-4d76-89cf-d50839f5c870
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540967686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.2540967686
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.2720402654
Short name T925
Test name
Test status
Simulation time 49607945 ps
CPU time 0.62 seconds
Started Jul 05 05:52:21 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 197852 kb
Host smart-8daadbd3-00e3-4170-a2cb-e8ab42848191
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720402654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.2720402654
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.42259037
Short name T318
Test name
Test status
Simulation time 65701872 ps
CPU time 0.66 seconds
Started Jul 05 05:52:59 PM PDT 24
Finished Jul 05 05:53:00 PM PDT 24
Peak memory 201084 kb
Host smart-f7650eef-f096-488d-9c5a-1cc44cc7d97e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42259037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invalid
.42259037
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_wakeup_race.1546228458
Short name T657
Test name
Test status
Simulation time 72211920 ps
CPU time 0.78 seconds
Started Jul 05 05:52:22 PM PDT 24
Finished Jul 05 05:52:24 PM PDT 24
Peak memory 198312 kb
Host smart-8b8362db-3b4a-492d-a889-9d0129a0143b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546228458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_w
akeup_race.1546228458
Directory /workspace/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.2739348860
Short name T633
Test name
Test status
Simulation time 46614139 ps
CPU time 0.67 seconds
Started Jul 05 05:52:26 PM PDT 24
Finished Jul 05 05:52:28 PM PDT 24
Peak memory 198900 kb
Host smart-81acad22-470a-4a5e-97d9-6602c29dfabb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739348860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.2739348860
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.317855595
Short name T757
Test name
Test status
Simulation time 162572111 ps
CPU time 0.79 seconds
Started Jul 05 05:52:32 PM PDT 24
Finished Jul 05 05:52:33 PM PDT 24
Peak memory 209356 kb
Host smart-3fb3b8db-1295-4310-8582-0d07febadf02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317855595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.317855595
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.3964365672
Short name T235
Test name
Test status
Simulation time 140594224 ps
CPU time 0.69 seconds
Started Jul 05 05:52:24 PM PDT 24
Finished Jul 05 05:52:26 PM PDT 24
Peak memory 198596 kb
Host smart-2c45f034-8838-4cc4-b487-7ecd3772e717
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964365672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_
cm_ctrl_config_regwen.3964365672
Directory /workspace/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2622700049
Short name T157
Test name
Test status
Simulation time 1092289195 ps
CPU time 2.34 seconds
Started Jul 05 05:52:25 PM PDT 24
Finished Jul 05 05:52:29 PM PDT 24
Peak memory 200940 kb
Host smart-815204f3-060d-495a-9a0a-cb825aa0d06b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622700049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2622700049
Directory /workspace/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2293068200
Short name T975
Test name
Test status
Simulation time 1182241163 ps
CPU time 2.24 seconds
Started Jul 05 05:52:17 PM PDT 24
Finished Jul 05 05:52:21 PM PDT 24
Peak memory 200952 kb
Host smart-2e3d037d-ec79-496c-8cf2-4bafb974aaf6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293068200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2293068200
Directory /workspace/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2249533434
Short name T716
Test name
Test status
Simulation time 172819037 ps
CPU time 0.93 seconds
Started Jul 05 05:52:19 PM PDT 24
Finished Jul 05 05:52:22 PM PDT 24
Peak memory 199400 kb
Host smart-d8e2beac-e451-4f5d-9b0a-d21852bba51c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249533434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2249533434
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.1569624932
Short name T583
Test name
Test status
Simulation time 119644748 ps
CPU time 0.64 seconds
Started Jul 05 05:52:27 PM PDT 24
Finished Jul 05 05:52:29 PM PDT 24
Peak memory 198288 kb
Host smart-7f55340b-593d-4f1f-9a8c-dd2d8be5ca6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569624932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.1569624932
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all.2824314539
Short name T708
Test name
Test status
Simulation time 2648721999 ps
CPU time 3.95 seconds
Started Jul 05 05:52:32 PM PDT 24
Finished Jul 05 05:52:36 PM PDT 24
Peak memory 201048 kb
Host smart-8211886c-811b-4614-b405-9793f06f0e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824314539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.2824314539
Directory /workspace/37.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all_with_rand_reset.2840140514
Short name T750
Test name
Test status
Simulation time 10214211250 ps
CPU time 13.77 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:53:01 PM PDT 24
Peak memory 201052 kb
Host smart-694aa10a-d0c5-41dc-8677-8e397a7279e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840140514 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all_with_rand_reset.2840140514
Directory /workspace/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup.4182176262
Short name T435
Test name
Test status
Simulation time 516599130 ps
CPU time 0.93 seconds
Started Jul 05 05:52:22 PM PDT 24
Finished Jul 05 05:52:25 PM PDT 24
Peak memory 199444 kb
Host smart-51467dff-2794-4f71-9452-ae5285ec5568
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182176262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.4182176262
Directory /workspace/37.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup_reset.2367556801
Short name T376
Test name
Test status
Simulation time 408895760 ps
CPU time 1.28 seconds
Started Jul 05 05:52:20 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 200816 kb
Host smart-9963551c-7b8e-4915-abdb-0aa9090df2c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367556801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.2367556801
Directory /workspace/37.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.1348318654
Short name T105
Test name
Test status
Simulation time 117151674 ps
CPU time 0.77 seconds
Started Jul 05 05:52:25 PM PDT 24
Finished Jul 05 05:52:32 PM PDT 24
Peak memory 198688 kb
Host smart-edf87201-23ac-4c60-bc20-81750c931676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348318654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.1348318654
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.209064448
Short name T189
Test name
Test status
Simulation time 46985631 ps
CPU time 0.77 seconds
Started Jul 05 05:53:06 PM PDT 24
Finished Jul 05 05:53:08 PM PDT 24
Peak memory 198928 kb
Host smart-03299887-f7bb-4c0c-b6df-02c9d5348d15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209064448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disa
ble_rom_integrity_check.209064448
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.1753808324
Short name T855
Test name
Test status
Simulation time 38739835 ps
CPU time 0.57 seconds
Started Jul 05 05:52:41 PM PDT 24
Finished Jul 05 05:52:41 PM PDT 24
Peak memory 197764 kb
Host smart-5ad19bd5-fd0d-4656-9c0a-7f56fff9e899
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753808324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.1753808324
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.4013624426
Short name T451
Test name
Test status
Simulation time 2498916134 ps
CPU time 0.95 seconds
Started Jul 05 05:52:36 PM PDT 24
Finished Jul 05 05:52:38 PM PDT 24
Peak memory 197908 kb
Host smart-fa35ef3a-e294-4497-b91e-1e726c3c3654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013624426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.4013624426
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.3080786120
Short name T275
Test name
Test status
Simulation time 56410461 ps
CPU time 0.67 seconds
Started Jul 05 05:53:05 PM PDT 24
Finished Jul 05 05:53:08 PM PDT 24
Peak memory 197048 kb
Host smart-90282be5-93cb-4dbd-9475-fc4afa984a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080786120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.3080786120
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.3656988291
Short name T873
Test name
Test status
Simulation time 23352642 ps
CPU time 0.61 seconds
Started Jul 05 05:52:54 PM PDT 24
Finished Jul 05 05:52:55 PM PDT 24
Peak memory 197836 kb
Host smart-7cc2f18b-f1f2-4dca-8fcd-56c7a6ab86b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656988291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.3656988291
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.205313103
Short name T219
Test name
Test status
Simulation time 102194396 ps
CPU time 0.65 seconds
Started Jul 05 05:52:32 PM PDT 24
Finished Jul 05 05:52:33 PM PDT 24
Peak memory 201120 kb
Host smart-aa5dba85-3eda-4a30-8663-a88a02070d71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205313103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invali
d.205313103
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.404712882
Short name T671
Test name
Test status
Simulation time 68746656 ps
CPU time 0.74 seconds
Started Jul 05 05:52:27 PM PDT 24
Finished Jul 05 05:52:29 PM PDT 24
Peak memory 198132 kb
Host smart-06de85f1-4b4e-43f4-9197-d991320d1655
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404712882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wa
keup_race.404712882
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.3685940631
Short name T681
Test name
Test status
Simulation time 83632897 ps
CPU time 0.72 seconds
Started Jul 05 05:52:23 PM PDT 24
Finished Jul 05 05:52:25 PM PDT 24
Peak memory 198416 kb
Host smart-0d2da3ac-5386-4783-98fe-a1e63086ead6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685940631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3685940631
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.1516358077
Short name T48
Test name
Test status
Simulation time 205806477 ps
CPU time 0.83 seconds
Started Jul 05 05:52:27 PM PDT 24
Finished Jul 05 05:52:28 PM PDT 24
Peak memory 209276 kb
Host smart-fd32b162-af77-49ab-b390-bec82d083fae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516358077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.1516358077
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.1943780196
Short name T62
Test name
Test status
Simulation time 287343263 ps
CPU time 1.29 seconds
Started Jul 05 05:52:26 PM PDT 24
Finished Jul 05 05:52:29 PM PDT 24
Peak memory 199880 kb
Host smart-b155a5a0-9c32-4386-9b49-0b2257137459
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943780196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_
cm_ctrl_config_regwen.1943780196
Directory /workspace/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2731799059
Short name T557
Test name
Test status
Simulation time 827240982 ps
CPU time 2.31 seconds
Started Jul 05 05:52:49 PM PDT 24
Finished Jul 05 05:52:53 PM PDT 24
Peak memory 200856 kb
Host smart-c4747a55-b989-40f4-8adb-a88a7db7b363
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731799059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2731799059
Directory /workspace/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2147767153
Short name T471
Test name
Test status
Simulation time 1201811139 ps
CPU time 2.28 seconds
Started Jul 05 05:52:38 PM PDT 24
Finished Jul 05 05:52:41 PM PDT 24
Peak memory 200812 kb
Host smart-5f004837-2bd8-4b49-b99e-1363c8214e47
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147767153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2147767153
Directory /workspace/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3236919821
Short name T383
Test name
Test status
Simulation time 65047084 ps
CPU time 0.88 seconds
Started Jul 05 05:52:48 PM PDT 24
Finished Jul 05 05:52:51 PM PDT 24
Peak memory 198956 kb
Host smart-6ab37052-69dc-4af5-b472-44f9f97b87c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236919821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3236919821
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.60497216
Short name T196
Test name
Test status
Simulation time 31015520 ps
CPU time 0.71 seconds
Started Jul 05 05:52:28 PM PDT 24
Finished Jul 05 05:52:30 PM PDT 24
Peak memory 199144 kb
Host smart-aaf12f76-465a-4589-a688-4467fcc76776
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60497216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.60497216
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all.267248822
Short name T488
Test name
Test status
Simulation time 653176219 ps
CPU time 1.95 seconds
Started Jul 05 05:53:04 PM PDT 24
Finished Jul 05 05:53:08 PM PDT 24
Peak memory 200972 kb
Host smart-42b7381d-6069-48cd-bee3-0aec375e7669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267248822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.267248822
Directory /workspace/38.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all_with_rand_reset.1255335823
Short name T437
Test name
Test status
Simulation time 5929287679 ps
CPU time 18.16 seconds
Started Jul 05 05:52:23 PM PDT 24
Finished Jul 05 05:52:42 PM PDT 24
Peak memory 201068 kb
Host smart-6a90a918-bcca-487a-9aac-13d9ab941312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255335823 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all_with_rand_reset.1255335823
Directory /workspace/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup.64548573
Short name T83
Test name
Test status
Simulation time 147163445 ps
CPU time 0.73 seconds
Started Jul 05 05:52:30 PM PDT 24
Finished Jul 05 05:52:32 PM PDT 24
Peak memory 198088 kb
Host smart-eccdd0dc-5536-4abe-93a5-0b2fc57da8b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64548573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.64548573
Directory /workspace/38.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup_reset.3969859871
Short name T706
Test name
Test status
Simulation time 161221730 ps
CPU time 1.08 seconds
Started Jul 05 05:53:05 PM PDT 24
Finished Jul 05 05:53:08 PM PDT 24
Peak memory 200672 kb
Host smart-bf2c7fff-8b35-4695-9618-5224711835e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969859871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.3969859871
Directory /workspace/38.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.2559056035
Short name T514
Test name
Test status
Simulation time 197487961 ps
CPU time 0.68 seconds
Started Jul 05 05:52:29 PM PDT 24
Finished Jul 05 05:52:31 PM PDT 24
Peak memory 198388 kb
Host smart-de3515f1-8d14-4264-bdfb-513aa89df167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559056035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.2559056035
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.3535632695
Short name T624
Test name
Test status
Simulation time 57353341 ps
CPU time 0.89 seconds
Started Jul 05 05:53:01 PM PDT 24
Finished Jul 05 05:53:02 PM PDT 24
Peak memory 198920 kb
Host smart-f8ac5520-f5f4-4a59-9f41-fb7d1ff3cc94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535632695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.3535632695
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.3960222772
Short name T467
Test name
Test status
Simulation time 33686834 ps
CPU time 0.61 seconds
Started Jul 05 05:53:02 PM PDT 24
Finished Jul 05 05:53:03 PM PDT 24
Peak memory 197060 kb
Host smart-c86c5be1-c63e-475c-bb25-d5bd62e5e40c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960222772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.3960222772
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.1082070198
Short name T384
Test name
Test status
Simulation time 2997968673 ps
CPU time 0.98 seconds
Started Jul 05 05:52:28 PM PDT 24
Finished Jul 05 05:52:30 PM PDT 24
Peak memory 198216 kb
Host smart-682491fe-6935-442d-9d09-373e200b38b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082070198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.1082070198
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.874529977
Short name T636
Test name
Test status
Simulation time 59644991 ps
CPU time 0.72 seconds
Started Jul 05 05:52:21 PM PDT 24
Finished Jul 05 05:52:23 PM PDT 24
Peak memory 197108 kb
Host smart-4493b7fc-4841-435c-8e13-2e603021d2dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874529977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.874529977
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.335789094
Short name T208
Test name
Test status
Simulation time 108446977 ps
CPU time 0.63 seconds
Started Jul 05 05:52:34 PM PDT 24
Finished Jul 05 05:52:35 PM PDT 24
Peak memory 198172 kb
Host smart-41b4c83f-19c9-4023-a9be-0456bc151606
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335789094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.335789094
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.3094767101
Short name T818
Test name
Test status
Simulation time 42290386 ps
CPU time 0.72 seconds
Started Jul 05 05:52:33 PM PDT 24
Finished Jul 05 05:52:34 PM PDT 24
Peak memory 201116 kb
Host smart-74d14608-5f4e-4781-89fc-6d917dd12541
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094767101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.3094767101
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.3883157890
Short name T882
Test name
Test status
Simulation time 182149677 ps
CPU time 1.07 seconds
Started Jul 05 05:52:29 PM PDT 24
Finished Jul 05 05:52:31 PM PDT 24
Peak memory 199400 kb
Host smart-e1264be5-2ac6-4d7e-8a65-68e82f7d390c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883157890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_w
akeup_race.3883157890
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.1171468258
Short name T867
Test name
Test status
Simulation time 41522527 ps
CPU time 0.8 seconds
Started Jul 05 05:52:18 PM PDT 24
Finished Jul 05 05:52:20 PM PDT 24
Peak memory 198932 kb
Host smart-146202a7-9005-47ef-b3b9-cbfb20f29ae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171468258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.1171468258
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.592633175
Short name T255
Test name
Test status
Simulation time 94223787 ps
CPU time 1.06 seconds
Started Jul 05 05:52:29 PM PDT 24
Finished Jul 05 05:52:31 PM PDT 24
Peak memory 209284 kb
Host smart-ce58f893-271d-4c55-9abb-9f632a586ddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592633175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.592633175
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.703651436
Short name T744
Test name
Test status
Simulation time 122663639 ps
CPU time 0.9 seconds
Started Jul 05 05:52:25 PM PDT 24
Finished Jul 05 05:52:28 PM PDT 24
Peak memory 199636 kb
Host smart-b935d9dc-d360-4476-aa27-79a8922881f1
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703651436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_c
m_ctrl_config_regwen.703651436
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3553547893
Short name T296
Test name
Test status
Simulation time 1259517594 ps
CPU time 2.13 seconds
Started Jul 05 05:52:42 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 200880 kb
Host smart-d9d3ad1a-25fa-49a9-8044-95ac7ed27380
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553547893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3553547893
Directory /workspace/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.464736570
Short name T7
Test name
Test status
Simulation time 842554708 ps
CPU time 2.44 seconds
Started Jul 05 05:52:26 PM PDT 24
Finished Jul 05 05:52:29 PM PDT 24
Peak memory 200660 kb
Host smart-11cb5f86-a4aa-4e94-bb9d-80f3687a2423
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464736570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.464736570
Directory /workspace/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.827042966
Short name T769
Test name
Test status
Simulation time 53862973 ps
CPU time 0.91 seconds
Started Jul 05 05:53:05 PM PDT 24
Finished Jul 05 05:53:08 PM PDT 24
Peak memory 199416 kb
Host smart-dd834c9d-ff03-4a24-bdc2-73283d520406
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827042966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_
mubi.827042966
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.1000985777
Short name T32
Test name
Test status
Simulation time 54409744 ps
CPU time 0.64 seconds
Started Jul 05 05:52:27 PM PDT 24
Finished Jul 05 05:52:29 PM PDT 24
Peak memory 198196 kb
Host smart-1844013b-b6d5-4b6b-a85f-34ddfe41932a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000985777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.1000985777
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all.2221720844
Short name T443
Test name
Test status
Simulation time 1659906147 ps
CPU time 5.09 seconds
Started Jul 05 05:52:20 PM PDT 24
Finished Jul 05 05:52:26 PM PDT 24
Peak memory 200928 kb
Host smart-5a2b283a-760f-4192-9da6-09f22ef2b583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221720844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.2221720844
Directory /workspace/39.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all_with_rand_reset.3839607858
Short name T916
Test name
Test status
Simulation time 12292887958 ps
CPU time 27.12 seconds
Started Jul 05 05:52:27 PM PDT 24
Finished Jul 05 05:52:55 PM PDT 24
Peak memory 201128 kb
Host smart-67322c82-3df5-46aa-a513-322af5edc856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839607858 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all_with_rand_reset.3839607858
Directory /workspace/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup.1325669593
Short name T739
Test name
Test status
Simulation time 183228901 ps
CPU time 0.78 seconds
Started Jul 05 05:52:25 PM PDT 24
Finished Jul 05 05:52:27 PM PDT 24
Peak memory 198196 kb
Host smart-f413a6e7-985c-4745-914e-e6251548ae1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325669593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.1325669593
Directory /workspace/39.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup_reset.1674223010
Short name T927
Test name
Test status
Simulation time 301687606 ps
CPU time 1.4 seconds
Started Jul 05 05:52:26 PM PDT 24
Finished Jul 05 05:52:28 PM PDT 24
Peak memory 200748 kb
Host smart-9dc826ea-f726-4b3d-9b17-69caddab8b0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674223010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.1674223010
Directory /workspace/39.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.2623060257
Short name T866
Test name
Test status
Simulation time 67872618 ps
CPU time 0.69 seconds
Started Jul 05 05:50:55 PM PDT 24
Finished Jul 05 05:50:57 PM PDT 24
Peak memory 198408 kb
Host smart-0c85cfb4-d054-459d-9bae-200aa29d07c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623060257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.2623060257
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.2933724713
Short name T303
Test name
Test status
Simulation time 62967894 ps
CPU time 0.76 seconds
Started Jul 05 05:50:44 PM PDT 24
Finished Jul 05 05:50:45 PM PDT 24
Peak memory 198520 kb
Host smart-f5d4c61b-7d96-44f9-9275-17ff5838ec3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933724713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.2933724713
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.3761767386
Short name T588
Test name
Test status
Simulation time 38730281 ps
CPU time 0.6 seconds
Started Jul 05 05:50:53 PM PDT 24
Finished Jul 05 05:50:56 PM PDT 24
Peak memory 197800 kb
Host smart-0d4372f1-acd4-4b47-a64c-18a0e5f6181c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761767386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.3761767386
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.1159230122
Short name T439
Test name
Test status
Simulation time 164002189 ps
CPU time 1.01 seconds
Started Jul 05 05:50:50 PM PDT 24
Finished Jul 05 05:50:53 PM PDT 24
Peak memory 197860 kb
Host smart-3362939b-c0e3-485d-8e3d-48c99c5ffb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159230122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.1159230122
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.3365497787
Short name T800
Test name
Test status
Simulation time 61106903 ps
CPU time 0.67 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:01 PM PDT 24
Peak memory 197816 kb
Host smart-0da50f6d-5733-40b4-9140-64f3264a5f9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365497787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.3365497787
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.767809997
Short name T849
Test name
Test status
Simulation time 45699150 ps
CPU time 0.6 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 197864 kb
Host smart-d3311e6b-5beb-4484-bcf2-a26b9789ead0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767809997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.767809997
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.1540352769
Short name T669
Test name
Test status
Simulation time 44125958 ps
CPU time 0.71 seconds
Started Jul 05 05:50:46 PM PDT 24
Finished Jul 05 05:50:48 PM PDT 24
Peak memory 201068 kb
Host smart-1b4fa9ea-d130-4e1a-953b-73d400214200
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540352769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.1540352769
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.1800194877
Short name T509
Test name
Test status
Simulation time 81936541 ps
CPU time 0.72 seconds
Started Jul 05 05:50:47 PM PDT 24
Finished Jul 05 05:50:49 PM PDT 24
Peak memory 198888 kb
Host smart-9122b463-9b40-4f4b-b613-553096e7f406
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800194877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa
keup_race.1800194877
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.4190676692
Short name T934
Test name
Test status
Simulation time 77983274 ps
CPU time 1.02 seconds
Started Jul 05 05:50:48 PM PDT 24
Finished Jul 05 05:50:50 PM PDT 24
Peak memory 199496 kb
Host smart-450ac03b-3293-4a98-b3fd-59769b449e27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190676692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.4190676692
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.1435610512
Short name T94
Test name
Test status
Simulation time 113160144 ps
CPU time 0.96 seconds
Started Jul 05 05:50:49 PM PDT 24
Finished Jul 05 05:50:52 PM PDT 24
Peak memory 209304 kb
Host smart-98a6d971-09fb-48d3-8381-09cac50872ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435610512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1435610512
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.405047179
Short name T27
Test name
Test status
Simulation time 564969266 ps
CPU time 1.09 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:04 PM PDT 24
Peak memory 216412 kb
Host smart-b8793684-16c4-45ac-8576-9c46e8789ea6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405047179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.405047179
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.1878240716
Short name T200
Test name
Test status
Simulation time 621540579 ps
CPU time 0.93 seconds
Started Jul 05 05:50:56 PM PDT 24
Finished Jul 05 05:50:58 PM PDT 24
Peak memory 199680 kb
Host smart-7cf20325-10df-4ead-b292-290722d0b799
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878240716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_c
m_ctrl_config_regwen.1878240716
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2303068528
Short name T248
Test name
Test status
Simulation time 1331646129 ps
CPU time 2.24 seconds
Started Jul 05 05:50:52 PM PDT 24
Finished Jul 05 05:50:57 PM PDT 24
Peak memory 200904 kb
Host smart-183221e2-f55f-48ad-bf63-4e837857a026
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303068528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2303068528
Directory /workspace/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3047565204
Short name T792
Test name
Test status
Simulation time 882710090 ps
CPU time 3.58 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:50:59 PM PDT 24
Peak memory 200924 kb
Host smart-a8598494-2bf0-4acc-997d-14526df92a49
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047565204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3047565204
Directory /workspace/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.184051855
Short name T456
Test name
Test status
Simulation time 109414053 ps
CPU time 0.85 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:50:56 PM PDT 24
Peak memory 199148 kb
Host smart-eef14c9d-0125-4bb7-9a62-c7882bc3d55e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184051855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.184051855
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.2161694151
Short name T31
Test name
Test status
Simulation time 32167848 ps
CPU time 0.72 seconds
Started Jul 05 05:50:51 PM PDT 24
Finished Jul 05 05:50:54 PM PDT 24
Peak memory 199152 kb
Host smart-c2b98fd5-4a49-4d47-ba64-9230f9e49690
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161694151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.2161694151
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all.476101979
Short name T568
Test name
Test status
Simulation time 741249801 ps
CPU time 3.13 seconds
Started Jul 05 05:50:47 PM PDT 24
Finished Jul 05 05:50:51 PM PDT 24
Peak memory 200964 kb
Host smart-52fcfeb8-74cc-46e7-869b-d2ef23e81414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476101979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.476101979
Directory /workspace/4.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all_with_rand_reset.4177656549
Short name T79
Test name
Test status
Simulation time 5073214271 ps
CPU time 16.05 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:20 PM PDT 24
Peak memory 201092 kb
Host smart-8e723b8d-c872-45ee-a06c-9bd2d5514471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177656549 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all_with_rand_reset.4177656549
Directory /workspace/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup.1538228145
Short name T974
Test name
Test status
Simulation time 286198912 ps
CPU time 0.79 seconds
Started Jul 05 05:50:51 PM PDT 24
Finished Jul 05 05:50:54 PM PDT 24
Peak memory 198260 kb
Host smart-89a919ca-5a7b-4ac3-8ceb-5dfa46b2c4ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538228145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.1538228145
Directory /workspace/4.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.1703572510
Short name T373
Test name
Test status
Simulation time 393291809 ps
CPU time 1.25 seconds
Started Jul 05 05:50:56 PM PDT 24
Finished Jul 05 05:50:59 PM PDT 24
Peak memory 200728 kb
Host smart-f2173ef4-b9dd-4d11-a160-0e6c650a0057
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703572510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.1703572510
Directory /workspace/4.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.1957671944
Short name T696
Test name
Test status
Simulation time 71525772 ps
CPU time 0.69 seconds
Started Jul 05 05:52:37 PM PDT 24
Finished Jul 05 05:52:39 PM PDT 24
Peak memory 198456 kb
Host smart-6416fbbe-89f9-4e6f-bb39-0ccabb6510ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957671944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1957671944
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.2842578098
Short name T104
Test name
Test status
Simulation time 56004343 ps
CPU time 0.8 seconds
Started Jul 05 05:52:35 PM PDT 24
Finished Jul 05 05:52:36 PM PDT 24
Peak memory 198936 kb
Host smart-8126d534-34c7-4b96-a65e-cb329ee464a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842578098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.2842578098
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.2959176654
Short name T838
Test name
Test status
Simulation time 49256184 ps
CPU time 0.63 seconds
Started Jul 05 05:52:30 PM PDT 24
Finished Jul 05 05:52:31 PM PDT 24
Peak memory 197696 kb
Host smart-a0e77d61-db59-40a7-90be-8235a84c863a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959176654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.2959176654
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.2170306419
Short name T352
Test name
Test status
Simulation time 604277174 ps
CPU time 0.99 seconds
Started Jul 05 05:52:30 PM PDT 24
Finished Jul 05 05:52:31 PM PDT 24
Peak memory 197860 kb
Host smart-e98a7bce-6221-49cb-821e-1dfa62d6c9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170306419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.2170306419
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.3230231675
Short name T946
Test name
Test status
Simulation time 37357289 ps
CPU time 0.61 seconds
Started Jul 05 05:53:04 PM PDT 24
Finished Jul 05 05:53:06 PM PDT 24
Peak memory 197852 kb
Host smart-bbf1a0e7-8a74-4f8b-b8fd-457cdc7ef11a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230231675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.3230231675
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.1659372657
Short name T108
Test name
Test status
Simulation time 53790076 ps
CPU time 0.62 seconds
Started Jul 05 05:52:32 PM PDT 24
Finished Jul 05 05:52:33 PM PDT 24
Peak memory 198164 kb
Host smart-e623197f-c08d-4b71-b19c-312cbc83b4e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659372657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.1659372657
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.1639548026
Short name T46
Test name
Test status
Simulation time 70716341 ps
CPU time 0.64 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:48 PM PDT 24
Peak memory 201104 kb
Host smart-9019cb1d-aa69-4ff1-9050-2a53a57dc317
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639548026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.1639548026
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.3023808665
Short name T84
Test name
Test status
Simulation time 406667262 ps
CPU time 1.08 seconds
Started Jul 05 05:52:50 PM PDT 24
Finished Jul 05 05:52:52 PM PDT 24
Peak memory 199608 kb
Host smart-07bf7e9d-faa6-42e8-957f-34311cd0d4b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023808665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_w
akeup_race.3023808665
Directory /workspace/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.3500849688
Short name T231
Test name
Test status
Simulation time 49485021 ps
CPU time 0.7 seconds
Started Jul 05 05:52:33 PM PDT 24
Finished Jul 05 05:52:34 PM PDT 24
Peak memory 198088 kb
Host smart-782a1aef-06c9-458e-aba1-07785c5cbaa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500849688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.3500849688
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.704579661
Short name T237
Test name
Test status
Simulation time 244471742 ps
CPU time 0.75 seconds
Started Jul 05 05:52:43 PM PDT 24
Finished Jul 05 05:52:45 PM PDT 24
Peak memory 209248 kb
Host smart-37a31139-1c67-46b8-b76f-46f950b4aade
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704579661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.704579661
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.3433517608
Short name T793
Test name
Test status
Simulation time 65098824 ps
CPU time 0.77 seconds
Started Jul 05 05:52:28 PM PDT 24
Finished Jul 05 05:52:30 PM PDT 24
Peak memory 198924 kb
Host smart-928b3b35-e1a0-4071-8725-7b9295f7982f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433517608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_
cm_ctrl_config_regwen.3433517608
Directory /workspace/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2612066094
Short name T848
Test name
Test status
Simulation time 946239143 ps
CPU time 2.14 seconds
Started Jul 05 05:52:27 PM PDT 24
Finished Jul 05 05:52:31 PM PDT 24
Peak memory 200912 kb
Host smart-3fc6ed9f-d47e-48ef-b26c-b6140447eb1d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612066094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2612066094
Directory /workspace/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1837011247
Short name T513
Test name
Test status
Simulation time 52847143 ps
CPU time 0.91 seconds
Started Jul 05 05:52:47 PM PDT 24
Finished Jul 05 05:52:51 PM PDT 24
Peak memory 199308 kb
Host smart-334d4381-8ec1-4dbc-8d3e-d01c7dff9dce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837011247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1837011247
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.3097269367
Short name T114
Test name
Test status
Simulation time 65662391 ps
CPU time 0.62 seconds
Started Jul 05 05:52:28 PM PDT 24
Finished Jul 05 05:52:30 PM PDT 24
Peak memory 198296 kb
Host smart-a29719f9-bcb1-4390-8b77-17ff12a8c7e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097269367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.3097269367
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all.181554482
Short name T918
Test name
Test status
Simulation time 3999981321 ps
CPU time 4.86 seconds
Started Jul 05 05:52:39 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 201032 kb
Host smart-69726bab-ce26-40b5-b3af-01331c54251e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181554482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.181554482
Directory /workspace/40.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all_with_rand_reset.3835164410
Short name T65
Test name
Test status
Simulation time 5779655397 ps
CPU time 19.21 seconds
Started Jul 05 05:52:27 PM PDT 24
Finished Jul 05 05:52:47 PM PDT 24
Peak memory 201108 kb
Host smart-9353c7d5-c7ad-4a79-b60b-d93a9ff93e61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835164410 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all_with_rand_reset.3835164410
Directory /workspace/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup.31501616
Short name T714
Test name
Test status
Simulation time 44846685 ps
CPU time 0.71 seconds
Started Jul 05 05:52:27 PM PDT 24
Finished Jul 05 05:52:29 PM PDT 24
Peak memory 198908 kb
Host smart-8a3058cb-1104-4a9c-afbd-6f4365d0481c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31501616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.31501616
Directory /workspace/40.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup_reset.2079270332
Short name T712
Test name
Test status
Simulation time 59900888 ps
CPU time 0.67 seconds
Started Jul 05 05:52:28 PM PDT 24
Finished Jul 05 05:52:30 PM PDT 24
Peak memory 198848 kb
Host smart-332ee6c4-430c-431e-95d8-1921a06b56e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079270332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.2079270332
Directory /workspace/40.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.641445366
Short name T790
Test name
Test status
Simulation time 52539812 ps
CPU time 0.74 seconds
Started Jul 05 05:52:28 PM PDT 24
Finished Jul 05 05:52:30 PM PDT 24
Peak memory 198608 kb
Host smart-29cac84b-2c85-4fac-a683-f7ae74019c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641445366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.641445366
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.788039482
Short name T50
Test name
Test status
Simulation time 69689418 ps
CPU time 0.68 seconds
Started Jul 05 05:52:37 PM PDT 24
Finished Jul 05 05:52:38 PM PDT 24
Peak memory 198584 kb
Host smart-1390835f-3bab-402c-a2c3-768cbb72d493
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788039482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disa
ble_rom_integrity_check.788039482
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.1659389279
Short name T980
Test name
Test status
Simulation time 32730716 ps
CPU time 0.61 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:47 PM PDT 24
Peak memory 197768 kb
Host smart-be644546-3fe9-426e-b753-f29abebc5aae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659389279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.1659389279
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.285623943
Short name T802
Test name
Test status
Simulation time 627273472 ps
CPU time 0.96 seconds
Started Jul 05 05:52:56 PM PDT 24
Finished Jul 05 05:52:58 PM PDT 24
Peak memory 197840 kb
Host smart-851c4678-ed3f-4d7f-82e4-499e58b23f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285623943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.285623943
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.440067970
Short name T996
Test name
Test status
Simulation time 33756868 ps
CPU time 0.6 seconds
Started Jul 05 05:52:53 PM PDT 24
Finished Jul 05 05:52:54 PM PDT 24
Peak memory 197180 kb
Host smart-1d33e8cb-b091-45f9-a8b3-d117b6ab6af2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440067970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.440067970
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.2754508938
Short name T351
Test name
Test status
Simulation time 51571377 ps
CPU time 0.6 seconds
Started Jul 05 05:52:42 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 197796 kb
Host smart-75a12451-cb21-4fb2-9328-af24bca50f4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754508938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.2754508938
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.1879444774
Short name T847
Test name
Test status
Simulation time 43848938 ps
CPU time 0.7 seconds
Started Jul 05 05:52:38 PM PDT 24
Finished Jul 05 05:52:39 PM PDT 24
Peak memory 201112 kb
Host smart-6d12c2db-ed2e-4135-8486-2ac10ada1e1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879444774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.1879444774
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.3812983565
Short name T905
Test name
Test status
Simulation time 257261446 ps
CPU time 1.03 seconds
Started Jul 05 05:52:37 PM PDT 24
Finished Jul 05 05:52:38 PM PDT 24
Peak memory 199284 kb
Host smart-1fc698ca-79de-4985-a64b-9a2d82f6f7f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812983565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_w
akeup_race.3812983565
Directory /workspace/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.2794186956
Short name T854
Test name
Test status
Simulation time 75623644 ps
CPU time 0.69 seconds
Started Jul 05 05:52:38 PM PDT 24
Finished Jul 05 05:52:39 PM PDT 24
Peak memory 198112 kb
Host smart-8835fcdd-f058-4bf2-ae49-54e82bb3b9c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794186956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2794186956
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1923087248
Short name T234
Test name
Test status
Simulation time 389333725 ps
CPU time 0.81 seconds
Started Jul 05 05:52:34 PM PDT 24
Finished Jul 05 05:52:36 PM PDT 24
Peak memory 209320 kb
Host smart-658df1df-0065-4f81-8534-4ae79f56f114
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923087248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1923087248
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.434261159
Short name T483
Test name
Test status
Simulation time 127655070 ps
CPU time 0.78 seconds
Started Jul 05 05:52:32 PM PDT 24
Finished Jul 05 05:52:34 PM PDT 24
Peak memory 198404 kb
Host smart-5b83901c-9e27-42c8-8139-b73efa853d10
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434261159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_c
m_ctrl_config_regwen.434261159
Directory /workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.634558523
Short name T489
Test name
Test status
Simulation time 924179673 ps
CPU time 2.55 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:50 PM PDT 24
Peak memory 200932 kb
Host smart-8abe493a-065a-4909-950d-3069e8060b9d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634558523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.634558523
Directory /workspace/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3742386418
Short name T211
Test name
Test status
Simulation time 864605233 ps
CPU time 2.81 seconds
Started Jul 05 05:52:37 PM PDT 24
Finished Jul 05 05:52:40 PM PDT 24
Peak memory 200780 kb
Host smart-becd4165-cab8-4bc9-bc5d-58afe08b1fb4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742386418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3742386418
Directory /workspace/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.863443581
Short name T442
Test name
Test status
Simulation time 145936304 ps
CPU time 0.89 seconds
Started Jul 05 05:53:04 PM PDT 24
Finished Jul 05 05:53:08 PM PDT 24
Peak memory 199144 kb
Host smart-855964ea-c5cc-4960-86ae-c8ce61f1b1c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863443581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_
mubi.863443581
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.1251008837
Short name T559
Test name
Test status
Simulation time 31254149 ps
CPU time 0.67 seconds
Started Jul 05 05:52:27 PM PDT 24
Finished Jul 05 05:52:29 PM PDT 24
Peak memory 198320 kb
Host smart-f31b03fa-0283-4574-9dcb-cc0a5aa808f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251008837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.1251008837
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all.975551773
Short name T121
Test name
Test status
Simulation time 1496611154 ps
CPU time 5.99 seconds
Started Jul 05 05:52:30 PM PDT 24
Finished Jul 05 05:52:37 PM PDT 24
Peak memory 200912 kb
Host smart-349944e3-91d2-4aaa-af1b-0d38b69276e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975551773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.975551773
Directory /workspace/41.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all_with_rand_reset.3723887504
Short name T417
Test name
Test status
Simulation time 10269818364 ps
CPU time 14.85 seconds
Started Jul 05 05:52:42 PM PDT 24
Finished Jul 05 05:52:57 PM PDT 24
Peak memory 201108 kb
Host smart-9a8dcc5e-d484-4e70-9fd6-b60d98807436
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723887504 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all_with_rand_reset.3723887504
Directory /workspace/41.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup.3110275737
Short name T642
Test name
Test status
Simulation time 182744900 ps
CPU time 0.72 seconds
Started Jul 05 05:52:52 PM PDT 24
Finished Jul 05 05:52:53 PM PDT 24
Peak memory 198152 kb
Host smart-bfd83b76-3225-4c6e-a431-d1d20c1a33d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110275737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.3110275737
Directory /workspace/41.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup_reset.2328342084
Short name T740
Test name
Test status
Simulation time 73385079 ps
CPU time 0.79 seconds
Started Jul 05 05:52:32 PM PDT 24
Finished Jul 05 05:52:33 PM PDT 24
Peak memory 199064 kb
Host smart-6a201463-79ce-40a2-af0a-f423d482b559
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328342084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.2328342084
Directory /workspace/41.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.3796704750
Short name T367
Test name
Test status
Simulation time 51405686 ps
CPU time 0.84 seconds
Started Jul 05 05:52:35 PM PDT 24
Finished Jul 05 05:52:36 PM PDT 24
Peak memory 199864 kb
Host smart-30b84d59-d1f2-41aa-af88-d4c8e65e742f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796704750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.3796704750
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.4214343786
Short name T727
Test name
Test status
Simulation time 69173807 ps
CPU time 0.71 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:47 PM PDT 24
Peak memory 198212 kb
Host smart-fbf04be8-d706-4c80-b43b-86cc41e268be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214343786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.4214343786
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.3375661910
Short name T931
Test name
Test status
Simulation time 30932236 ps
CPU time 0.63 seconds
Started Jul 05 05:52:53 PM PDT 24
Finished Jul 05 05:52:54 PM PDT 24
Peak memory 197824 kb
Host smart-b260cc2b-3ec4-4622-92e6-8f63229ab69f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375661910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.3375661910
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.3195778431
Short name T481
Test name
Test status
Simulation time 2146746333 ps
CPU time 0.89 seconds
Started Jul 05 05:52:49 PM PDT 24
Finished Jul 05 05:52:52 PM PDT 24
Peak memory 197868 kb
Host smart-a6339f05-333a-4820-9464-c0b635423ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195778431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.3195778431
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.1184979679
Short name T343
Test name
Test status
Simulation time 34064842 ps
CPU time 0.65 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:46 PM PDT 24
Peak memory 197880 kb
Host smart-e7e73f0f-3c4a-40b6-a330-46d0d372bda4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184979679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.1184979679
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.771700364
Short name T426
Test name
Test status
Simulation time 54279111 ps
CPU time 0.61 seconds
Started Jul 05 05:52:55 PM PDT 24
Finished Jul 05 05:52:57 PM PDT 24
Peak memory 197848 kb
Host smart-4326982b-a67c-4dd8-bb69-51379208c3a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771700364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.771700364
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.388096763
Short name T906
Test name
Test status
Simulation time 44569785 ps
CPU time 0.74 seconds
Started Jul 05 05:52:43 PM PDT 24
Finished Jul 05 05:52:45 PM PDT 24
Peak memory 201148 kb
Host smart-599461d3-39d6-4fa1-a780-1d11bb9b1bd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388096763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invali
d.388096763
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.657888403
Short name T597
Test name
Test status
Simulation time 246070991 ps
CPU time 1.22 seconds
Started Jul 05 05:52:27 PM PDT 24
Finished Jul 05 05:52:30 PM PDT 24
Peak memory 199388 kb
Host smart-28f31cfb-f0b9-4a0f-b151-27606e895e48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657888403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wa
keup_race.657888403
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.3864943136
Short name T803
Test name
Test status
Simulation time 58007387 ps
CPU time 0.76 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:46 PM PDT 24
Peak memory 198200 kb
Host smart-603e2b96-80f5-491a-bf71-5c04b599b0cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864943136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.3864943136
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.2777852081
Short name T620
Test name
Test status
Simulation time 123460824 ps
CPU time 0.85 seconds
Started Jul 05 05:52:30 PM PDT 24
Finished Jul 05 05:52:32 PM PDT 24
Peak memory 209264 kb
Host smart-e18c1b54-b986-4f0f-b188-8366886eddae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777852081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.2777852081
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.2369154894
Short name T155
Test name
Test status
Simulation time 165437178 ps
CPU time 0.66 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 198524 kb
Host smart-0db3ebcf-75fb-4b84-8ac0-ff0319341bee
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369154894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_
cm_ctrl_config_regwen.2369154894
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.136698985
Short name T644
Test name
Test status
Simulation time 1587699993 ps
CPU time 1.97 seconds
Started Jul 05 05:52:33 PM PDT 24
Finished Jul 05 05:52:35 PM PDT 24
Peak memory 200896 kb
Host smart-284a330b-63c0-4209-add7-2aec9d0495ed
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136698985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.136698985
Directory /workspace/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1630593794
Short name T812
Test name
Test status
Simulation time 857191944 ps
CPU time 3.15 seconds
Started Jul 05 05:52:26 PM PDT 24
Finished Jul 05 05:52:30 PM PDT 24
Peak memory 200668 kb
Host smart-87093f99-5d93-4538-b326-eba15ee2d758
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630593794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1630593794
Directory /workspace/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.3953802324
Short name T510
Test name
Test status
Simulation time 244818233 ps
CPU time 0.86 seconds
Started Jul 05 05:52:47 PM PDT 24
Finished Jul 05 05:52:51 PM PDT 24
Peak memory 198956 kb
Host smart-9c7f30bb-2c12-4e94-836c-0b5f29cbd71c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953802324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3953802324
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.1493688199
Short name T743
Test name
Test status
Simulation time 27735605 ps
CPU time 0.67 seconds
Started Jul 05 05:52:24 PM PDT 24
Finished Jul 05 05:52:26 PM PDT 24
Peak memory 199152 kb
Host smart-e0229184-3993-441a-bc68-aa0099d75ddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493688199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.1493688199
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all.3775758989
Short name T239
Test name
Test status
Simulation time 1597840734 ps
CPU time 2.39 seconds
Started Jul 05 05:52:41 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 200924 kb
Host smart-f6605199-e246-4ecb-8d99-a59287eec7d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775758989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.3775758989
Directory /workspace/42.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all_with_rand_reset.2452671721
Short name T77
Test name
Test status
Simulation time 11143973020 ps
CPU time 21.23 seconds
Started Jul 05 05:52:39 PM PDT 24
Finished Jul 05 05:53:00 PM PDT 24
Peak memory 201136 kb
Host smart-7a28eaaf-7e52-45ab-82ff-9bf2c08ba6d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452671721 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all_with_rand_reset.2452671721
Directory /workspace/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup.2450214008
Short name T571
Test name
Test status
Simulation time 84230443 ps
CPU time 0.75 seconds
Started Jul 05 05:52:36 PM PDT 24
Finished Jul 05 05:52:38 PM PDT 24
Peak memory 198060 kb
Host smart-897b6d02-4e1e-43c3-9d4f-b9feb27e288f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450214008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.2450214008
Directory /workspace/42.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup_reset.1002075491
Short name T835
Test name
Test status
Simulation time 177947320 ps
CPU time 0.87 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:48 PM PDT 24
Peak memory 199620 kb
Host smart-51c037c2-4619-4e75-869b-72e137a70702
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002075491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.1002075491
Directory /workspace/42.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.345660758
Short name T462
Test name
Test status
Simulation time 45912819 ps
CPU time 0.97 seconds
Started Jul 05 05:52:32 PM PDT 24
Finished Jul 05 05:52:33 PM PDT 24
Peak memory 199996 kb
Host smart-e0e0902e-4114-4166-871a-0fee186ac13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345660758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.345660758
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.1547744004
Short name T506
Test name
Test status
Simulation time 64411820 ps
CPU time 0.7 seconds
Started Jul 05 05:52:31 PM PDT 24
Finished Jul 05 05:52:37 PM PDT 24
Peak memory 198872 kb
Host smart-ac590c7f-709c-4384-a362-00449041c550
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547744004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.1547744004
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.1463439555
Short name T299
Test name
Test status
Simulation time 38106431 ps
CPU time 0.61 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:48 PM PDT 24
Peak memory 197764 kb
Host smart-a814b872-bf9c-4f47-82f2-e0148746439e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463439555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.1463439555
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.958567542
Short name T168
Test name
Test status
Simulation time 610097057 ps
CPU time 1.16 seconds
Started Jul 05 05:52:43 PM PDT 24
Finished Jul 05 05:52:45 PM PDT 24
Peak memory 197872 kb
Host smart-ae750352-76da-4961-958e-b83bbe541618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958567542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.958567542
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.3862712642
Short name T945
Test name
Test status
Simulation time 57208007 ps
CPU time 0.6 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:46 PM PDT 24
Peak memory 197824 kb
Host smart-93a1d16e-6689-456e-a4f8-77cedf5f1ae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862712642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.3862712642
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.204643150
Short name T549
Test name
Test status
Simulation time 30578086 ps
CPU time 0.62 seconds
Started Jul 05 05:52:57 PM PDT 24
Finished Jul 05 05:52:58 PM PDT 24
Peak memory 197856 kb
Host smart-b885ff3e-d9b2-4695-958c-1b97e161cdec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204643150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.204643150
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.773962929
Short name T457
Test name
Test status
Simulation time 43831332 ps
CPU time 0.7 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 200948 kb
Host smart-5fc01056-fff4-422c-8205-f9d2f4a488dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773962929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invali
d.773962929
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.461028194
Short name T498
Test name
Test status
Simulation time 126623801 ps
CPU time 0.75 seconds
Started Jul 05 05:52:49 PM PDT 24
Finished Jul 05 05:52:52 PM PDT 24
Peak memory 198896 kb
Host smart-72ea57ad-1fd2-42bf-9b10-12f16b2b04fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461028194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wa
keup_race.461028194
Directory /workspace/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.918347939
Short name T8
Test name
Test status
Simulation time 63453409 ps
CPU time 0.65 seconds
Started Jul 05 05:52:55 PM PDT 24
Finished Jul 05 05:52:56 PM PDT 24
Peak memory 199112 kb
Host smart-b19416e1-724e-4059-b464-a0b1ea0defac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918347939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.918347939
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.1625348394
Short name T257
Test name
Test status
Simulation time 162269231 ps
CPU time 0.85 seconds
Started Jul 05 05:52:41 PM PDT 24
Finished Jul 05 05:52:43 PM PDT 24
Peak memory 209320 kb
Host smart-2026a9eb-700b-41ac-94a3-eec22dc818cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625348394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.1625348394
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.2290370317
Short name T156
Test name
Test status
Simulation time 67167131 ps
CPU time 0.68 seconds
Started Jul 05 05:52:56 PM PDT 24
Finished Jul 05 05:52:57 PM PDT 24
Peak memory 198380 kb
Host smart-0458a1d2-95b0-43bc-90e2-52f24083edee
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290370317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_
cm_ctrl_config_regwen.2290370317
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3086710930
Short name T856
Test name
Test status
Simulation time 788832345 ps
CPU time 2.78 seconds
Started Jul 05 05:52:36 PM PDT 24
Finished Jul 05 05:52:39 PM PDT 24
Peak memory 200936 kb
Host smart-5508b7b8-732b-4e87-8dd2-acb1c3cf95e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086710930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3086710930
Directory /workspace/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.753841684
Short name T6
Test name
Test status
Simulation time 831821593 ps
CPU time 3.39 seconds
Started Jul 05 05:52:35 PM PDT 24
Finished Jul 05 05:52:39 PM PDT 24
Peak memory 200756 kb
Host smart-fa10c8c2-65ec-41da-8eb5-d94c67593288
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753841684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.753841684
Directory /workspace/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1661222677
Short name T805
Test name
Test status
Simulation time 107954431 ps
CPU time 0.81 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 199424 kb
Host smart-ae81d2a0-3fbc-4ea7-9f1b-84dbe6dfecf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661222677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1661222677
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.2695916022
Short name T476
Test name
Test status
Simulation time 94569518 ps
CPU time 0.66 seconds
Started Jul 05 05:52:58 PM PDT 24
Finished Jul 05 05:53:00 PM PDT 24
Peak memory 198276 kb
Host smart-4fe64271-8026-4feb-b04a-66da375134ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695916022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.2695916022
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all.2318780707
Short name T491
Test name
Test status
Simulation time 1440312852 ps
CPU time 2.22 seconds
Started Jul 05 05:52:43 PM PDT 24
Finished Jul 05 05:52:47 PM PDT 24
Peak memory 200924 kb
Host smart-3697e571-e709-461d-b03d-6d06c26141fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318780707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.2318780707
Directory /workspace/43.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all_with_rand_reset.2000361643
Short name T89
Test name
Test status
Simulation time 4903889404 ps
CPU time 20 seconds
Started Jul 05 05:52:50 PM PDT 24
Finished Jul 05 05:53:11 PM PDT 24
Peak memory 201132 kb
Host smart-99963e59-7650-40f3-a53d-03d72833cd3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000361643 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all_with_rand_reset.2000361643
Directory /workspace/43.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup.946226486
Short name T371
Test name
Test status
Simulation time 48808076 ps
CPU time 0.78 seconds
Started Jul 05 05:52:42 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 198328 kb
Host smart-b42f8357-d20a-441f-afdf-ec1100b81fd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946226486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.946226486
Directory /workspace/43.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.405732325
Short name T204
Test name
Test status
Simulation time 182653695 ps
CPU time 0.82 seconds
Started Jul 05 05:52:43 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 199140 kb
Host smart-01b29301-cb88-40c5-87ad-bed3e2061fa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405732325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.405732325
Directory /workspace/43.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.3417743135
Short name T658
Test name
Test status
Simulation time 22859928 ps
CPU time 0.73 seconds
Started Jul 05 05:52:33 PM PDT 24
Finished Jul 05 05:52:34 PM PDT 24
Peak memory 198928 kb
Host smart-75a3411f-7140-41be-af7c-90adb6a57f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417743135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.3417743135
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.2671779238
Short name T249
Test name
Test status
Simulation time 53194220 ps
CPU time 0.82 seconds
Started Jul 05 05:52:47 PM PDT 24
Finished Jul 05 05:52:51 PM PDT 24
Peak memory 198912 kb
Host smart-9dc56377-adef-4e24-b9f1-7b691847fada
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671779238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.2671779238
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.2125582780
Short name T541
Test name
Test status
Simulation time 29706798 ps
CPU time 0.62 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:46 PM PDT 24
Peak memory 197744 kb
Host smart-3cf1f4ce-c037-456d-85b0-edea6f28ad12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125582780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.2125582780
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.2073386920
Short name T171
Test name
Test status
Simulation time 1168181553 ps
CPU time 0.94 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 197856 kb
Host smart-18045268-6bdf-4e64-8c9d-abe3961e85e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073386920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.2073386920
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.1015939306
Short name T397
Test name
Test status
Simulation time 39735084 ps
CPU time 0.61 seconds
Started Jul 05 05:53:04 PM PDT 24
Finished Jul 05 05:53:07 PM PDT 24
Peak memory 197840 kb
Host smart-89167388-4bdc-4281-993f-6d3d3901de2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015939306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.1015939306
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.1294521597
Short name T635
Test name
Test status
Simulation time 288002479 ps
CPU time 0.61 seconds
Started Jul 05 05:52:36 PM PDT 24
Finished Jul 05 05:52:37 PM PDT 24
Peak memory 198172 kb
Host smart-9442a3c1-855c-4782-a8fa-d49d8b494bf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294521597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.1294521597
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.1696766294
Short name T715
Test name
Test status
Simulation time 151257927 ps
CPU time 0.68 seconds
Started Jul 05 05:52:59 PM PDT 24
Finished Jul 05 05:53:00 PM PDT 24
Peak memory 201096 kb
Host smart-f3e5a5f9-31ae-4e6d-8d79-761efde29256
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696766294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.1696766294
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_wakeup_race.1775933077
Short name T253
Test name
Test status
Simulation time 239247849 ps
CPU time 0.94 seconds
Started Jul 05 05:52:40 PM PDT 24
Finished Jul 05 05:52:41 PM PDT 24
Peak memory 199424 kb
Host smart-0928ea36-f161-4af4-b38d-feabaaaf9c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775933077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_w
akeup_race.1775933077
Directory /workspace/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.1609396053
Short name T301
Test name
Test status
Simulation time 45271728 ps
CPU time 0.71 seconds
Started Jul 05 05:52:34 PM PDT 24
Finished Jul 05 05:52:35 PM PDT 24
Peak memory 198268 kb
Host smart-dc12279d-28f2-4a71-b6be-6d102db96ce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609396053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.1609396053
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.3913924116
Short name T245
Test name
Test status
Simulation time 105994806 ps
CPU time 0.88 seconds
Started Jul 05 05:52:38 PM PDT 24
Finished Jul 05 05:52:40 PM PDT 24
Peak memory 209324 kb
Host smart-a3694349-6984-4aa2-a05a-825ba2a40676
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913924116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.3913924116
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.1334394578
Short name T877
Test name
Test status
Simulation time 373534860 ps
CPU time 1.04 seconds
Started Jul 05 05:52:52 PM PDT 24
Finished Jul 05 05:52:54 PM PDT 24
Peak memory 199744 kb
Host smart-dd537dfd-3309-434b-b25f-6a2c7256403d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334394578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_
cm_ctrl_config_regwen.1334394578
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.5547099
Short name T998
Test name
Test status
Simulation time 926788972 ps
CPU time 1.9 seconds
Started Jul 05 05:52:42 PM PDT 24
Finished Jul 05 05:52:45 PM PDT 24
Peak memory 200948 kb
Host smart-5680522b-a587-46c2-9bf6-4db050333861
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5547099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.5547099
Directory /workspace/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2686809574
Short name T565
Test name
Test status
Simulation time 1279780783 ps
CPU time 1.85 seconds
Started Jul 05 05:52:43 PM PDT 24
Finished Jul 05 05:52:45 PM PDT 24
Peak memory 200816 kb
Host smart-87e39137-a9bd-4064-9e68-de9d71662553
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686809574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2686809574
Directory /workspace/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.736556987
Short name T959
Test name
Test status
Simulation time 64509218 ps
CPU time 0.85 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 199444 kb
Host smart-57bddb4a-00c4-4d2e-93c2-2a6193012844
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736556987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_
mubi.736556987
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.216903609
Short name T786
Test name
Test status
Simulation time 29208402 ps
CPU time 0.73 seconds
Started Jul 05 05:52:39 PM PDT 24
Finished Jul 05 05:52:40 PM PDT 24
Peak memory 199152 kb
Host smart-ff14e7a1-3e20-4824-ba01-cf58e87d47a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216903609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.216903609
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all.3377659274
Short name T850
Test name
Test status
Simulation time 333869839 ps
CPU time 1.51 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 200480 kb
Host smart-2698cafe-136f-46b7-b05c-afd791cffdd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377659274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.3377659274
Directory /workspace/44.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all_with_rand_reset.1883696449
Short name T120
Test name
Test status
Simulation time 8877432608 ps
CPU time 11.18 seconds
Started Jul 05 05:52:41 PM PDT 24
Finished Jul 05 05:52:52 PM PDT 24
Peak memory 201124 kb
Host smart-da1cabe2-6b26-4648-a285-c8574a6fc3ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883696449 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all_with_rand_reset.1883696449
Directory /workspace/44.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup.1127721022
Short name T280
Test name
Test status
Simulation time 83277008 ps
CPU time 0.84 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:46 PM PDT 24
Peak memory 198180 kb
Host smart-cbb2e965-65cd-4c63-b8c8-3e25a2541f9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127721022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.1127721022
Directory /workspace/44.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup_reset.602419525
Short name T705
Test name
Test status
Simulation time 214732105 ps
CPU time 1.2 seconds
Started Jul 05 05:52:58 PM PDT 24
Finished Jul 05 05:53:00 PM PDT 24
Peak memory 199788 kb
Host smart-0a4a4453-004a-4e24-b2a6-665427b80760
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602419525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.602419525
Directory /workspace/44.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.3743326830
Short name T976
Test name
Test status
Simulation time 122126881 ps
CPU time 0.89 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 199964 kb
Host smart-01370de6-dbaf-4120-b03c-aa392b4a3f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743326830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.3743326830
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.1434075480
Short name T534
Test name
Test status
Simulation time 39555931 ps
CPU time 0.6 seconds
Started Jul 05 05:52:43 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 197772 kb
Host smart-146f6b61-7ad3-4e15-a915-0cae50b00ac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434075480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.1434075480
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.1621534869
Short name T11
Test name
Test status
Simulation time 631620184 ps
CPU time 0.95 seconds
Started Jul 05 05:52:51 PM PDT 24
Finished Jul 05 05:52:53 PM PDT 24
Peak memory 197888 kb
Host smart-71a1c84e-845d-4f33-9fb5-af8453142ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621534869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.1621534869
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.2425473514
Short name T16
Test name
Test status
Simulation time 118076699 ps
CPU time 0.6 seconds
Started Jul 05 05:52:48 PM PDT 24
Finished Jul 05 05:52:51 PM PDT 24
Peak memory 197840 kb
Host smart-4345dd13-3da2-4d83-ad0a-b41292f6faaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425473514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.2425473514
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.2166190902
Short name T217
Test name
Test status
Simulation time 100470884 ps
CPU time 0.61 seconds
Started Jul 05 05:52:43 PM PDT 24
Finished Jul 05 05:52:46 PM PDT 24
Peak memory 197764 kb
Host smart-6813b223-f5d2-4b83-8f3c-0ab6d109b8c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166190902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.2166190902
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.1620904154
Short name T402
Test name
Test status
Simulation time 111278843 ps
CPU time 0.67 seconds
Started Jul 05 05:52:43 PM PDT 24
Finished Jul 05 05:52:45 PM PDT 24
Peak memory 201092 kb
Host smart-ecdafe9f-0fec-4188-b608-f07845c916ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620904154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.1620904154
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_wakeup_race.4168688074
Short name T335
Test name
Test status
Simulation time 107245371 ps
CPU time 0.85 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:50 PM PDT 24
Peak memory 198928 kb
Host smart-ac3b0ca7-f76d-44c0-aa0e-0d48675ec45a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168688074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_w
akeup_race.4168688074
Directory /workspace/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.713791025
Short name T970
Test name
Test status
Simulation time 105477163 ps
CPU time 0.81 seconds
Started Jul 05 05:52:42 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 199704 kb
Host smart-7dd5ff28-3ad7-4728-91b6-edf0812dbc86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713791025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.713791025
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.997107133
Short name T415
Test name
Test status
Simulation time 104539681 ps
CPU time 0.95 seconds
Started Jul 05 05:52:57 PM PDT 24
Finished Jul 05 05:52:59 PM PDT 24
Peak memory 209344 kb
Host smart-93cb8929-41a9-4256-8fce-17d4f4554e54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997107133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.997107133
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.2736796137
Short name T625
Test name
Test status
Simulation time 311256651 ps
CPU time 0.97 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:50 PM PDT 24
Peak memory 199752 kb
Host smart-432d3e3d-a500-46c9-8b76-8eeb11ffd61c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736796137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_
cm_ctrl_config_regwen.2736796137
Directory /workspace/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1142906909
Short name T338
Test name
Test status
Simulation time 819956118 ps
CPU time 2.99 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:52 PM PDT 24
Peak memory 200900 kb
Host smart-60e75871-1803-48e4-a832-904606545eb4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142906909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1142906909
Directory /workspace/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1166318407
Short name T564
Test name
Test status
Simulation time 910045992 ps
CPU time 2.53 seconds
Started Jul 05 05:52:43 PM PDT 24
Finished Jul 05 05:52:46 PM PDT 24
Peak memory 200952 kb
Host smart-11906249-163c-48a1-a4b9-2808dde7d62d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166318407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1166318407
Directory /workspace/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2634206603
Short name T585
Test name
Test status
Simulation time 268259269 ps
CPU time 0.88 seconds
Started Jul 05 05:53:10 PM PDT 24
Finished Jul 05 05:53:12 PM PDT 24
Peak memory 199160 kb
Host smart-ddd95871-3df8-43c4-8fac-d20bcb3ef2bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634206603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2634206603
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.2295913498
Short name T811
Test name
Test status
Simulation time 31539564 ps
CPU time 0.7 seconds
Started Jul 05 05:52:47 PM PDT 24
Finished Jul 05 05:52:51 PM PDT 24
Peak memory 199148 kb
Host smart-9e214cac-3d6b-4eb3-99af-5553a24671fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295913498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.2295913498
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all.3367684943
Short name T502
Test name
Test status
Simulation time 2074190466 ps
CPU time 5.85 seconds
Started Jul 05 05:52:58 PM PDT 24
Finished Jul 05 05:53:04 PM PDT 24
Peak memory 200972 kb
Host smart-5a776840-fa3b-4b29-b784-6b3c2cf92b3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367684943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.3367684943
Directory /workspace/45.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all_with_rand_reset.907344747
Short name T54
Test name
Test status
Simulation time 8791998649 ps
CPU time 30.42 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:53:18 PM PDT 24
Peak memory 201144 kb
Host smart-ab96cbce-435d-4b3e-977c-27e97e542d57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907344747 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all_with_rand_reset.907344747
Directory /workspace/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup.1158572659
Short name T251
Test name
Test status
Simulation time 162450093 ps
CPU time 0.81 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 198380 kb
Host smart-b3c75c62-6b72-4c89-95cd-5bd7b376b073
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158572659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.1158572659
Directory /workspace/45.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup_reset.1586237558
Short name T650
Test name
Test status
Simulation time 270428630 ps
CPU time 0.85 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:47 PM PDT 24
Peak memory 199056 kb
Host smart-d8605efa-f343-4883-b0b3-e399ea93f79e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586237558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.1586237558
Directory /workspace/45.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.2417252890
Short name T355
Test name
Test status
Simulation time 198780888 ps
CPU time 0.77 seconds
Started Jul 05 05:53:04 PM PDT 24
Finished Jul 05 05:53:06 PM PDT 24
Peak memory 199644 kb
Host smart-ea520a03-5bcb-4999-a6c3-49bcfca9649a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417252890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.2417252890
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.259228521
Short name T993
Test name
Test status
Simulation time 57109303 ps
CPU time 0.82 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:48 PM PDT 24
Peak memory 198856 kb
Host smart-463b3629-2012-465d-ba73-2dc4b36c4552
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259228521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disa
ble_rom_integrity_check.259228521
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.269618779
Short name T386
Test name
Test status
Simulation time 35313683 ps
CPU time 0.59 seconds
Started Jul 05 05:52:41 PM PDT 24
Finished Jul 05 05:52:42 PM PDT 24
Peak memory 197828 kb
Host smart-f042bd25-042a-4977-90d5-18609a212dd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269618779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_
malfunc.269618779
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.2196101613
Short name T354
Test name
Test status
Simulation time 664766139 ps
CPU time 0.92 seconds
Started Jul 05 05:52:42 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 198172 kb
Host smart-1ba16694-e1a7-4791-9c33-2bc4e0dc30d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196101613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.2196101613
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.3709440102
Short name T263
Test name
Test status
Simulation time 55078635 ps
CPU time 0.71 seconds
Started Jul 05 05:52:43 PM PDT 24
Finished Jul 05 05:52:45 PM PDT 24
Peak memory 197136 kb
Host smart-f7ec13de-e3de-40b2-be62-e3691d6f47b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709440102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.3709440102
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.2792115711
Short name T719
Test name
Test status
Simulation time 71443196 ps
CPU time 0.63 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 197764 kb
Host smart-985cd65d-247b-46b6-8341-003ab658a3fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792115711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.2792115711
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.1264981152
Short name T242
Test name
Test status
Simulation time 52223502 ps
CPU time 0.68 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:50 PM PDT 24
Peak memory 201124 kb
Host smart-26ad37ed-45e2-4bea-90a6-223bd4a35cb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264981152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.1264981152
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.2589644409
Short name T794
Test name
Test status
Simulation time 201943076 ps
CPU time 1.05 seconds
Started Jul 05 05:52:58 PM PDT 24
Finished Jul 05 05:52:59 PM PDT 24
Peak memory 198400 kb
Host smart-a5fd8895-1886-44c7-b4f2-9ae08d080da3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589644409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_w
akeup_race.2589644409
Directory /workspace/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.834749718
Short name T337
Test name
Test status
Simulation time 83843788 ps
CPU time 0.77 seconds
Started Jul 05 05:53:12 PM PDT 24
Finished Jul 05 05:53:13 PM PDT 24
Peak memory 198200 kb
Host smart-cc649344-d898-4b9a-8814-0e0aa3d53b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834749718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.834749718
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.1863165115
Short name T601
Test name
Test status
Simulation time 99565936 ps
CPU time 0.89 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:48 PM PDT 24
Peak memory 209312 kb
Host smart-d418b478-0b6f-4ba2-902f-219d172d4ff1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863165115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.1863165115
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.2381921185
Short name T857
Test name
Test status
Simulation time 282154469 ps
CPU time 1.01 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 200324 kb
Host smart-7f0fb620-de0a-40bd-a520-3155ff5a2f7b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381921185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_
cm_ctrl_config_regwen.2381921185
Directory /workspace/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2333841228
Short name T995
Test name
Test status
Simulation time 836857916 ps
CPU time 3.04 seconds
Started Jul 05 05:52:41 PM PDT 24
Finished Jul 05 05:52:45 PM PDT 24
Peak memory 200956 kb
Host smart-27a8eb38-0a72-4afe-9455-92125f48cb94
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333841228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2333841228
Directory /workspace/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3046274279
Short name T175
Test name
Test status
Simulation time 1806160411 ps
CPU time 2.03 seconds
Started Jul 05 05:52:58 PM PDT 24
Finished Jul 05 05:53:01 PM PDT 24
Peak memory 200804 kb
Host smart-fee8aa1c-4e26-40d9-87b7-a317d2292e78
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046274279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3046274279
Directory /workspace/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2835910726
Short name T490
Test name
Test status
Simulation time 91206276 ps
CPU time 0.84 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 198900 kb
Host smart-e741d61a-41cd-4f92-8e25-73e97834c454
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835910726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2835910726
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.1140809888
Short name T229
Test name
Test status
Simulation time 56045002 ps
CPU time 0.65 seconds
Started Jul 05 05:52:49 PM PDT 24
Finished Jul 05 05:52:51 PM PDT 24
Peak memory 198316 kb
Host smart-6225c5e6-3adf-4303-af7f-32b6318a9be6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140809888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.1140809888
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all.2681563105
Short name T898
Test name
Test status
Simulation time 1854030877 ps
CPU time 3.68 seconds
Started Jul 05 05:52:56 PM PDT 24
Finished Jul 05 05:53:00 PM PDT 24
Peak memory 200944 kb
Host smart-4491b625-8914-487c-8775-b85f80b145f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681563105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.2681563105
Directory /workspace/46.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all_with_rand_reset.4289365621
Short name T163
Test name
Test status
Simulation time 15055171318 ps
CPU time 19.93 seconds
Started Jul 05 05:52:56 PM PDT 24
Finished Jul 05 05:53:16 PM PDT 24
Peak memory 201124 kb
Host smart-e6c773d3-e2d5-4662-9d5d-bd197a1754ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289365621 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all_with_rand_reset.4289365621
Directory /workspace/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup.3384455369
Short name T582
Test name
Test status
Simulation time 67264466 ps
CPU time 0.76 seconds
Started Jul 05 05:52:42 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 198932 kb
Host smart-49abab8b-8bab-4b15-8c51-ebd68054f0ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384455369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.3384455369
Directory /workspace/46.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup_reset.3818180215
Short name T344
Test name
Test status
Simulation time 304434008 ps
CPU time 0.97 seconds
Started Jul 05 05:52:58 PM PDT 24
Finished Jul 05 05:52:59 PM PDT 24
Peak memory 199956 kb
Host smart-66b03e65-bd22-45cb-843f-b7c0321bd7fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818180215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.3818180215
Directory /workspace/46.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.1831966743
Short name T128
Test name
Test status
Simulation time 37376266 ps
CPU time 0.84 seconds
Started Jul 05 05:53:04 PM PDT 24
Finished Jul 05 05:53:07 PM PDT 24
Peak memory 199960 kb
Host smart-6b041bfa-d983-4990-907d-d1e9e0e86fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831966743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.1831966743
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.3901680406
Short name T43
Test name
Test status
Simulation time 66707375 ps
CPU time 0.71 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:47 PM PDT 24
Peak memory 198332 kb
Host smart-5a080271-a38c-490f-9f64-bca1ae38e6ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901680406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.3901680406
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.1433043663
Short name T982
Test name
Test status
Simulation time 30399200 ps
CPU time 0.67 seconds
Started Jul 05 05:53:03 PM PDT 24
Finished Jul 05 05:53:06 PM PDT 24
Peak memory 197784 kb
Host smart-6830527a-037f-43c4-9941-59f79ca218bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433043663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.1433043663
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.837837504
Short name T95
Test name
Test status
Simulation time 625903316 ps
CPU time 0.93 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:48 PM PDT 24
Peak memory 197820 kb
Host smart-20ec15f6-98f8-4e1b-88a7-24a0c25cbfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837837504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.837837504
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.40745621
Short name T29
Test name
Test status
Simulation time 55988086 ps
CPU time 0.62 seconds
Started Jul 05 05:53:00 PM PDT 24
Finished Jul 05 05:53:01 PM PDT 24
Peak memory 197868 kb
Host smart-a7133c00-bcc3-4216-8cef-c31c1d0d4252
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40745621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.40745621
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.2694965800
Short name T810
Test name
Test status
Simulation time 29950445 ps
CPU time 0.63 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 197856 kb
Host smart-664eae98-d57d-4192-8f12-31490023c991
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694965800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2694965800
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.2967825259
Short name T218
Test name
Test status
Simulation time 64120623 ps
CPU time 0.67 seconds
Started Jul 05 05:55:23 PM PDT 24
Finished Jul 05 05:55:25 PM PDT 24
Peak memory 201092 kb
Host smart-a0f16182-f8a8-4e10-b90e-4b7743a8fc90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967825259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.2967825259
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.4281088
Short name T869
Test name
Test status
Simulation time 334156900 ps
CPU time 0.98 seconds
Started Jul 05 05:52:47 PM PDT 24
Finished Jul 05 05:52:51 PM PDT 24
Peak memory 199532 kb
Host smart-eb702b7b-65a0-47f5-8389-a19dc6fa32aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_
race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_wake
up_race.4281088
Directory /workspace/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.2402115543
Short name T701
Test name
Test status
Simulation time 57089194 ps
CPU time 0.82 seconds
Started Jul 05 05:53:02 PM PDT 24
Finished Jul 05 05:53:04 PM PDT 24
Peak memory 198460 kb
Host smart-db8252c3-e7ac-42a9-b784-b4f9f8f31498
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402115543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.2402115543
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.2100774395
Short name T325
Test name
Test status
Simulation time 163958711 ps
CPU time 0.8 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:50 PM PDT 24
Peak memory 209304 kb
Host smart-98a82356-d178-454d-9d60-10382e2bb8a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100774395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.2100774395
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.3394700366
Short name T302
Test name
Test status
Simulation time 276191792 ps
CPU time 1.02 seconds
Started Jul 05 05:52:42 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 199884 kb
Host smart-ca33c73a-bc47-4d2d-83be-139747401be7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394700366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_
cm_ctrl_config_regwen.3394700366
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4266886824
Short name T600
Test name
Test status
Simulation time 1199869072 ps
CPU time 2.38 seconds
Started Jul 05 05:53:07 PM PDT 24
Finished Jul 05 05:53:11 PM PDT 24
Peak memory 200816 kb
Host smart-bfdc5184-72d4-45ad-8e20-6cd71e9509b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266886824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4266886824
Directory /workspace/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2950893957
Short name T315
Test name
Test status
Simulation time 966732400 ps
CPU time 2.72 seconds
Started Jul 05 05:52:42 PM PDT 24
Finished Jul 05 05:52:45 PM PDT 24
Peak memory 200952 kb
Host smart-1ecb2877-83b6-4daf-9ff0-3da2c46f30ac
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950893957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2950893957
Directory /workspace/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3946646110
Short name T550
Test name
Test status
Simulation time 138878726 ps
CPU time 0.85 seconds
Started Jul 05 05:52:45 PM PDT 24
Finished Jul 05 05:52:48 PM PDT 24
Peak memory 199020 kb
Host smart-53cd7cb1-2de1-4571-8057-a68ace3b06b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946646110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3946646110
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.1407302731
Short name T247
Test name
Test status
Simulation time 76367291 ps
CPU time 0.63 seconds
Started Jul 05 05:53:11 PM PDT 24
Finished Jul 05 05:53:13 PM PDT 24
Peak memory 198228 kb
Host smart-d1097426-b25a-4fc4-a65e-022ac0981362
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407302731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.1407302731
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all.9160837
Short name T450
Test name
Test status
Simulation time 1735261556 ps
CPU time 2.6 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:48 PM PDT 24
Peak memory 200964 kb
Host smart-cefe902b-996f-4f24-bf76-cf3801cde069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9160837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.9160837
Directory /workspace/47.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all_with_rand_reset.1064362490
Short name T90
Test name
Test status
Simulation time 2316839730 ps
CPU time 7.83 seconds
Started Jul 05 05:52:48 PM PDT 24
Finished Jul 05 05:52:58 PM PDT 24
Peak memory 201172 kb
Host smart-b37e7863-74b7-4e0e-91c9-93a5fbd102b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064362490 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all_with_rand_reset.1064362490
Directory /workspace/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup.3841586827
Short name T874
Test name
Test status
Simulation time 120047572 ps
CPU time 0.87 seconds
Started Jul 05 05:53:09 PM PDT 24
Finished Jul 05 05:53:11 PM PDT 24
Peak memory 198068 kb
Host smart-4a99aced-84e5-41f1-8276-b6ac74c5de81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841586827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.3841586827
Directory /workspace/47.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup_reset.3606908013
Short name T179
Test name
Test status
Simulation time 372856844 ps
CPU time 1.13 seconds
Started Jul 05 05:52:59 PM PDT 24
Finished Jul 05 05:53:01 PM PDT 24
Peak memory 200764 kb
Host smart-2dbf9c73-1a3b-4138-8845-b030295cdcad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606908013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.3606908013
Directory /workspace/47.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.2949326317
Short name T392
Test name
Test status
Simulation time 178052840 ps
CPU time 0.92 seconds
Started Jul 05 05:53:03 PM PDT 24
Finished Jul 05 05:53:06 PM PDT 24
Peak memory 199900 kb
Host smart-1bc8a07c-2997-492a-b6f0-9884c965d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949326317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.2949326317
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.2813438358
Short name T728
Test name
Test status
Simulation time 77328107 ps
CPU time 0.72 seconds
Started Jul 05 05:53:08 PM PDT 24
Finished Jul 05 05:53:10 PM PDT 24
Peak memory 198856 kb
Host smart-4b4b3242-5586-41e9-b4bf-512d832bebe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813438358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.2813438358
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.1756787276
Short name T419
Test name
Test status
Simulation time 29565773 ps
CPU time 0.66 seconds
Started Jul 05 05:52:51 PM PDT 24
Finished Jul 05 05:52:53 PM PDT 24
Peak memory 197068 kb
Host smart-8b2973a7-9890-4064-beaa-f76a7b8d37aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756787276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.1756787276
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.2169744153
Short name T356
Test name
Test status
Simulation time 166982573 ps
CPU time 0.99 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:54 PM PDT 24
Peak memory 198184 kb
Host smart-1336f1d7-e332-4062-b2b7-dc026b06b56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169744153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.2169744153
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.562721655
Short name T930
Test name
Test status
Simulation time 54756434 ps
CPU time 0.63 seconds
Started Jul 05 05:52:52 PM PDT 24
Finished Jul 05 05:52:54 PM PDT 24
Peak memory 197072 kb
Host smart-8d174ece-5adf-4a7d-8fe1-c9bf983dc58e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562721655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.562721655
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.251133872
Short name T433
Test name
Test status
Simulation time 37980122 ps
CPU time 0.63 seconds
Started Jul 05 05:52:42 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 197860 kb
Host smart-33ed453f-bd7b-440d-8749-bd54bc100042
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251133872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.251133872
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.3670861113
Short name T747
Test name
Test status
Simulation time 69135474 ps
CPU time 0.67 seconds
Started Jul 05 05:52:58 PM PDT 24
Finished Jul 05 05:53:00 PM PDT 24
Peak memory 201128 kb
Host smart-ecc31b6b-a0ce-4d6e-96c2-412cea14ea80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670861113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.3670861113
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.3523437488
Short name T834
Test name
Test status
Simulation time 122584974 ps
CPU time 0.79 seconds
Started Jul 05 05:52:47 PM PDT 24
Finished Jul 05 05:52:50 PM PDT 24
Peak memory 198252 kb
Host smart-595d9bc1-a855-46df-a74c-2acb9c6bc91e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523437488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_w
akeup_race.3523437488
Directory /workspace/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.658348183
Short name T484
Test name
Test status
Simulation time 66499917 ps
CPU time 0.66 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:46 PM PDT 24
Peak memory 198900 kb
Host smart-f6719dbe-9530-4e60-9f92-881bb8ba8030
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658348183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.658348183
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.1472024254
Short name T774
Test name
Test status
Simulation time 115177183 ps
CPU time 0.85 seconds
Started Jul 05 05:52:49 PM PDT 24
Finished Jul 05 05:52:52 PM PDT 24
Peak memory 209312 kb
Host smart-d7bfd5bd-7ad4-476e-9923-5abf2d9b1cc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472024254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.1472024254
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3220456291
Short name T759
Test name
Test status
Simulation time 255287723 ps
CPU time 1.34 seconds
Started Jul 05 05:53:02 PM PDT 24
Finished Jul 05 05:53:04 PM PDT 24
Peak memory 200528 kb
Host smart-f4af41bb-b79d-4d4f-b900-0043b69f3107
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220456291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_
cm_ctrl_config_regwen.3220456291
Directory /workspace/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.452986047
Short name T969
Test name
Test status
Simulation time 876679398 ps
CPU time 2.18 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 200876 kb
Host smart-96d44707-062f-47f6-9e60-313850ebd9d2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452986047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.452986047
Directory /workspace/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3810336378
Short name T393
Test name
Test status
Simulation time 1402793985 ps
CPU time 1.9 seconds
Started Jul 05 05:53:06 PM PDT 24
Finished Jul 05 05:53:10 PM PDT 24
Peak memory 200840 kb
Host smart-0d75c493-2651-4452-b24d-c789311eeee9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810336378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3810336378
Directory /workspace/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1251385313
Short name T199
Test name
Test status
Simulation time 261802242 ps
CPU time 0.86 seconds
Started Jul 05 05:53:03 PM PDT 24
Finished Jul 05 05:53:06 PM PDT 24
Peak memory 199440 kb
Host smart-27b0c11c-1bfb-4e6d-bb24-842041acda56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251385313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1251385313
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.3260194318
Short name T364
Test name
Test status
Simulation time 39130789 ps
CPU time 0.65 seconds
Started Jul 05 05:53:12 PM PDT 24
Finished Jul 05 05:53:13 PM PDT 24
Peak memory 198940 kb
Host smart-da865286-e94b-4f03-8b6b-1b4c63656fe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260194318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.3260194318
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all.3357840904
Short name T123
Test name
Test status
Simulation time 1261520903 ps
CPU time 4.44 seconds
Started Jul 05 05:52:52 PM PDT 24
Finished Jul 05 05:52:57 PM PDT 24
Peak memory 200904 kb
Host smart-199348c1-560a-4921-bff5-234649a168f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357840904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.3357840904
Directory /workspace/48.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all_with_rand_reset.492706693
Short name T60
Test name
Test status
Simulation time 14028995925 ps
CPU time 21.79 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:53:09 PM PDT 24
Peak memory 201136 kb
Host smart-58343776-c420-46ee-bc04-2650bdbeae73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492706693 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all_with_rand_reset.492706693
Directory /workspace/48.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup.3158416640
Short name T894
Test name
Test status
Simulation time 718578586 ps
CPU time 0.8 seconds
Started Jul 05 05:52:49 PM PDT 24
Finished Jul 05 05:52:52 PM PDT 24
Peak memory 198288 kb
Host smart-46a1947f-9a27-46e6-af2b-be619b91352b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158416640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.3158416640
Directory /workspace/48.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup_reset.2160740796
Short name T965
Test name
Test status
Simulation time 285486853 ps
CPU time 1.54 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:48 PM PDT 24
Peak memory 200636 kb
Host smart-a93ec0c4-4fd6-41fb-b120-62cf7c83b801
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160740796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.2160740796
Directory /workspace/48.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.2442405795
Short name T100
Test name
Test status
Simulation time 22990378 ps
CPU time 0.74 seconds
Started Jul 05 05:53:05 PM PDT 24
Finished Jul 05 05:53:07 PM PDT 24
Peak memory 198952 kb
Host smart-9361bd02-4000-4f85-bcd8-247f188e76b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442405795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.2442405795
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.1292948547
Short name T664
Test name
Test status
Simulation time 80547865 ps
CPU time 0.73 seconds
Started Jul 05 05:53:02 PM PDT 24
Finished Jul 05 05:53:03 PM PDT 24
Peak memory 198296 kb
Host smart-f6cf45b0-ca97-4cc5-bc07-eab836d07d3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292948547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.1292948547
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.488766800
Short name T381
Test name
Test status
Simulation time 34571223 ps
CPU time 0.61 seconds
Started Jul 05 05:53:03 PM PDT 24
Finished Jul 05 05:53:04 PM PDT 24
Peak memory 197040 kb
Host smart-f535de9f-3b5b-4704-98d5-11f9133ef6cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488766800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_
malfunc.488766800
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.3897308397
Short name T1
Test name
Test status
Simulation time 165186319 ps
CPU time 0.97 seconds
Started Jul 05 05:52:51 PM PDT 24
Finished Jul 05 05:52:54 PM PDT 24
Peak memory 198164 kb
Host smart-afbc3505-4bc9-41b6-8ab7-82b7112e8e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897308397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.3897308397
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.1150851213
Short name T599
Test name
Test status
Simulation time 37443078 ps
CPU time 0.66 seconds
Started Jul 05 05:53:09 PM PDT 24
Finished Jul 05 05:53:11 PM PDT 24
Peak memory 197140 kb
Host smart-db32569b-6d1f-454a-a9b1-8dfa906bdc7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150851213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.1150851213
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.3415149288
Short name T880
Test name
Test status
Simulation time 50791080 ps
CPU time 0.6 seconds
Started Jul 05 05:53:04 PM PDT 24
Finished Jul 05 05:53:07 PM PDT 24
Peak memory 197804 kb
Host smart-4c447706-1d4d-4755-b1d8-9ab2fd8c0ca7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415149288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.3415149288
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.1360006420
Short name T732
Test name
Test status
Simulation time 75251698 ps
CPU time 0.67 seconds
Started Jul 05 05:52:52 PM PDT 24
Finished Jul 05 05:52:53 PM PDT 24
Peak memory 201120 kb
Host smart-3a6ea7d8-4672-4b7f-9ddc-224398fc0754
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360006420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.1360006420
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.3306305532
Short name T523
Test name
Test status
Simulation time 273449597 ps
CPU time 0.8 seconds
Started Jul 05 05:52:46 PM PDT 24
Finished Jul 05 05:52:49 PM PDT 24
Peak memory 198088 kb
Host smart-a59b3031-43e2-4d83-8423-cad583942e04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306305532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_w
akeup_race.3306305532
Directory /workspace/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.303256898
Short name T783
Test name
Test status
Simulation time 63849139 ps
CPU time 0.99 seconds
Started Jul 05 05:53:08 PM PDT 24
Finished Jul 05 05:53:10 PM PDT 24
Peak memory 199524 kb
Host smart-9c692f1c-d0b8-4dfb-9ffd-bb5c7e08e259
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303256898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.303256898
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.1975468959
Short name T270
Test name
Test status
Simulation time 109161193 ps
CPU time 1.02 seconds
Started Jul 05 05:52:50 PM PDT 24
Finished Jul 05 05:52:53 PM PDT 24
Peak memory 209324 kb
Host smart-65ef8435-795a-42a1-963b-edf884b46494
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975468959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.1975468959
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.1476237325
Short name T10
Test name
Test status
Simulation time 100970169 ps
CPU time 0.78 seconds
Started Jul 05 05:53:04 PM PDT 24
Finished Jul 05 05:53:06 PM PDT 24
Peak memory 198900 kb
Host smart-9a184142-142f-4441-80cb-b2f58beba7be
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476237325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_
cm_ctrl_config_regwen.1476237325
Directory /workspace/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3775848537
Short name T840
Test name
Test status
Simulation time 1681403993 ps
CPU time 1.84 seconds
Started Jul 05 05:52:51 PM PDT 24
Finished Jul 05 05:52:54 PM PDT 24
Peak memory 200876 kb
Host smart-0deddb9d-f485-45b8-b6c5-0caa6e6eab87
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775848537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3775848537
Directory /workspace/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3668298200
Short name T480
Test name
Test status
Simulation time 970477255 ps
CPU time 2.43 seconds
Started Jul 05 05:53:09 PM PDT 24
Finished Jul 05 05:53:13 PM PDT 24
Peak memory 200932 kb
Host smart-519cbb0b-b9bc-4a3f-aac6-1c5548e54e1e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668298200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3668298200
Directory /workspace/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1770851504
Short name T329
Test name
Test status
Simulation time 88013112 ps
CPU time 0.85 seconds
Started Jul 05 05:53:06 PM PDT 24
Finished Jul 05 05:53:08 PM PDT 24
Peak memory 199052 kb
Host smart-796679aa-8eaf-488e-a5ae-3bc837e12190
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770851504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1770851504
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.2716931432
Short name T35
Test name
Test status
Simulation time 32375432 ps
CPU time 0.72 seconds
Started Jul 05 05:53:11 PM PDT 24
Finished Jul 05 05:53:13 PM PDT 24
Peak memory 198280 kb
Host smart-46255741-2a0f-4fa1-8a12-bcdce4f998a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716931432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.2716931432
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all.2956203365
Short name T876
Test name
Test status
Simulation time 1295636980 ps
CPU time 2.47 seconds
Started Jul 05 05:52:41 PM PDT 24
Finished Jul 05 05:52:44 PM PDT 24
Peak memory 200992 kb
Host smart-038e5d4a-d49f-4d3b-a90b-3b6e54ce7739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956203365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.2956203365
Directory /workspace/49.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all_with_rand_reset.3250721986
Short name T694
Test name
Test status
Simulation time 4056308559 ps
CPU time 6.47 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:53 PM PDT 24
Peak memory 201100 kb
Host smart-dfd7f46e-a6c6-46a2-8111-55bfa9af6b6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250721986 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all_with_rand_reset.3250721986
Directory /workspace/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup.2867560417
Short name T939
Test name
Test status
Simulation time 154516855 ps
CPU time 0.84 seconds
Started Jul 05 05:53:09 PM PDT 24
Finished Jul 05 05:53:11 PM PDT 24
Peak memory 198252 kb
Host smart-079d07ef-ad1e-4b65-bfb9-9a10a8dd3197
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867560417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.2867560417
Directory /workspace/49.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup_reset.338582527
Short name T827
Test name
Test status
Simulation time 353634184 ps
CPU time 1.22 seconds
Started Jul 05 05:53:11 PM PDT 24
Finished Jul 05 05:53:13 PM PDT 24
Peak memory 200788 kb
Host smart-a851ff46-47d8-4aef-9f61-344ae10c3190
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338582527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.338582527
Directory /workspace/49.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.276845271
Short name T673
Test name
Test status
Simulation time 60817011 ps
CPU time 0.77 seconds
Started Jul 05 05:50:44 PM PDT 24
Finished Jul 05 05:50:45 PM PDT 24
Peak memory 198948 kb
Host smart-b5661a88-602e-4446-8863-254e789be163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276845271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.276845271
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.1918727854
Short name T418
Test name
Test status
Simulation time 65665306 ps
CPU time 0.89 seconds
Started Jul 05 05:50:47 PM PDT 24
Finished Jul 05 05:50:49 PM PDT 24
Peak memory 198840 kb
Host smart-0c7a4486-b989-4431-a20f-3c4f33711646
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918727854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.1918727854
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1851865216
Short name T282
Test name
Test status
Simulation time 32944994 ps
CPU time 0.6 seconds
Started Jul 05 05:50:53 PM PDT 24
Finished Jul 05 05:50:56 PM PDT 24
Peak memory 197740 kb
Host smart-85198e3c-9a50-4e74-adf0-b7704029f83a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851865216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.1851865216
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.2235215606
Short name T614
Test name
Test status
Simulation time 192126248 ps
CPU time 0.99 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:03 PM PDT 24
Peak memory 197856 kb
Host smart-9c375028-d715-4752-b8a5-7a36c71ab16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235215606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.2235215606
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.4196544909
Short name T561
Test name
Test status
Simulation time 74717724 ps
CPU time 0.64 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:01 PM PDT 24
Peak memory 197804 kb
Host smart-860c7d3b-caf0-4375-aee3-3b627e22530f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196544909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.4196544909
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.1454239323
Short name T667
Test name
Test status
Simulation time 228452211 ps
CPU time 0.6 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:03 PM PDT 24
Peak memory 197820 kb
Host smart-9a228747-a82e-44e7-b530-759a7e8ed5f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454239323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.1454239323
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.1401467527
Short name T310
Test name
Test status
Simulation time 77240918 ps
CPU time 0.68 seconds
Started Jul 05 05:50:50 PM PDT 24
Finished Jul 05 05:50:53 PM PDT 24
Peak memory 201120 kb
Host smart-ef245c53-22ea-4023-ad22-c676ef832959
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401467527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.1401467527
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.3170504965
Short name T411
Test name
Test status
Simulation time 151865608 ps
CPU time 1.02 seconds
Started Jul 05 05:50:55 PM PDT 24
Finished Jul 05 05:50:58 PM PDT 24
Peak memory 198140 kb
Host smart-64a0ced4-7aa6-41e9-868e-594dda83dac3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170504965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wa
keup_race.3170504965
Directory /workspace/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.104687080
Short name T562
Test name
Test status
Simulation time 35561986 ps
CPU time 0.77 seconds
Started Jul 05 05:50:56 PM PDT 24
Finished Jul 05 05:50:59 PM PDT 24
Peak memory 198948 kb
Host smart-1814f3b3-adb4-4bb7-8384-bcff552be2c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104687080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.104687080
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.3938395316
Short name T904
Test name
Test status
Simulation time 221064059 ps
CPU time 0.81 seconds
Started Jul 05 05:50:53 PM PDT 24
Finished Jul 05 05:50:56 PM PDT 24
Peak memory 209344 kb
Host smart-7ff67d09-4e38-4718-9d78-f9a8eae3abdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938395316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.3938395316
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3422220994
Short name T598
Test name
Test status
Simulation time 74379290 ps
CPU time 0.63 seconds
Started Jul 05 05:50:52 PM PDT 24
Finished Jul 05 05:50:55 PM PDT 24
Peak memory 198272 kb
Host smart-896a0764-1e26-454e-9263-5517a45865e3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422220994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_c
m_ctrl_config_regwen.3422220994
Directory /workspace/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3613229790
Short name T563
Test name
Test status
Simulation time 839353636 ps
CPU time 3.18 seconds
Started Jul 05 05:50:57 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 200880 kb
Host smart-d0fff24a-e1e9-4082-b661-11e1c89f12ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613229790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3613229790
Directory /workspace/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.967123768
Short name T548
Test name
Test status
Simulation time 892486412 ps
CPU time 2.34 seconds
Started Jul 05 05:51:04 PM PDT 24
Finished Jul 05 05:51:08 PM PDT 24
Peak memory 200940 kb
Host smart-db7d234b-5794-4879-89cf-81070938c329
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967123768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.967123768
Directory /workspace/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3470312971
Short name T459
Test name
Test status
Simulation time 65965276 ps
CPU time 0.99 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 199152 kb
Host smart-1a85c266-0660-4504-8ab9-13807088076c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470312971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3470312971
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.1883162638
Short name T117
Test name
Test status
Simulation time 29853404 ps
CPU time 0.76 seconds
Started Jul 05 05:50:55 PM PDT 24
Finished Jul 05 05:50:57 PM PDT 24
Peak memory 199112 kb
Host smart-5bf30ba9-5459-4b0e-8504-1756a7f1e8cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883162638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.1883162638
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all.3725164853
Short name T362
Test name
Test status
Simulation time 1666459930 ps
CPU time 4.08 seconds
Started Jul 05 05:50:55 PM PDT 24
Finished Jul 05 05:51:01 PM PDT 24
Peak memory 200936 kb
Host smart-a962df2b-d400-45f1-ae88-e023e3ef0f81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725164853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.3725164853
Directory /workspace/5.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all_with_rand_reset.2377224408
Short name T375
Test name
Test status
Simulation time 10661332183 ps
CPU time 30.32 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:33 PM PDT 24
Peak memory 201100 kb
Host smart-2f3a4957-7187-4b5b-997b-5b0a89b31904
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377224408 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all_with_rand_reset.2377224408
Directory /workspace/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.966971806
Short name T587
Test name
Test status
Simulation time 275533422 ps
CPU time 0.92 seconds
Started Jul 05 05:50:57 PM PDT 24
Finished Jul 05 05:50:59 PM PDT 24
Peak memory 199416 kb
Host smart-ed355b29-ffe1-4bbc-b6da-67684f8d0ce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966971806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.966971806
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup_reset.1206289466
Short name T903
Test name
Test status
Simulation time 142127842 ps
CPU time 0.78 seconds
Started Jul 05 05:50:57 PM PDT 24
Finished Jul 05 05:50:59 PM PDT 24
Peak memory 199164 kb
Host smart-bfe5ce60-b830-451d-bcd0-91a4532f9846
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206289466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.1206289466
Directory /workspace/5.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.640360540
Short name T607
Test name
Test status
Simulation time 294475363 ps
CPU time 0.83 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:50:57 PM PDT 24
Peak memory 199704 kb
Host smart-5ce67b98-2292-4d4c-b15e-0e9f71d908f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640360540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.640360540
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.790043222
Short name T638
Test name
Test status
Simulation time 68742630 ps
CPU time 0.77 seconds
Started Jul 05 05:51:03 PM PDT 24
Finished Jul 05 05:51:06 PM PDT 24
Peak memory 198832 kb
Host smart-29b29f4a-ec68-40bf-8ac6-f35bce3ead79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790043222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disab
le_rom_integrity_check.790043222
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.3782627681
Short name T986
Test name
Test status
Simulation time 37449737 ps
CPU time 0.58 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 197772 kb
Host smart-a550f287-4451-42ae-a4b9-0782dff6c798
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782627681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.3782627681
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.3007829670
Short name T409
Test name
Test status
Simulation time 157357003 ps
CPU time 1 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:50:57 PM PDT 24
Peak memory 197868 kb
Host smart-c9ad0a42-5c9c-4312-892f-302d1ed86ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007829670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.3007829670
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.3256479133
Short name T985
Test name
Test status
Simulation time 50139478 ps
CPU time 0.68 seconds
Started Jul 05 05:50:52 PM PDT 24
Finished Jul 05 05:50:55 PM PDT 24
Peak memory 197804 kb
Host smart-c725830c-8a01-451d-89df-82f54a74e0b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256479133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3256479133
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.872838657
Short name T30
Test name
Test status
Simulation time 50311363 ps
CPU time 0.59 seconds
Started Jul 05 05:50:58 PM PDT 24
Finished Jul 05 05:51:00 PM PDT 24
Peak memory 197812 kb
Host smart-437ae79f-a09c-451e-9cbb-631bd5b04933
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872838657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.872838657
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.4084382301
Short name T220
Test name
Test status
Simulation time 258200638 ps
CPU time 0.67 seconds
Started Jul 05 05:50:57 PM PDT 24
Finished Jul 05 05:50:59 PM PDT 24
Peak memory 201116 kb
Host smart-c6106555-f896-4555-9421-6bdd59fb49bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084382301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.4084382301
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.1231503761
Short name T441
Test name
Test status
Simulation time 309207525 ps
CPU time 0.94 seconds
Started Jul 05 05:50:50 PM PDT 24
Finished Jul 05 05:50:53 PM PDT 24
Peak memory 199532 kb
Host smart-7c62fbbe-c334-4e41-acf8-737edc2d866a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231503761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wa
keup_race.1231503761
Directory /workspace/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.2865954842
Short name T323
Test name
Test status
Simulation time 88188362 ps
CPU time 0.9 seconds
Started Jul 05 05:50:57 PM PDT 24
Finished Jul 05 05:50:59 PM PDT 24
Peak memory 199680 kb
Host smart-95d83bcf-eebb-482b-8285-ac6a37733f60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865954842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.2865954842
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.228526702
Short name T545
Test name
Test status
Simulation time 117640038 ps
CPU time 0.91 seconds
Started Jul 05 05:50:50 PM PDT 24
Finished Jul 05 05:50:54 PM PDT 24
Peak memory 209272 kb
Host smart-cc5b9884-1b58-47e6-8b20-4675bcf7ff2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228526702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.228526702
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.2077541927
Short name T479
Test name
Test status
Simulation time 246389502 ps
CPU time 0.86 seconds
Started Jul 05 05:50:55 PM PDT 24
Finished Jul 05 05:50:58 PM PDT 24
Peak memory 198588 kb
Host smart-67ba0e30-4e80-4c93-868b-2967ff24546a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077541927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_c
m_ctrl_config_regwen.2077541927
Directory /workspace/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1420023493
Short name T823
Test name
Test status
Simulation time 869906160 ps
CPU time 3.09 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:04 PM PDT 24
Peak memory 200908 kb
Host smart-76a581b2-0dc2-4dc2-856a-8259666ba7ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420023493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1420023493
Directory /workspace/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1871763582
Short name T412
Test name
Test status
Simulation time 1385602817 ps
CPU time 2.34 seconds
Started Jul 05 05:50:47 PM PDT 24
Finished Jul 05 05:50:50 PM PDT 24
Peak memory 200660 kb
Host smart-8e5eba40-e9d0-45a0-bf3f-0c2e973d952b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871763582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1871763582
Directory /workspace/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2542011470
Short name T259
Test name
Test status
Simulation time 86643464 ps
CPU time 0.9 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:50:56 PM PDT 24
Peak memory 199284 kb
Host smart-08fa123b-05ad-40ce-b3c1-9957767493d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542011470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2542011470
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.722879812
Short name T469
Test name
Test status
Simulation time 198176409 ps
CPU time 0.62 seconds
Started Jul 05 05:50:57 PM PDT 24
Finished Jul 05 05:50:59 PM PDT 24
Peak memory 198280 kb
Host smart-4c4bf449-16ef-492a-9080-573dfe660cc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722879812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.722879812
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all.241935493
Short name T515
Test name
Test status
Simulation time 2237524124 ps
CPU time 4.55 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:08 PM PDT 24
Peak memory 201052 kb
Host smart-cbf2629f-75d9-4646-a1ec-f1ff8b9226ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241935493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.241935493
Directory /workspace/6.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all_with_rand_reset.3656938885
Short name T522
Test name
Test status
Simulation time 3328448311 ps
CPU time 10.72 seconds
Started Jul 05 05:51:02 PM PDT 24
Finished Jul 05 05:51:15 PM PDT 24
Peak memory 201128 kb
Host smart-87bf8b6b-7cd9-47de-b461-4694a884c3e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656938885 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all_with_rand_reset.3656938885
Directory /workspace/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup.688996346
Short name T295
Test name
Test status
Simulation time 232415089 ps
CPU time 0.87 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 199400 kb
Host smart-1dde37b6-7d5f-45e0-9344-7b4f7b4f9528
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688996346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.688996346
Directory /workspace/6.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup_reset.4191574306
Short name T452
Test name
Test status
Simulation time 430855682 ps
CPU time 1.11 seconds
Started Jul 05 05:50:56 PM PDT 24
Finished Jul 05 05:50:59 PM PDT 24
Peak memory 200756 kb
Host smart-e397c4e4-5bc0-4f5d-bced-e975db54656e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191574306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.4191574306
Directory /workspace/6.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.1854376657
Short name T826
Test name
Test status
Simulation time 106037989 ps
CPU time 0.78 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:01 PM PDT 24
Peak memory 198740 kb
Host smart-deb82f7a-3b93-437a-a0b1-bb9e5cc55213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854376657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.1854376657
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.3561727906
Short name T466
Test name
Test status
Simulation time 69458743 ps
CPU time 0.82 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:03 PM PDT 24
Peak memory 198856 kb
Host smart-eca7e996-2b3f-4a44-9020-b1adfec80637
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561727906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.3561727906
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.818369444
Short name T533
Test name
Test status
Simulation time 32436364 ps
CPU time 0.68 seconds
Started Jul 05 05:51:30 PM PDT 24
Finished Jul 05 05:51:31 PM PDT 24
Peak memory 197788 kb
Host smart-7ca4e19a-f293-496a-8ebf-d18e22c7b755
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818369444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_m
alfunc.818369444
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.2703228838
Short name T424
Test name
Test status
Simulation time 1648892911 ps
CPU time 0.99 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:02 PM PDT 24
Peak memory 197808 kb
Host smart-d374f282-c2b6-4151-9fcd-e60b277a186c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703228838 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.2703228838
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.3058510235
Short name T265
Test name
Test status
Simulation time 44312410 ps
CPU time 0.62 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:09 PM PDT 24
Peak memory 197808 kb
Host smart-1dd4362b-b434-436c-8752-46ab6f969b5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058510235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.3058510235
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.2681098449
Short name T775
Test name
Test status
Simulation time 48641473 ps
CPU time 0.64 seconds
Started Jul 05 05:50:58 PM PDT 24
Finished Jul 05 05:51:00 PM PDT 24
Peak memory 197796 kb
Host smart-2f665b56-dfdf-4c73-b38a-dafa02afd5a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681098449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.2681098449
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.1315462282
Short name T806
Test name
Test status
Simulation time 117075066 ps
CPU time 0.72 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:50:57 PM PDT 24
Peak memory 201132 kb
Host smart-024143a7-c959-4ee1-9ffe-eec0401d8dd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315462282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.1315462282
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.1564188182
Short name T260
Test name
Test status
Simulation time 177313327 ps
CPU time 0.75 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:04 PM PDT 24
Peak memory 198072 kb
Host smart-ef4f21e4-b8d8-4a14-bc89-600dbe4f6c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564188182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wa
keup_race.1564188182
Directory /workspace/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.2883779341
Short name T363
Test name
Test status
Simulation time 46198430 ps
CPU time 0.72 seconds
Started Jul 05 05:51:03 PM PDT 24
Finished Jul 05 05:51:06 PM PDT 24
Peak memory 198836 kb
Host smart-3ae6c44f-5df1-41f5-956e-927f7505364c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883779341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.2883779341
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.2969799256
Short name T431
Test name
Test status
Simulation time 105496440 ps
CPU time 0.9 seconds
Started Jul 05 05:50:56 PM PDT 24
Finished Jul 05 05:50:59 PM PDT 24
Peak memory 209328 kb
Host smart-a73c93a9-bf58-4697-a765-fbe7baa5a3cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969799256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.2969799256
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.3472498062
Short name T353
Test name
Test status
Simulation time 296812538 ps
CPU time 1.12 seconds
Started Jul 05 05:51:05 PM PDT 24
Finished Jul 05 05:51:08 PM PDT 24
Peak memory 200564 kb
Host smart-9550f4f6-7389-4323-be42-dd7f96f0e1a6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472498062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_c
m_ctrl_config_regwen.3472498062
Directory /workspace/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2536907817
Short name T883
Test name
Test status
Simulation time 786722838 ps
CPU time 2.79 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:50:59 PM PDT 24
Peak memory 200880 kb
Host smart-d4329e22-c6f7-4ce3-96f0-848317e8bb2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536907817 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2536907817
Directory /workspace/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3451105327
Short name T779
Test name
Test status
Simulation time 75142678 ps
CPU time 0.95 seconds
Started Jul 05 05:50:58 PM PDT 24
Finished Jul 05 05:51:00 PM PDT 24
Peak memory 199164 kb
Host smart-f7c6fe37-4e88-4ea7-a2d6-b0910f0bd1df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451105327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3451105327
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.3523235599
Short name T718
Test name
Test status
Simulation time 59005987 ps
CPU time 0.65 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:03 PM PDT 24
Peak memory 198304 kb
Host smart-7968c9be-3a2f-410c-8df6-0f3ee0daf9b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523235599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.3523235599
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all.1245459103
Short name T852
Test name
Test status
Simulation time 1405181964 ps
CPU time 4.19 seconds
Started Jul 05 05:50:56 PM PDT 24
Finished Jul 05 05:51:01 PM PDT 24
Peak memory 200852 kb
Host smart-0858cfed-4a87-40df-87cf-fcf662e747f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245459103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.1245459103
Directory /workspace/7.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all_with_rand_reset.1030495053
Short name T496
Test name
Test status
Simulation time 10044555556 ps
CPU time 18.75 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:19 PM PDT 24
Peak memory 201140 kb
Host smart-4547de64-ac6e-4e9e-8312-ab124d7018f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030495053 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all_with_rand_reset.1030495053
Directory /workspace/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup.1173974447
Short name T741
Test name
Test status
Simulation time 453635259 ps
CPU time 1.06 seconds
Started Jul 05 05:50:51 PM PDT 24
Finished Jul 05 05:50:55 PM PDT 24
Peak memory 199680 kb
Host smart-e1cd9a58-ac5c-4887-bc09-c7a4db716a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173974447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.1173974447
Directory /workspace/7.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup_reset.3644429379
Short name T425
Test name
Test status
Simulation time 339157211 ps
CPU time 1.09 seconds
Started Jul 05 05:51:08 PM PDT 24
Finished Jul 05 05:51:11 PM PDT 24
Peak memory 200012 kb
Host smart-5f69f1e8-b64f-4ade-89a1-087e30a3e8e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644429379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.3644429379
Directory /workspace/7.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.1428729147
Short name T901
Test name
Test status
Simulation time 31470733 ps
CPU time 1.03 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:08 PM PDT 24
Peak memory 200740 kb
Host smart-63a07418-62d6-4e5c-8699-421a642c4ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428729147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.1428729147
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.2156153235
Short name T977
Test name
Test status
Simulation time 49938284 ps
CPU time 0.83 seconds
Started Jul 05 05:50:52 PM PDT 24
Finished Jul 05 05:50:56 PM PDT 24
Peak memory 198920 kb
Host smart-8a1cdb30-2755-414f-bad0-4247da950a88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156153235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.2156153235
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1527659202
Short name T430
Test name
Test status
Simulation time 39216365 ps
CPU time 0.64 seconds
Started Jul 05 05:50:56 PM PDT 24
Finished Jul 05 05:50:58 PM PDT 24
Peak memory 197780 kb
Host smart-af908bab-949f-4186-abbb-9923651c0ea5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527659202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.1527659202
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.4149873094
Short name T346
Test name
Test status
Simulation time 311275920 ps
CPU time 0.97 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:04 PM PDT 24
Peak memory 198164 kb
Host smart-2464227a-347d-4e85-9703-e718a8e52288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149873094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.4149873094
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.493477916
Short name T350
Test name
Test status
Simulation time 72479975 ps
CPU time 0.62 seconds
Started Jul 05 05:51:05 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 197836 kb
Host smart-831d2e4f-571b-4640-92aa-5c84dc2b7cf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493477916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.493477916
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.4061683561
Short name T575
Test name
Test status
Simulation time 27227082 ps
CPU time 0.59 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:08 PM PDT 24
Peak memory 197752 kb
Host smart-b61b3809-497e-4ec3-bba4-df82ea516b3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061683561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.4061683561
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.770030808
Short name T361
Test name
Test status
Simulation time 75150470 ps
CPU time 0.65 seconds
Started Jul 05 05:50:57 PM PDT 24
Finished Jul 05 05:50:59 PM PDT 24
Peak memory 201048 kb
Host smart-2ad31bb6-df3e-4eb9-af35-264058dfb0c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770030808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid
.770030808
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.1899171585
Short name T278
Test name
Test status
Simulation time 293310205 ps
CPU time 1.03 seconds
Started Jul 05 05:52:59 PM PDT 24
Finished Jul 05 05:53:00 PM PDT 24
Peak memory 199460 kb
Host smart-1f4fb829-ecb0-4e6b-a11a-522b8fc7660e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899171585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wa
keup_race.1899171585
Directory /workspace/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.2333213588
Short name T110
Test name
Test status
Simulation time 107264823 ps
CPU time 0.72 seconds
Started Jul 05 05:50:58 PM PDT 24
Finished Jul 05 05:51:00 PM PDT 24
Peak memory 198240 kb
Host smart-fc37f6d4-a62f-4a8a-9902-1d3922ba81db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333213588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2333213588
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.2037401936
Short name T843
Test name
Test status
Simulation time 248193265 ps
CPU time 0.77 seconds
Started Jul 05 05:50:56 PM PDT 24
Finished Jul 05 05:50:58 PM PDT 24
Peak memory 209296 kb
Host smart-bdc15cf2-e44b-46b6-bc38-cca4bf9ef45a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037401936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.2037401936
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.1007322777
Short name T655
Test name
Test status
Simulation time 196755043 ps
CPU time 0.8 seconds
Started Jul 05 05:50:58 PM PDT 24
Finished Jul 05 05:51:01 PM PDT 24
Peak memory 198912 kb
Host smart-2434d19f-865f-4dd8-b1cd-4cc9cf688f75
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007322777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_c
m_ctrl_config_regwen.1007322777
Directory /workspace/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2012890122
Short name T181
Test name
Test status
Simulation time 899721043 ps
CPU time 3.22 seconds
Started Jul 05 05:51:08 PM PDT 24
Finished Jul 05 05:51:13 PM PDT 24
Peak memory 200812 kb
Host smart-eb926c6b-8401-49f5-ac9e-09c84b798938
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012890122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2012890122
Directory /workspace/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2161801175
Short name T919
Test name
Test status
Simulation time 859184458 ps
CPU time 3.35 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:11 PM PDT 24
Peak memory 200900 kb
Host smart-40d51ecb-7ed3-4dda-a552-6c58acc80260
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161801175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2161801175
Directory /workspace/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1754261036
Short name T286
Test name
Test status
Simulation time 66937030 ps
CPU time 0.83 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:04 PM PDT 24
Peak memory 199100 kb
Host smart-d72af47c-07ff-40b0-90f1-2c450a487908
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754261036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1754261036
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.1603455391
Short name T9
Test name
Test status
Simulation time 32960397 ps
CPU time 0.71 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:04 PM PDT 24
Peak memory 198356 kb
Host smart-fc4d7c78-09f7-4432-abba-8e1b7bd5fe9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603455391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.1603455391
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all.1665225576
Short name T125
Test name
Test status
Simulation time 1300766957 ps
CPU time 3.51 seconds
Started Jul 05 05:51:03 PM PDT 24
Finished Jul 05 05:51:09 PM PDT 24
Peak memory 200932 kb
Host smart-56b70ce5-c1cf-4478-b167-b8f1540690c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665225576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.1665225576
Directory /workspace/8.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all_with_rand_reset.3421672296
Short name T553
Test name
Test status
Simulation time 14856276507 ps
CPU time 20.36 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:51:16 PM PDT 24
Peak memory 201192 kb
Host smart-4c1586b0-c5f0-408a-9388-fcea09dc56af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421672296 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all_with_rand_reset.3421672296
Directory /workspace/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup.3413973880
Short name T851
Test name
Test status
Simulation time 268469598 ps
CPU time 0.99 seconds
Started Jul 05 05:51:03 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 199400 kb
Host smart-6645455d-245f-4956-b1f3-7e8db846c3af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413973880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.3413973880
Directory /workspace/8.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup_reset.731622892
Short name T691
Test name
Test status
Simulation time 321709676 ps
CPU time 0.91 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:04 PM PDT 24
Peak memory 199900 kb
Host smart-d27bace4-e12b-4c00-9dfa-caa82dd7fd80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731622892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.731622892
Directory /workspace/8.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.4073859264
Short name T518
Test name
Test status
Simulation time 78770005 ps
CPU time 0.73 seconds
Started Jul 05 05:51:02 PM PDT 24
Finished Jul 05 05:51:05 PM PDT 24
Peak memory 198512 kb
Host smart-4e52b579-4735-4169-aa12-470749aab62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073859264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.4073859264
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.902968107
Short name T176
Test name
Test status
Simulation time 78336070 ps
CPU time 0.72 seconds
Started Jul 05 05:51:05 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 198868 kb
Host smart-6eaecae6-9ac9-445a-bea0-899a64536a3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902968107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disab
le_rom_integrity_check.902968107
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.2879008802
Short name T391
Test name
Test status
Simulation time 50392213 ps
CPU time 0.58 seconds
Started Jul 05 05:50:58 PM PDT 24
Finished Jul 05 05:51:00 PM PDT 24
Peak memory 197076 kb
Host smart-0051ca42-aa61-46ce-8686-e4c09b8e079f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879008802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.2879008802
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.3054574131
Short name T631
Test name
Test status
Simulation time 316854611 ps
CPU time 1.03 seconds
Started Jul 05 05:51:15 PM PDT 24
Finished Jul 05 05:51:17 PM PDT 24
Peak memory 198160 kb
Host smart-323874a2-de8c-4e12-ac3d-1c9da27317b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054574131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.3054574131
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.1090318067
Short name T668
Test name
Test status
Simulation time 83021685 ps
CPU time 0.63 seconds
Started Jul 05 05:51:15 PM PDT 24
Finished Jul 05 05:51:16 PM PDT 24
Peak memory 197124 kb
Host smart-bc00f80a-dfb2-4635-9119-f53d2e0dfa9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090318067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.1090318067
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.779694910
Short name T997
Test name
Test status
Simulation time 74558850 ps
CPU time 0.65 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:04 PM PDT 24
Peak memory 198148 kb
Host smart-ce1f3efe-877a-4f51-b74b-3c2ce0ff5d72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779694910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.779694910
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.4197727096
Short name T119
Test name
Test status
Simulation time 68182677 ps
CPU time 0.65 seconds
Started Jul 05 05:51:01 PM PDT 24
Finished Jul 05 05:51:04 PM PDT 24
Peak memory 200936 kb
Host smart-4c09bf7b-c14e-4175-b8e0-b05faf4def2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197727096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.4197727096
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.2629562905
Short name T895
Test name
Test status
Simulation time 41474705 ps
CPU time 0.71 seconds
Started Jul 05 05:51:00 PM PDT 24
Finished Jul 05 05:51:03 PM PDT 24
Peak memory 198256 kb
Host smart-a99c8d64-bf47-4089-8669-11f3b70325b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629562905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wa
keup_race.2629562905
Directory /workspace/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.1271261518
Short name T271
Test name
Test status
Simulation time 69742081 ps
CPU time 0.7 seconds
Started Jul 05 05:51:11 PM PDT 24
Finished Jul 05 05:51:12 PM PDT 24
Peak memory 198864 kb
Host smart-aeec45aa-7962-4c76-88c7-69ecd2bf8e41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271261518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.1271261518
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.1255550176
Short name T401
Test name
Test status
Simulation time 168693521 ps
CPU time 0.81 seconds
Started Jul 05 05:51:05 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 209376 kb
Host smart-c78fe84b-e2b1-4722-b504-930881ee8f13
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255550176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.1255550176
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3033940185
Short name T444
Test name
Test status
Simulation time 119846282 ps
CPU time 0.79 seconds
Started Jul 05 05:51:05 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 198540 kb
Host smart-f5281e59-9ce2-490e-80db-b6a9902e141f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033940185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_c
m_ctrl_config_regwen.3033940185
Directory /workspace/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4221931205
Short name T672
Test name
Test status
Simulation time 759163925 ps
CPU time 3 seconds
Started Jul 05 05:51:06 PM PDT 24
Finished Jul 05 05:51:10 PM PDT 24
Peak memory 200896 kb
Host smart-f3c189bc-d3b3-4d0a-bd8d-8d442fa37289
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221931205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4221931205
Directory /workspace/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1190181242
Short name T853
Test name
Test status
Simulation time 838575010 ps
CPU time 3.42 seconds
Started Jul 05 05:50:59 PM PDT 24
Finished Jul 05 05:51:04 PM PDT 24
Peak memory 200864 kb
Host smart-6ca2725c-4a0e-4a21-bfa1-c8d8586b43c3
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190181242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1190181242
Directory /workspace/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2122941161
Short name T214
Test name
Test status
Simulation time 72293780 ps
CPU time 0.85 seconds
Started Jul 05 05:51:04 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 198868 kb
Host smart-a0e83681-9cda-41f5-9b8a-cc3f91d7371e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122941161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2122941161
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.764080796
Short name T789
Test name
Test status
Simulation time 46539184 ps
CPU time 0.65 seconds
Started Jul 05 05:51:02 PM PDT 24
Finished Jul 05 05:51:05 PM PDT 24
Peak memory 199140 kb
Host smart-ebc67d83-4646-4a58-b8d1-e589b4c27535
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764080796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.764080796
Directory /workspace/9.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all.2914531633
Short name T966
Test name
Test status
Simulation time 2849914838 ps
CPU time 4.63 seconds
Started Jul 05 05:51:03 PM PDT 24
Finished Jul 05 05:51:10 PM PDT 24
Peak memory 201004 kb
Host smart-61916f14-e844-41c4-a8ac-af59848d81fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914531633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.2914531633
Directory /workspace/9.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all_with_rand_reset.2967593200
Short name T527
Test name
Test status
Simulation time 10126889535 ps
CPU time 24.8 seconds
Started Jul 05 05:50:58 PM PDT 24
Finished Jul 05 05:51:25 PM PDT 24
Peak memory 201132 kb
Host smart-82bc28b8-310e-45a0-a0b7-92923b927a2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967593200 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all_with_rand_reset.2967593200
Directory /workspace/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup.3068486508
Short name T943
Test name
Test status
Simulation time 133296344 ps
CPU time 0.79 seconds
Started Jul 05 05:52:58 PM PDT 24
Finished Jul 05 05:52:59 PM PDT 24
Peak memory 198136 kb
Host smart-5a7be1dc-d621-4cdd-a2f7-d8ce03f2f8f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068486508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.3068486508
Directory /workspace/9.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup_reset.3475076490
Short name T102
Test name
Test status
Simulation time 424902331 ps
CPU time 1.09 seconds
Started Jul 05 05:51:03 PM PDT 24
Finished Jul 05 05:51:07 PM PDT 24
Peak memory 200072 kb
Host smart-07931e66-b52f-40de-9076-2972517fcd26
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475076490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.3475076490
Directory /workspace/9.pwrmgr_wakeup_reset/latest
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