Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32465

1

T1

11

T3

20

T6

58

auto[1]

31019

1

T1

5

T3

10

T6

42

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32566

1

T1

6

T3

8

T6

34

auto[1]

30918

1

T1

10

T3

22

T6

66

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31138

1

T1

13

T3

12

T6

52

auto[1]

32346

1

T1

3

T3

18

T6

48

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35860

1

T1

9

T3

15

T6

50

auto[1]

27624

1

T1

7

T3

15

T6

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31103

1

T1

6

T3

14

T6

42

auto[1]

32381

1

T1

10

T3

16

T6

58

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32179

1

T1

9

T3

10

T6

58

auto[1]

31305

1

T1

7

T3

20

T6

42

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1108

1

T6

3

T10

2

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

846

1

T6

3

T10

2

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1064

1

T10

1

T39

2

T12

5

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

796

1

T10

1

T39

2

T12

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1068

1

T1

1

T6

1

T9

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

790

1

T1

1

T6

1

T9

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1820

1

T6

1

T9

2

T37

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1601

1

T6

1

T9

2

T37

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1090

1

T1

1

T7

2

T9

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

818

1

T1

1

T7

2

T9

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1140

1

T3

2

T6

3

T7

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

883

1

T3

2

T6

3

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1115

1

T6

1

T37

2

T38

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

853

1

T6

1

T37

2

T38

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1094

1

T3

1

T9

3

T37

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

836

1

T3

1

T9

3

T37

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1141

1

T1

1

T3

1

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

859

1

T1

1

T3

1

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1098

1

T3

1

T6

1

T10

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

828

1

T3

1

T6

1

T10

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1091

1

T1

1

T3

1

T6

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

853

1

T1

1

T3

1

T6

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1080

1

T3

1

T6

7

T21

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

812

1

T3

1

T6

7

T38

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1129

1

T3

1

T6

3

T9

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

864

1

T3

1

T6

3

T9

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1088

1

T1

1

T6

2

T7

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

827

1

T6

2

T7

2

T37

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1142

1

T1

1

T3

1

T6

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

886

1

T1

1

T3

1

T6

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1055

1

T3

1

T6

2

T9

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

790

1

T3

1

T6

2

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1068

1

T6

3

T7

1

T9

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

809

1

T6

3

T7

1

T9

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1129

1

T10

1

T37

1

T39

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

873

1

T10

1

T37

1

T39

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1099

1

T6

2

T7

1

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

832

1

T6

2

T7

1

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1039

1

T6

1

T9

1

T39

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

808

1

T6

1

T9

1

T39

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1157

1

T3

1

T6

1

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

906

1

T3

1

T6

1

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1140

1

T7

1

T37

1

T39

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

888

1

T7

1

T37

1

T39

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1056

1

T6

1

T9

2

T10

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

848

1

T6

1

T9

2

T10

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1129

1

T1

1

T9

1

T10

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

863

1

T1

1

T9

1

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1058

1

T1

1

T6

1

T38

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

807

1

T6

1

T38

1

T39

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1073

1

T6

1

T7

1

T21

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

818

1

T6

1

T7

1

T21

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1124

1

T1

1

T6

2

T39

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

843

1

T1

1

T6

2

T39

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1098

1

T3

1

T6

3

T12

8

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

846

1

T3

1

T6

3

T12

7

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1096

1

T6

1

T9

1

T10

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

850

1

T6

1

T9

1

T10

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1057

1

T3

1

T6

2

T10

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

795

1

T3

1

T6

2

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1088

1

T3

1

T6

2

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

844

1

T3

1

T6

2

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1126

1

T3

1

T6

1

T39

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

852

1

T3

1

T6

1

T39

3