Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32606 1 T1 2 T2 3 T3 2
auto[1] 31324 1 T1 2 T2 3 T4 6


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32736 1 T1 2 T2 4 T3 2
auto[1] 31194 1 T1 2 T2 2 T4 9


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31253 1 T2 2 T4 10 T5 4
auto[1] 32677 1 T1 4 T2 4 T3 2


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35947 1 T1 2 T2 4 T3 1
auto[1] 27983 1 T1 2 T2 2 T3 1


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31275 1 T2 1 T4 7 T5 2
auto[1] 32655 1 T1 4 T2 5 T3 2


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32584 1 T1 4 T2 5 T3 2
auto[1] 31346 1 T2 1 T4 7 T5 4


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1126 1 T4 2 T9 1 T16 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 871 1 T9 1 T20 2 T40 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1068 1 T6 1 T9 2 T27 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 850 1 T6 1 T9 2 T27 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1066 1 T2 1 T4 2 T9 3
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 816 1 T2 1 T9 3 T27 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1778 1 T3 1 T9 2 T16 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1545 1 T3 1 T9 2 T27 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1096 1 T9 3 T27 1 T46 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 879 1 T9 3 T27 1 T46 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1080 1 T9 1 T27 1 T47 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 826 1 T9 1 T27 1 T47 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1151 1 T9 2 T46 1 T40 3
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 887 1 T9 2 T46 1 T40 3
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1115 1 T2 1 T16 1 T27 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 862 1 T27 1 T41 1 T67 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1083 1 T9 1 T17 1 T40 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 832 1 T9 1 T40 2 T86 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1102 1 T4 1 T9 2 T16 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 850 1 T9 2 T47 1 T40 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1121 1 T6 1 T9 2 T16 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 864 1 T9 2 T41 3 T62 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1070 1 T1 1 T4 1 T9 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 809 1 T1 1 T9 3 T20 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1102 1 T4 2 T9 2 T16 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 853 1 T9 2 T27 1 T47 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1115 1 T9 1 T40 1 T41 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 869 1 T9 1 T40 1 T41 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1133 1 T4 1 T9 2 T27 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 876 1 T9 2 T27 1 T47 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1090 1 T5 1 T9 2 T16 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 821 1 T5 1 T9 2 T40 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1060 1 T40 1 T41 3 T177 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 828 1 T40 1 T41 3 T177 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1106 1 T2 1 T47 2 T40 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 860 1 T47 2 T40 1 T41 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1086 1 T9 3 T16 1 T27 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 860 1 T9 3 T27 1 T46 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1111 1 T1 1 T40 6 T41 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 863 1 T1 1 T40 6 T41 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1050 1 T4 1 T9 1 T16 2
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 818 1 T9 1 T40 1 T41 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1145 1 T9 4 T27 1 T41 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 891 1 T9 4 T27 1 T41 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1150 1 T9 2 T20 1 T41 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 884 1 T9 2 T20 1 T41 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1125 1 T4 1 T5 1 T9 3
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 883 1 T5 1 T9 3 T27 2
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1112 1 T5 1 T9 2 T47 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 870 1 T5 1 T9 2 T47 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1163 1 T4 1 T9 1 T16 2
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 917 1 T9 1 T46 1 T40 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1101 1 T4 1 T5 1 T20 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 845 1 T5 1 T20 1 T47 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1102 1 T2 1 T5 1 T6 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 849 1 T2 1 T5 1 T6 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1068 1 T9 1 T20 1 T40 3
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 810 1 T9 1 T20 1 T40 3
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1114 1 T9 2 T16 1 T47 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 861 1 T9 2 T40 1 T84 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1109 1 T4 1 T16 2 T40 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 846 1 T40 1 T41 1 T67 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1049 1 T4 1 T9 1 T40 3
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 788 1 T9 1 T40 3 T41 2

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